CN104749511B - The description method of trap resistance - Google Patents
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- CN104749511B CN104749511B CN201310752999.0A CN201310752999A CN104749511B CN 104749511 B CN104749511 B CN 104749511B CN 201310752999 A CN201310752999 A CN 201310752999A CN 104749511 B CN104749511 B CN 104749511B
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000012360 testing method Methods 0.000 claims description 12
- 238000000605 extraction Methods 0.000 claims description 6
- 238000011156 evaluation Methods 0.000 abstract description 6
- 238000000407 epitaxy Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 238000012512 characterization method Methods 0.000 description 1
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Abstract
Method is described the invention discloses a kind of trap resistance, on the basis of conventional trap resistance is evaluated, the buried regions current potential of trap resistance is raised, trap resistance is changed, in the evaluation procedure that buried regions current potential is included in trap resistance to the influence factor of trap resistance, trap resistance can more accurately be described.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit design, in particular to a well resistor description method.
Background
Analog circuit design requires not only high resistance accuracy, but also accurate resistance parameters to correctly describe resistance performance. At present, the evaluation of the trap resistance adopts a conventional resistance evaluation method, namely a two-end resistance method, the influence on a buried layer is neglected, and the resistance parameter extraction characterization formula is as follows:
R(V)＝R0*(1+VC1*(n1n2)+VC2*(n1n2)2)
however, in practical circuit applications, a high potential is often required to be added to the buried layer, and different potentials loaded on the buried layer greatly affect the resistance of the well resistor. The buried layer potential is particularly important for extracting the voltage parameter of the conventional well resistor, and the accurate voltage dependency coefficient provides a more accurate well resistor for circuit application. Therefore, the introduction of the buried layer voltage dependency coefficient in the well resistance evaluation is the key point.
Disclosure of Invention
The invention aims to provide a well resistance description method, which can accurately calculate the well resistance.
In order to solve the above problems, the well resistor according to the present invention is described by the following formula:
wherein,
F1(V(n1，n2))＝1+VC1*V(n1，n2)+VC2*V(n1，n2)2；
F2(V(n2，n3))＝1+VC3*V(n2，n3)+VC4*V(n2，n3)2；
F3(V(n2，n3))＝1+VC5*V(n2，n3)+VC6*V(n2，n3)2；
F4(V(n2，n3))＝1+VC7*V(n2，n3)+VC8*V(n2，n3)2；
in the formula, V (n1, n2) represents the voltage between two nodes of n1 and n2, V (n2, n3) represents the voltage between two nodes of n2 and n3, L represents the resistance length, W represents the resistance width, dl represents the deviation of the resistance length caused by process errors, dw represents the deviation of the resistance width caused by process errors, R0 represents the resistance of a well resistor square, VC1 and VC2 are first-order and second-order voltage coefficients of a conventional well resistor, VC3 and VC4 are first-order and second-order voltage coefficients extracted by a buried layer voltage influencing the well resistor, VC5 and VC6 are first-order and second-order voltage coefficients influencing the well resistor length by the buried layer voltage raising, and VC7 and VC8 are first-order and second-order voltage coefficients influencing the well resistor width by the buried layer voltage raising; VC 1-VC 8 are trap resistance coefficients.
The trap resistivity extraction method comprises the following steps:
a) when the potential of the buried layer under the trap is 0 potential, extracting trap resistance coefficients dl, dw, VC1, VC2 and R0 through an R (V) calculation formula;
b) when the potential of a buried layer under a trap is raised, selecting trap resistance test values under 3-5 different buried layer voltages, selecting a trap resistor with the length and width both larger than 10 mu m, and removing the influence of 2dw and 2dl in an R (V) calculation formula through an R (V) calculation formula because the resistor width and the resistor length are large, and extracting trap resistance coefficients VC3 and VC 4;
c) selecting trap resistance test values of 3-5 different buried layer voltages, selecting a group of trap resistances with the same length and the width of more than 10 mu m and different widths through an R (V) calculation formula, and extracting trap resistance coefficients VC7 and VC 8;
d) selecting trap resistance test values of 3-5 different buried layer voltages, selecting a group of trap resistances with the same width and the length of more than 10 mu m and extracting trap resistance coefficients VC5 and VC6 through an R (V) calculation formula.
On the basis of conventional well resistance evaluation, the invention arranges the influence factors of the potential of the buried layer under the well on the well resistance into an evaluation system of the well resistance, so that the influence of the potential of the buried layer on the well resistance can be accurately calculated, and more accurate well resistance value is provided for circuit application.
Drawings
Fig. 1 is a schematic diagram of a P-well structure.
Detailed Description
The trap resistor is described by the following formula:
wherein,
F1(V(n1，n2))＝1+VC1*V(n1，n2)+VC2*V(n1，n2)2；
F2(V(n2，n3))＝1+VC3*V(n2，n3)+VC4*V(n2，n3)2；
F3(V(n2，n3))＝1+VC5*V(n2，n3)+VC6*V(n2，n3)2；
F4(V(n2，n3))＝1+VC7*V(n2，n3)+VC8*V(n2，n3)2；
in the formula, V (n1, n2) represents the voltage between two nodes of n1 and n2, V (n2, n3) represents the voltage between two nodes of n2 and n3, L represents the resistance length, W represents the resistance width, dl represents the deviation of the resistance length caused by process errors, dw represents the deviation of the resistance width caused by process errors, R0 represents the resistance of a well resistor square, VC1 and VC2 are first-order and second-order voltage coefficients of a conventional well resistor, VC3 and VC4 are first-order and second-order voltage coefficients extracted by a buried layer voltage influencing the well resistor, VC5 and VC6 are first-order and second-order voltage coefficients influencing the well resistor length by the buried layer voltage raising, and VC7 and VC8 are first-order and second-order voltage coefficients influencing the well resistor width by the buried layer voltage raising; VC 1-VC 8 are trap resistivity. The trap resistivity extraction method comprises the following steps:
a) when the potential of the buried layer under the trap is 0 potential, extracting trap resistance coefficients dl, dw, VC1, VC2 and R0 through an R (V) calculation formula;
b) when the potential of a buried layer under a trap is raised, selecting trap resistance test values under 3-5 different buried layer voltages, selecting trap resistances with the resistance length and width larger than 10 microns, such as trap resistances with W/L =20/20, and removing the influences of 2dw and 2dl in the R (V) calculation formula through an R (V) calculation formula due to the fact that the resistance width and length are large, and extracting trap resistance coefficients VC3 and VC 4;
c) selecting well resistance test values of 3-5 different buried layer voltages, selecting a group of well resistances with the same length and more than 10 μm and different widths, such as well resistances of W/L =0.2/20, W/L =1/20, W/L =2/20, W/L =5/20, W/L =10/20 and W/L =20/20, and extracting well resistance coefficients VC7 and VC8 by an R (V) calculation formula;
d) selecting well resistance test values of 3-5 different buried layer voltages, selecting a group of well resistances with the same width and larger than 10 mu m and different lengths, such as W/L =20/5, W/L =20/10 and W/L =20/20, and extracting well resistance coefficients VC5 and VC6 by an R (V) calculation formula.
The above description is a well resistance description method of the present invention, and is specifically described as follows with reference to an embodiment:
taking a P-type well resistor as an example, the structure of the P-type well resistor is shown in fig. 1, the P-type well and a P-type substrate are separated by an N-type epitaxial layer (N-EPI) and an N-type buried layer (NBL), two ends of the well resistor are respectively connected to two contact PADs (N1, N2), and simultaneously, the leading-out 1 end of the N-type buried layer is connected to 1 contact PAD (N3).
In the application of the analog circuit, different potentials are required to be applied to the buried layer end according to different application requirements. With the rising of the potential of the buried layer, a PN junction formed by the P well and the N type epitaxy enters a reverse bias state, a depletion region is formed at the PN junction, and the current path of the P well resistor is narrowed due to the widening of the depletion region at the side of the P well, so that the resistance value of the P well resistor is increased. The invention takes the influence factor of the buried layer potential on the trap resistance into consideration, and extracts the resistance parameters R0, VC 1-VC 8, dL and dW through the formula 1. The invention considers the influence of the potential of the buried layer on the voltage coefficient of the well resistor and the length and width dimensions of the well resistor.
In equation 1 above:
f1(V (n1, n2)) describes the well resistance voltage coefficient itself:
F1(V(n1,n2))=1+VC1*V(n1,n2)+VC2*V(n1,n2)2
f2(V (n2, n3)) describes the well voltage resistance coefficient introduced by the buried layer potential:
F2(V(n2,n3))=1+VC3*V(n2,n3)+VC4*V(n2,n3)2
f3(V (N2, N3)) describes the depletion of the PN junction of the P-well/N-type epitaxy due to the potential difference between the buried layer and the P-well, causing the variation of the well resistance length:
F3(V(n2,n3))=1+VC5*V(n2,n3)+VC6*V(n2,n3)2
f4(V (N2, N3)) describes the depletion of the PN junction of the P-well/N-type epitaxy due to the potential difference between the buried layer and the P-well, causing the variation of the well resistance width:
F4(V(n2,n3))=1+VC7*V(n2,n3)+VC8*V(n2,n3)2
the main extraction steps of the parameters of the trap resistance are as follows:
designing a set of well resistor structure arrays of different widths and lengths, as listed in the following table: (unit: μm)
| W | 20 | 10 | 5 | 2 | 1 | 0.5 | 20 | 20 |
| L | 20 | 20 | 20 | 20 | 20 | 20 | 10 | 5 |
When the N-type buried layer is at 0 potential, the well resistivity can be extracted by equation 1: dL, dW, VC1, VC2 and R0.
When the potential of the N-type buried layer is raised, well resistance test values when 3-5 different N-type buried layer voltages are selected, well resistance with a large size (W/L = 20/20) is selected and substituted into formula 1, and because the resistance width and the length are large, 2dW and 2dL influences can be removed at the moment, so that the well resistance coefficient can be extracted: VC3 and VC 4.
Selecting well resistance test values of 3-5 different N-type buried layer voltages, and extracting well resistance coefficients by using well resistances of a group of sizes of W/L =0.5/20, W/L =1/20, W/L =2/20, W/L =5/20, W/L =10/20 and W/L =20/20 according to formula 1: VC7 and VC 8.
Selecting trap resistance test values of 3-5 different NBL voltages, and extracting a trap resistance coefficient by using trap resistances of a group of sizes such as W/L =20/5, W/L =20/10 and W/L =20/20 according to formula 1: VC5 and VC 6.
In equation 1 above, in conjunction with FIG. 1:
n 1: a high potential end of a finger well resistor;
n 2: a low potential end of a finger well resistor;
n 3: a buried layer potential terminal;
l indicates the length of the resistor, W indicates the width of the resistor, and the unit is mum;
dl refers to the deviation of the resistance length caused by process errors, and dw refers to the deviation of the resistance width caused by process errors, and the unit is mum;
r0, which is the resistance of the trap resistor square with the unit of omega/□;
VC1, VC 2: the first-order and second-order voltage coefficients of the conventional trap resistor;
VC3, VC 4: the voltage of the buried layer influences the first-order and second-order voltage coefficients extracted by the well resistor;
VC5, VC 6: the first-order and second-order voltage coefficients which influence the length of the well resistor are raised by the voltage of the buried layer;
VC7, VC 8: the first order and second order voltage coefficients which affect the width of the trap resistor are raised by the buried layer voltage.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (2)
1. A method for describing well resistance, comprising: described using the following formula:
<mrow> <mi>R</mi> <mrow> <mo>(</mo> <mi>V</mi> <mo>)</mo> </mrow> <mo>=</mo> <mi>R</mi> <mn>0</mn> <mo>*</mo> <mi>F</mi> <mn>1</mn> <mrow> <mo>(</mo> <mi>V</mi> <mo>(</mo> <mrow> <mi>n</mi> <mn>1</mn> <mo>,</mo> <mi>n</mi> <mn>2</mn> </mrow> <mo>)</mo> <mo>)</mo> </mrow> <mo>*</mo> <mi>F</mi> <mn>2</mn> <mrow> <mo>(</mo> <mi>V</mi> <mo>(</mo> <mrow> <mi>n</mi> <mn>2</mn> <mo>,</mo> <mi>n</mi> <mn>3</mn> </mrow> <mo>)</mo> <mo>)</mo> </mrow> <mo>*</mo> <mfrac> <mrow> <mi>L</mi> <mo>-</mo> <mn>2</mn> <mi>d</mi> <mi>l</mi> <mo>*</mo> <mi>F</mi> <mn>3</mn> <mrow> <mo>(</mo> <mi>V</mi> <mo>(</mo> <mrow> <mi>n</mi> <mn>2</mn> <mo>,</mo> <mi>n</mi> <mn>3</mn> </mrow> <mo>)</mo> <mo>)</mo> </mrow> </mrow> <mrow> <mi>W</mi> <mo>-</mo> <mn>2</mn> <mi>d</mi> <mi>w</mi> <mo>*</mo> <mi>F</mi> <mn>4</mn> <mrow> <mo>(</mo> <mi>V</mi> <mo>(</mo> <mrow> <mi>n</mi> <mn>2</mn> <mo>,</mo> <mi>n</mi> <mn>3</mn> </mrow> <mo>)</mo> <mo>)</mo> </mrow> </mrow> </mfrac> </mrow>
wherein,
F1(V(n1,n2))＝1+VC1*V(n1,n2)+VC2*V(n1,n2)2；
F2(V(n2,n3))＝1+VC3*V(n2,n3)+VC4*V(n2,n3)2；
F3(V(n2,n3))＝1+VC5*V(n2,n3)+VC6*V(n2,n3)2；
F4(V(n2,n3))＝1+VC7*V(n2,n3)+VC8*V(n2,n3)2；
in the formula, V (n1, n2) represents the voltage between two nodes n1 and n2, and V (n2, n3) represents the voltage between two nodes n2 and n 3; n1 is a high potential end of a well resistor, n2 is a low potential end of the well resistor, and n3 is a buried potential end; l is the resistance length, W is the resistance width, dl is the resistance length deviation caused by process errors, dw is the resistance width deviation caused by process errors, R0 is the resistance value of a trap resistor square, VC1 and VC2 are first-order and second-order voltage coefficients of a conventional trap resistor, VC3 and VC4 are first-order and second-order voltage coefficients of a buried layer voltage influencing the extraction of the trap resistor, VC5 and VC6 are first-order and second-order voltage coefficients of the trap resistor length influenced by the buried layer voltage elevation, and VC7 and VC8 are first-order and second-order voltage coefficients of the trap resistor width influenced by the buried layer voltage elevation; VC 1-VC 8 are trap resistance coefficients.
2. The method for describing a well resistance according to claim 1, wherein: the trap resistivity extraction method comprises the following steps:
a) when the potential of the buried layer under the trap is 0 potential, extracting trap resistance coefficients dl, dw, VC1, VC2 and R0 through an R (V) calculation formula;
b) when the potential of a buried layer under a trap is raised, selecting trap resistance test values under 3-5 different buried layer voltages, selecting a trap resistor with the length and width both larger than 10 mu m, and removing the influence of 2dw and 2dl in an R (V) calculation formula through an R (V) calculation formula because the resistor width and the resistor length are large, and extracting trap resistance coefficients VC3 and VC 4;
c) selecting trap resistance test values of 3-5 different buried layer voltages, selecting a group of trap resistances with the same length and the width of more than 10 mu m and different widths through an R (V) calculation formula, and extracting trap resistance coefficients VC7 and VC 8;
d) selecting trap resistance test values of 3-5 different buried layer voltages, selecting a group of trap resistances with the same width and the length of more than 10 mu m and extracting trap resistance coefficients VC5 and VC6 through an R (V) calculation formula.
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