CN104735929B

CN104735929B - Circuit board processing method and equipment

Info

Publication number: CN104735929B
Application number: CN201310722833.4A
Authority: CN
Inventors: 刘宝林; 张静峰
Original assignee: Shennan Circuit Co Ltd
Current assignee: Shennan Circuit Co Ltd
Priority date: 2013-12-24
Filing date: 2013-12-24
Publication date: 2017-12-29
Anticipated expiration: 2033-12-24
Also published as: CN104735929A

Abstract

The embodiment of the present invention discloses circuit board processing method and circuit board processing device.Circuit board processing method includes：First line figure is formed on the first face of the first conductive base, if the first face is the hair side of the first conductive base, first line figure is based on plating conductive material in the first face and being formed；The second line pattern is formed on the second face of the second conductive base, if the second face is the hair side of the second conductive base, first line figure is based on plating conductive material in the second face and being formed；Prepreg is pressed between the first face of the first conductive base and the second face of the second conductive base to form the first board set；To the 3rd facet etch of the first conductive base in the first board set to expose first line figure, the fourth face of the second conductive base in the first board set is etched to expose the second line pattern.Scheme provided in an embodiment of the present invention is advantageous to improve PCB proof voltage energy on the premise of prepreg thickness in control PCB as far as possible.

Description

Circuit board processing method and equipment

Technical field

The present invention relates to circuit board processing and manufacturing technology, and in particular to circuit board processing method and circuit board processing are set It is standby.

Background technology

As electronic product appellative function is more and more, printed circuit board (PCB)（PCB, Printed circuit board）'s The number of plies also requires more and more, but PCB layer number is higher, its thickness it is thicker, it is necessary to assembly space it is also bigger, and this and electricity The requirement such as light, thin, short, small of sub- product is disagreed.

To reduce PCB thickness of slab, most manufacturers are mainly by reducing the usage quantity of prepreg in PCB come real It is existing, found in practice process, PCB dielectric thickness is reduced by reducing the usage quantity of prepreg, because circuit is deposited , if actually active dielectric thickness is too low in PCB, for having the PCB of high voltage withstanding requirement, it is pressure-resistant exist it is very big hidden Suffer from, and then big PCB job security may be had a strong impact on.

The content of the invention

The embodiment of the present invention provides circuit board processing method and circuit board processing device, with partly solid in control PCB as far as possible PCB proof voltage energy is improved on the premise of changing piece thickness.

First aspect present invention provides a kind of circuit board processing method, including：

First line figure is formed on the first face of the first conductive base, wherein, if first face is described first The smooth surface of conductive base, then the first line figure be based on first face being etched and/or plated conductive material and shape Into if first face is the hair side of first conductive base, the first line figure is based on plating in first face Conductive material and formed；

The second line pattern is formed on the second face of the second conductive base, wherein, if second face is described second The smooth surface of conductive base, then second line pattern be based on second face being etched and/or plated conductive material and shape Into if second face is the hair side of second conductive base, the first line figure is based on plating in second face Conductive material and formed；

By prepreg press to first conductive base the first face and second conductive base the second face it Between to form the first board set；

3rd face of first conductive base in first board set is etched to expose the First Line Road figure, the fourth face of second conductive base in first board set is etched to expose second circuit Figure.

Optionally, 3 to 6 ounces of the thickness thickness of first line figure described in the thickness ratio of first conductive base.

Optionally, 3 to 6 ounces of the thickness thickness of the second line pattern described in the thickness ratio of second conductive base.

Optionally, the distance between the first line figure in first board set and second line pattern For x mil, wherein, design between the first line figure and second line pattern is pressure-resistant to be lied prostrate for y, wherein, y/x is small In or equal to 500.

Optionally, methods described also includes：The first line figure and second line pattern are exposed into surface First board set is pressed with least one second board set.

Optionally, it is described in the first face of the first conductive base if first face is the smooth surface of the first conductive base Upper formation first line figure, including：

The first plating resist film is covered in the 3rd face of first conductive base；On the first face of first conductive base Cover the second plating resist film and expose the first logicalnot circuit graph area；The first logicalnot circuit graph area is etched to be formed First line figure；Remove the second plating resist film in first face；Remove the first plating resist film in the 3rd face.

The first plating resist film is covered on the 3rd face of first conductive base；In the first face of first conductive base The second plating resist film of upper covering simultaneously exposes first line graph area；Conductive material is plated to the first line graph area to form first Line pattern；Remove the second plating resist film in first face；Remove the first plating resist film in the 3rd face；Wherein, The thickness of the first line figure is equal to the thickness of the second plating resist film.

Optionally, it is described in the first face of the first conductive base if first face is the hair side of the first conductive base Upper formation first line figure, including：

Optionally, it is described in the second face of the second conductive base if second face is the smooth surface of the second conductive base The second line pattern of upper formation, including：

The 3rd plating resist film is covered on the fourth face of second conductive base；In the second face of second conductive base The 4th plating resist film of upper covering simultaneously exposes the first logicalnot circuit graph area；The first logicalnot circuit graph area is etched with shape Into the second line pattern；Remove the 4th plating resist film in second face；Remove the 3rd plating resist film of the fourth face.

The 3rd plating resist film is covered on the fourth face of second conductive base；In the second face of second conductive base The 4th plating resist film of upper covering simultaneously exposes the second line pattern area；Conductive material is plated to the second line pattern area to form second Line pattern；Remove the 4th plating resist film in second face；Remove the 3rd plating resist film of the fourth face；Wherein, The thickness of second line pattern is equal to the thickness of the 4th plating resist film.

Optionally, it is described in the second face of the second conductive base if second face is the hair side of the second conductive base The second line pattern of upper formation, including：

Optionally, the 3rd face of first conductive base in first board set is etched to expose The first line figure, including：3rd face of first conductive base in first board set is etched with Expose the first line figure, and to expose the first line figure and the prepreg table in first board set Face flushes.

Optionally, the fourth face of second conductive base in first board set is etched to expose Second line pattern, including：The fourth face of second conductive base in first board set is etched with Expose second line pattern, and to expose second line pattern and the prepreg table in first board set Face flushes.

The embodiment of the present invention also provides a kind of circuit board processing device, it may include：

Figure forming apparatus, for forming first line figure on the first face of the first conductive base, wherein, if described First face be first conductive base smooth surface, then the first line figure be based on first face is etched and/ Or plate conductive material and formed, if first face is the hair side of first conductive base, the first line figure base Formed in first face plating conductive material；The second line pattern is formed on the second face of the second conductive base, wherein, If second face is the smooth surface of second conductive base, second line pattern is based on losing second face Carve and/or plate conductive material and formed, if second face is the hair side of second conductive base, the first line figure Shape is based on plating conductive material in second face and being formed；

Press fit device, for the first face that prepreg is pressed to first conductive base and second conductive base To form the first board set between second face of material；

Etaching device, for being etched to the 3rd face of first conductive base in first board set with dew Go out the first line figure, the fourth face of second conductive base in first board set is etched to expose Second line pattern.

As can be seen that in the wiring board processing scheme of the present embodiment, first is formed on the first face of the first conductive base Line pattern, the second line pattern is formed on the second face of the second conductive base, wherein, if the first face is the first conductive base Smooth surface, then first line figure be based on the first face is etched and/or plate conductive material and is formed, if the first face be first The hair side of conductive base, then first line figure be based on the first face plate conductive material and formed；If the second face is second conductive The smooth surface of base material, then the second line pattern to the second face based on being etched and/or plating conductive material and formed, if the second face is The hair side of second conductive base, then first line figure be based on the second face plate conductive material and formed；Prepreg is pressed To between the first face of the first conductive base and the second face of the second conductive base to form the first board set；To the first board set In the 3rd face of the first conductive base be etched to expose first line figure, to the second conductive base in the first board set The fourth face of material is etched to expose the second line pattern.Due in above-mentioned processing scheme, distinguishing the hair side of conductive base And smooth surface, form line pattern progress for processing to form line pattern and process in its smooth surface on the hair side of conductive base Difference is treated, to accomplish that elimination is relatively low because conductive base is inherently present surface smoothness as far as possible in circuit process as far as possible Burr is more and the influence of line pattern surface smoothness and burr to processing, is advantageous to improve line pattern surface as far as possible Flatness, decrease or even eliminate line pattern surface spikes, due in circuit process just as far as possible to eliminate these right The very big fault of construction of pressure-resistant performance impact, therefore, among such line pattern layer is pressed into multilayer circuit board, even if The thickness of prepreg is relatively low between line pattern layer, can also ensure the pressure-resistant performance of multilayer circuit board to a certain extent.It can be seen that The technical scheme that embodiment provides is advantageous to improve PCB proof voltage on the premise of prepreg thickness in control PCB as far as possible Performance, and then be advantageous to effectively reduce high multi-layer PCB finally overall thickness of slab.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also To obtain other accompanying drawings according to these accompanying drawings.

Fig. 1 is that the embodiment of the present invention provides a kind of schematic flow sheet of circuit board processing method；

Fig. 2-a~Fig. 2-h are that the embodiment of the present invention provides a kind of circuit board work flow schematic diagram；

Fig. 3-a~Fig. 3-i are that the embodiment of the present invention provides another circuit board work flow schematic diagram；

Fig. 4 is that the embodiment of the present invention provides a kind of schematic diagram of circuit board processing device.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

Term " first ", " second ", " the 3rd " " in description and claims of this specification and above-mentioned accompanying drawing Four " etc.（If there is）It is for distinguishing similar object, without for describing specific order or precedence.It should manage The data that solution so uses can exchange in the appropriate case, so as to embodiments of the invention described herein for example can with except Order beyond those for illustrating or describing herein is implemented.In addition, term " comprising " and " having " and theirs is any Deformation, it is intended that cover it is non-exclusive include, for example, containing the process of series of steps or unit, method, system, production Product or equipment are not necessarily limited to those steps clearly listed or unit, but may include not list clearly or for this The intrinsic other steps of a little process, method, product or equipment or unit.

One embodiment of circuit board processing method of the present invention, wherein, circuit board processing method may include：It is conductive first First line figure is formed on first face of base material, wherein, if the first face is the smooth surface of the first conductive base, first line figure Shape is based on being etched the first face and/or plating conductive material and formed, if the first face is the hair side of the first conductive base, the One line pattern is based on plating conductive material in the first face and being formed；The second line map is formed on the second face of the second conductive base Shape, wherein, if the second face be the second conductive base smooth surface, the second line pattern be based on the second face is etched and/or Plate conductive material and formed, if the second face is the hair side of the second conductive base, first line figure is based on the plating in the second face and led Electric material and formed；Prepreg is pressed between the first face of the first conductive base and the second face of the second conductive base with Form the first board set；3rd face of the first conductive base in the first board set is etched to expose first line figure Shape, the fourth face of the second conductive base in the first board set is etched to expose the second line pattern.

Fig. 1 is referred to, Fig. 1 is a kind of schematic flow sheet of circuit board processing method provided in an embodiment of the present invention.Such as Fig. 1 Shown, a kind of circuit board processing method provided in an embodiment of the present invention can include herein below：

101st, first line figure is formed on the first face of the first conductive base, wherein, if the first face is first conductive The smooth surface of base material, then first line figure to the first face based on being etched and/or plating conductive material and formed, if the first face is The hair side of first conductive base, then first line figure be based on the first face plate conductive material and formed.

102nd, the second line pattern is formed on the second face of the second conductive base, wherein, if the second face is second conductive The smooth surface of base material, then the second line pattern to the second face based on being etched and/or plating conductive material and formed, if the second face is The hair side of second conductive base, then first line figure be based on the second face plate conductive material and formed.

Wherein, the smooth surface of conductive base and hair side are relative concepts, and the burr quantity of the smooth surface of conductive base is less than conduction The burr quantity of base material hair side, the flatness of the smooth surface of conductive base are higher than the flatness of conductive base hair side.Due to conductive base The particularity of manufacture process, create and the relatively low hair side of the relatively more flatness of burr quantity necessarily deposited on conductive base, The higher hair side of the relatively fewer flatness of burr quantity.Test result shows in actual production, burr on the hair side of conductive base Quantity and burr length are more than the several times of the burr quantity and burr length in smooth surface.

Wherein, found in testing and put into practice, for the hair side of conductive base, if passing through plating（Such as plating and/or chemistry Plating）Conductive material and line pattern is formed on hair side, the surface of the line pattern is relatively smooth smooth, substantially without burr. But if only pass through etching（That is subtractive process）Line pattern is formed on hair side, then the relatively low burr of the surface smoothness is more, Because by only passing through etching（That is subtractive process）Line pattern is formed on hair side, then line pattern surface just inherits conduction The problem of intrinsic relatively low burr of flatness of the hair side of base material is more, this may be that follow-up pressure-resistant problem is embedded to larger hidden danger. For the smooth surface of conductive base, if passing through plating（Such as plating and/or chemical plating）Conductive material or the mode of etching are in smooth surface Upper formation line pattern, the surface of the line pattern is relatively smooth smooth, substantially without burr.

That is, for conductive base, processed on its hair side and form circuit and the processing formation in its smooth surface Circuit is to need to carry out difference to treat, if the face that circuit is not formed to processing is that smooth surface or hair side are distinguish between, simply using certain Processing mode is planted to form line pattern, then may make it that the relatively low burr of line pattern surface smoothness is more, be pressed to Among multilayer circuit board, this may be that the pressure-resistant performance of multilayer circuit board is embedded to larger hidden danger.

In some embodiments of the invention, if passing through plating（Such as plating and/or chemical plating）Conductive material forms First Line Road figure, then smooth processing further also is carried out to the first line patterned surface that plating is formed, further to improve First Line The flatness of road patterned surface.

In some embodiments of the invention, if passing through plating（Such as plating and/or chemical plating）Conductive material forms the second line Road figure, then smooth processing further also is carried out to the second line pattern surface that plating is formed, further to improve the second line The flatness of road patterned surface.

In some embodiments of the invention, the thickness of the above-mentioned first line figure of the thickness ratio of above-mentioned first conductive base Thick 3 to 6 ounces, certainly, the thickness of above-mentioned first conductive base is also thick more than 6 ounces than the thickness of above-mentioned first line figure Or more than 8 ounces or more than 10 ounces.Or the thickness of above-mentioned first conductive base is also than the thickness of above-mentioned first line figure Degree is thick less than 2.5 ounces or less than 2 ounces or less than 1 ounce.

In some embodiments of the invention, the thickness of above-mentioned second line pattern of the thickness ratio of above-mentioned second conductive base Thick 3 to 6 ounces, certainly, the thickness of above-mentioned second conductive base is also thick more than 6 ounces than the thickness of above-mentioned second line pattern Or more than 8 ounces or more than 10 ounces, or, the thickness of above-mentioned second conductive base is also than the thickness of above-mentioned second line pattern Degree is thick less than 2.5 ounces or less than 2 ounces or less than 1 ounce.

103rd, prepreg is pressed between the first face of the first conductive base and the second face of the second conductive base with Form the first board set.

Wherein, the prepreg in the embodiment of the present invention for example can be epoxy resin, phenolic resin, polyimides, cyanogen At least one of acid esters and bismaleimide-triazine resin, certain prepreg may also comprise other dielectrics.

Wherein, prepreg is pressed between the first face of the first conductive base and the second face of the second conductive base with During forming the first board set, lamination contraposition is carried out using registration holes.Inner line figure and positioning hole can be same Drilled out in a set of alignment system, to ensure that inner line figure occurs without inconsistent phenomenon in lamination as far as possible.

104th, the 3rd face for pressing to the first conductive base among the first board set is etched to expose First Line Road figure, the fourth face for pressing to the second conductive base among the first board set is etched to expose the second line map Shape.

During actual processing, the 3rd face for pressing to the first conductive base among the first board set is etched Specifically it may include with exposing first line figure：The 3rd face for pressing to the first conductive base among the first board set is carried out Customary etch, when soon exposing above-mentioned prepreg, continue to etch the 3rd face of the first conductive base using microetch technique, directly All expose to above-mentioned prepreg, thus advantageously ensured that remaining circuit body of the first line figure in addition to a surface It is wholly embedded within prepreg, i.e. first line patterned surface is completely concordant with prepreg surface.

Similar.During actual processing, the fourth face to pressing to the second conductive base among the first board set Be etched specifically may include with exposing the second line pattern：To pressing to the second conductive base among the first board set Four sides carries out customary etch, when soon exposing above-mentioned prepreg, continues to etch the second conductive base using microetch technique Fourth face, until above-mentioned prepreg all exposes, thus advantageously ensure that the second line pattern in addition to a surface Remaining circuit body is wholly embedded within above-mentioned prepreg, i.e. the second line pattern surface and above-mentioned prepreg surface are complete Concordantly.

Subsequently, also the first board set can be subjected to brown processing.

In some embodiments of the invention, it is above-mentioned conductive first if the first face is the smooth surface of the first conductive base First line figure is formed on first face of base material, it may include：The first plating resist film is covered on the 3rd face of the first conductive base； The second plating resist film is covered on the first face of the first conductive base and exposes the first logicalnot circuit graph area；To the first logicalnot circuit figure Area is etched to form first line figure；Remove the second plating resist film in the first face；Remove first plating resist in the 3rd face Film.As can be seen that this processing mode when being etched using the first conductive base as etching carrier, without using other erosions Carve carrier（Such as peelable carrier etc.）, be advantageous to simplify manufacturing procedure.

It is above-mentioned to be led first if the first face is the smooth surface of the first conductive base in other embodiments of the present invention First line figure is formed on first face of electric base material, it may include：The first plating resist is covered on the 3rd face of the first conductive base Film；The second plating resist film is covered on the first face of the first conductive base and exposes first line graph area；To first line figure Conductive material is plated to form first line figure in area；Remove the second plating resist film in the first face；Remove the first plating resist film in the 3rd face； Wherein, the thickness of first line figure is equal to the thickness of the second plating resist film.As can be seen that this processing mode is carrying out plating conduction Using the first conductive base as etching carrier during material, without using other plating carriers（Such as peelable carrier etc.）, favorably In simplified manufacturing procedure.

In some embodiments of the invention, it is above-mentioned conductive first if the first face is the hair side of the first conductive base First line figure is formed on first face of base material, can be included：The first plating resist is covered on the 3rd face of the first conductive base Film；The second plating resist film is covered on the first face of the first conductive base and exposes first line graph area；To first line figure Conductive material is plated to form first line figure in area；Remove the second plating resist film in the first face；Remove the first plating resist film in the 3rd face； Wherein, the thickness of first line figure is equal to the thickness of the second plating resist film.As can be seen that this processing mode is when being etched Using the first conductive base as etching carrier, without using other etching carriers（Such as peelable carrier etc.）, be advantageous to simplify Manufacturing procedure.

In some embodiments of the invention, it is above-mentioned conductive second if the second face is the smooth surface of the second conductive base The second line pattern is formed on second face of base material, including：The 3rd plating resist film is covered on the fourth face of the second conductive base； The 4th plating resist film is covered on second face of the second conductive base and exposes the first logicalnot circuit graph area；To the first logicalnot circuit graph area It is etched to form the second line pattern；Remove the 4th plating resist film in the second face；Remove the 3rd plating resist film of fourth face. As can be seen that this processing mode when being etched using the second conductive base as etching carrier, without using other etchings Carrier（Such as peelable carrier etc.）, be advantageous to simplify manufacturing procedure.

In other embodiments of the present invention, the 3rd plating resist film is covered on the fourth face of the second conductive base； The 4th plating resist film is covered on second face of two conductive bases and exposes the second line pattern area；Second line pattern area is plated conductive Material is to form the second line pattern；Remove the 4th plating resist film in the second face；Remove the 3rd plating resist film of fourth face；Second circuit The thickness of figure is equal to the thickness of the 4th plating resist film.As can be seen that this processing mode when carrying out plating conductive material with first Conductive base is as etching carrier, without using other plating carriers（Such as peelable carrier etc.）, be advantageous to simplify processing work Sequence.

In some embodiments of the invention, it is above-mentioned conductive second if the second face is the hair side of the second conductive base The second line pattern is formed on second face of base material, including：The 3rd plating resist film is covered on the fourth face of the second conductive base； The 4th plating resist film is covered on second face of the second conductive base and exposes the second line pattern area；The plating of second line pattern area is led Electric material is to form the second line pattern；Remove the 4th plating resist film in the second face；Remove the 3rd plating resist film of fourth face；Wherein, The thickness of second line pattern is equal to the thickness of the 4th plating resist film.Therein, it can be seen that this processing mode is carrying out plating conduction Using the first conductive base as etching carrier during material, without using other plating carriers（Such as peelable carrier etc.）, favorably In simplified manufacturing procedure.

In some embodiments of the invention, the 3rd face of above-mentioned first conductive base in above-mentioned first board set is carried out Etching may include with exposing above-mentioned first line figure：To the 3rd face of above-mentioned first conductive base in above-mentioned first board set It is etched to expose above-mentioned first line figure, and to expose in above-mentioned first line figure and above-mentioned first board set Prepreg surface flushes or is substantially flush；Or the 3rd face of above-mentioned first conductive base in above-mentioned first board set is carried out Etching to expose above-mentioned first line figure with half in above-mentioned first board set admittedly to expose above-mentioned first line figure The difference in height changed between piece is less than or equal to first threshold（The span of first threshold can be 0~2 millimeter）.

In some embodiments of the invention, the fourth face of above-mentioned second conductive base in above-mentioned first board set is carried out Etching is included with exposing above-mentioned second line pattern：The fourth face of above-mentioned second conductive base in above-mentioned first board set is entered Row etching to expose above-mentioned second line pattern and half in above-mentioned first board set to expose above-mentioned second line pattern Cured sheets surface flushes or is substantially flush；Or the fourth face of above-mentioned second conductive base in above-mentioned first board set is lost Carve to expose above-mentioned second line pattern, and to expose above-mentioned second line pattern and the semi-solid preparation in above-mentioned first board set Difference in height between piece is less than Second Threshold（The span of Second Threshold can be 0~2 millimeter）.

In some embodiments of the invention, the above-mentioned first line figure in above-mentioned first board set and above-mentioned second line The distance between road figure is x mil（Mil）, wherein, setting between above-mentioned first line figure and above-mentioned second line pattern It is that y is lied prostrate to count pressure-resistant, wherein, y/x may be less than or equal to 500.The first line figure that is processed due to the scheme of the present embodiment and The flatness on the second line pattern surface is relatively very high, thus y/x may be less than or equal to it is 500 even more small, if based on existing plus Work mode, then y/x be typically only capable to be less than 700 or so, it is difficult to accomplish y/x be less than or equal to 500 pressure-resistant effect.Therefore, this reality The technical scheme for applying example is advantageous to improve PCB proof voltage energy on the premise of prepreg thickness in control PCB as far as possible, enters And be advantageous to effectively reduce high multi-layer PCB finally overall thickness of slab.

Wherein, 1 millimeter=40mil, 1mil are about mil.

In some embodiments of the invention, foregoing circuit plate processing method can also further comprise：Surface is exposed First board set of one line pattern and the second line pattern is pressed with least one second board set.

Wherein, the second board set can also have the structure of similar first board set, and the second board set can also use similar add The technique of the board set of work first processes to obtain.Certain second board set has not similar to the structure of the first board set, the second plate Material collection also can be processed to obtain using other techniques of the not technique of the first board set of similar processing.

In some embodiments of the invention, if the second board set for example may include dry plate pcb board material（Such as FR4 sheet materials）, Wherein, can be for example bonded in the second board set between each PCB material by prepreg or other materials.

In some embodiments of the invention, if by prepreg by the first board set and at least one second board set Pressed, and if the second board set also process to obtain using the technique similar to the first board set of processing, first board set Distance with the second adjacent board set is x2mil, between the first board set and the second adjacent board set adjacent lines figure Design it is pressure-resistant lied prostrate for y2, then y2/x2 can be less than or equal to 500 even more small.Because the scheme of the present embodiment processes The first board set surface first line figure and the second line pattern surface flatness it is relatively very high, therefore y2/x2 can Less than or equal to 500, if being based on existing processing mode, y2/x2 is typically only capable to be less than 700 or so, it is difficult to accomplishes that y2/x2 is small In or equal to 500 pressure-resistant effect.Therefore, it is thick to be advantageous to the prepreg in control PCB as far as possible for the technical scheme of the present embodiment PCB proof voltage energy is improved on the premise of degree, and then is advantageous to effectively reduce high multi-layer PCB finally overall thickness of slab.

For ease of being better understood from and implementing the such scheme of the embodiment of the present invention, application scenarios are carried out below in conjunction with the accompanying drawings Citing.

Please also refer to Fig. 2-a~Fig. 2-h, wherein, Fig. 2-a~Fig. 2-h are a kind of multilayer provided in an embodiment of the present invention Wiring board work flow schematic diagram.

Wherein, Fig. 2-a show the first conductive base 210 and the second conductive base 220.

Fig. 2-b show that the hair side in the first conductive base 210 covers the first plating resist film 231, in the first conductive base 210 Smooth surface on cover the second plating resist film 232 and expose the first logicalnot circuit graph area 211.Fig. 2-b also show in the second conductive base The hair side of material 220 covers the 3rd plating resist film 234, and the 4th plating resist film 233 is covered in the smooth surface of the second conductive base 220 and is exposed Second logicalnot circuit graph area 221.

Fig. 2-c are shown is etched place to the first logicalnot circuit graph area 211 in the smooth surface of the first conductive base 210 Manage to form first line figure 212；Remove the second plating resist film 232 in smooth surface；Remove the first plating resist film 231 on hair side. Fig. 2-b also show to be etched with shape to the second logicalnot circuit graph area 221 in the smooth surface of the second conductive base 220 Into the second line pattern 222；Remove the 4th plating resist film 234 in smooth surface；Remove the 3rd plating resist film 234 on hair side.

Fig. 2-d and Fig. 2-e show the smooth surface and the second conduction that prepreg 240 is pressed to the first conductive base 210 To form the first board set 200 between the smooth surface of base material 220.

Wherein, prepreg 240 for example can be that epoxy resin, phenolic resin, polyimides, cyanate and span carry out acyl At least one of imines-cyanate resin, certain prepreg 240 may also comprise other dielectrics.

Wherein, prepreg 240 is pressed to the smooth surface of the first conductive base 210 and the smooth surface of the second conductive base 220 Between with formed the first board set 200 during, can utilize registration holes etc. progress lamination contraposition.Inner line figure and fixed Position hole can drill out in same set of alignment system, to ensure that inner line figure occurs without inconsistent phenomenon in lamination as far as possible.

Fig. 2-f show the hair side for pressing to the first conductive base 210 among the first board set 200 is etched with Expose first line figure 212, the hair side for pressing to the second conductive base 220 among the first board set 200 is etched To expose the second line pattern 222.

During actual processing, the hair side for pressing to the first conductive base 210 among the first board set 200 is entered Row etching specifically may include with exposing first line figure 212：To pressing to the first conductive base among the first board set 200 210 hair side carries out customary etch, when soon exposing above-mentioned prepreg 240, continues etching first using microetch technique and leads The hair side of electric base material 210, expose until above-mentioned prepreg 240 is whole, thus advantageously ensured that first line figure 212 Remaining circuit body in addition to a surface is wholly embedded within prepreg 240, i.e. the surface of first line figure 212 and half is admittedly It is completely concordant to change the surface of piece 240.

In the process of reality, the hair side for pressing to the first conductive base 210 among the first board set 200 is entered The board set of first line figure 212 and first that row etching process is exposed with exposing first line figure 212, and also may be such that The difference in height between prepreg 240 in 200 is less than or equal to first threshold（The span of first threshold can be 0~2 Millimeter）.In figure so that first threshold is equal to 0 millimeter or substantially close to 0 millimeter as an example.

During actual processing, the hair side for pressing to the second conductive base 220 among the first board set 200 is entered Row etching specifically may include with exposing the second line pattern 222：To pressing to the second conductive base among the first board set 200 220 hair side carries out customary etch, when soon exposing above-mentioned prepreg 240, continues etching second using microetch technique and leads The hair side of electric base material 220, expose until above-mentioned prepreg 240 is whole, thus advantageously ensured that the second line pattern 222 Remaining circuit body in addition to a surface is wholly embedded within prepreg 240, i.e. the surface of the second line pattern 222 and half is admittedly It is completely concordant to change the surface of piece 240.

In the process of reality, the hair side for pressing to the second conductive base 220 among the first board set 200 is entered The second line pattern 222 and the first board set that row etching process is exposed with exposing the second line pattern 222, and also may be such that The difference in height between prepreg 240 in 200 is less than or equal to first threshold（The span of first threshold can be 0~2 Millimeter）.In figure so that first threshold is equal to 0 millimeter or substantially close to 0 millimeter as an example.

Subsequently, also the first board set 240 can be subjected to brown processing.

In some embodiments of the invention, the line pattern of first line figure 212 and second in the first board set 200 The distance between 222 be x mil, wherein, design between the line pattern 222 of first line figure 212 second is pressure-resistant to be lied prostrate for y, Wherein, y/x may be less than or equal to 500.The line map of first line figure 212 and second processed due to the scheme of the present embodiment The flatness on the surface of shape 222 is relatively very high, thus y/x may be less than or equal to it is 500 even more small, if being based on existing processing mode, Then y/x is typically only capable to be less than 700 or so, it is difficult to accomplishes the pressure-resistant effect that y/x is less than or equal to 500.Therefore, the skill of the present embodiment Art scheme is advantageous to improve PCB proof voltage energy on the premise of prepreg thickness in control PCB as far as possible, and then is advantageous to Effectively reduce high multi-layer PCB finally overall thickness of slab.

Fig. 2-g show by surface expose the first board set 200 of the line pattern 222 of first line figure 212 and second with At least one second board set is pressed.Fig. 2-g show in by prepreg by the first board set 200 and two the second plates Material collection 250 and two the second board sets 260 press.Wherein, the second board set 260 is conductive layer.

Wherein, in figure so that the second board set 250 has the similar structure of first board set 200 as an example, the second board set 250 is also It can process to obtain using the technique of the first board set 200 of similar processing.

In some embodiments of the invention, if by prepreg by the first board set 200 and at least one second plate Material collection 250 is pressed, and if the second board set 250 also processed using the technique similar to first board set 200 of processing Arrive, the distance of the first board set 200 and the second adjacent board set 250 be x2mil, the first board set 200 and adjacent second Design between the adjacent lines figure of board set 250 is pressure-resistant to be lied prostrate for y2, then it is even more small can be less than or equal to 500 by y2/x2. Due to the line pattern 222 of first line figure 212 and second on the surface of the first board set 200 that the scheme of the present embodiment processes The flatness on surface is relatively very high, therefore y2/x2 may be less than or equal to 500, if being based on existing processing mode, y2/x2 leads to Often it can only be less than 700 or so, it is difficult to accomplish the pressure-resistant effect that y2/x2 is less than or equal to 500.Therefore the technical scheme of the present embodiment Be advantageous to improve PCB proof voltage energy on the premise of prepreg thickness in control PCB as far as possible, and then be advantageous to effectively drop The final overall thickness of slab of low high multi-layer PCB.

Fig. 2-h show the second board set 260 being processed into surface line figure 261.

Please also refer to Fig. 3-a~Fig. 3-i, wherein, Fig. 3-a~Fig. 3-i are that another kind provided in an embodiment of the present invention is more Sandwich circuit board work flow schematic diagram.

Wherein, Fig. 3-a show the first conductive base 310 and the second conductive base 320.

Fig. 3-b show that the smooth surface in the first conductive base 310 covers the first plating resist film 331, in the first conductive base 210 Hair side on cover the second plating resist film 332 and expose first line graph area 311.Fig. 3-b also show in the second conductive base 320 smooth surface covers the 3rd plating resist film 334, and the 4th plating resist film 333 is covered on the hair side of the second conductive base 320 and exposes the Two circuit graph areas 221.

Fig. 3-c are shown carries out electroplating processes to the first line graph area 311 on the hair side of the first conductive base 310 To form first line figure 312；Remove the first plating resist film 331 in smooth surface；Wherein, the height of first line figure 312 is about Equal to the height of the second plating resist film 332 on hair side.It also show in Fig. 3-c on the hair side of the second conductive base 320 Second line pattern area 321 carries out electroplating processes to form first line figure 322；Remove the 3rd plating resist film 334 in smooth surface； Wherein, the height of the second line pattern 322 is approximately equal to the height of the 4th plating resist film 333 on hair side.

Fig. 3-d show the second plating resist film 332 removed on the hair side of the first conductive base 310, and Fig. 3-d also show removal The 4th plating resist film 333 on the hair side of second conductive base 320.

Fig. 3-e and Fig. 3-f show the hair side and the second conduction that prepreg 340 is pressed to the first conductive base 310 To form the first board set 300 between the hair side of base material 320.

Wherein, prepreg 340 for example can be that epoxy resin, phenolic resin, polyimides, cyanate and span carry out acyl At least one of imines-cyanate resin, certain prepreg 240 may also comprise other dielectrics.

Wherein, prepreg 340 is pressed to the hair side of the first conductive base 310 and the smooth surface of the second conductive base 320 Between with formed the first board set 300 during, can utilize registration holes etc. progress lamination contraposition.Inner line figure and fixed Position hole can drill out in same set of alignment system, to ensure that inner line figure occurs without inconsistent phenomenon in lamination as far as possible.

Fig. 3-g show the smooth surface for pressing to the first conductive base 310 among the first board set 300 is etched with Expose first line figure 312, the smooth surface for pressing to the second conductive base 320 among the first board set 300 is etched To expose the second line pattern 322.

During actual processing, the smooth surface for pressing to the first conductive base 310 among the first board set 300 is entered Row etching specifically may include with exposing first line figure 312：To pressing to the first conductive base among the first board set 300 310 smooth surface carries out customary etch, when soon exposing above-mentioned prepreg 340, continues etching first using microetch technique and leads The smooth surface of electric base material 310, expose until above-mentioned prepreg 340 is whole, thus advantageously ensured that first line figure 312 Remaining circuit body in addition to a surface is wholly embedded within prepreg 340, i.e. the surface of first line figure 312 and half is admittedly It is completely concordant to change the surface of piece 340.

In the process of reality, the smooth surface for pressing to the first conductive base 310 among the first board set 300 is entered The board set of first line figure 312 and first that row etching process is exposed with exposing first line figure 312, and also may be such that The difference in height between prepreg 340 in 300 is less than or equal to first threshold（The span of first threshold can be 0~2 Millimeter）.

During actual processing, the smooth surface for pressing to the second conductive base 320 among the first board set 300 is entered Row etching specifically may include with exposing the second line pattern 322：To pressing to the second conductive base among the first board set 300 320 smooth surface carries out customary etch, when soon exposing above-mentioned prepreg 340, continues etching second using microetch technique and leads The smooth surface of electric base material 320, expose until above-mentioned prepreg 340 is whole, thus advantageously ensured that the second line pattern 322 Remaining circuit body in addition to a surface is wholly embedded within prepreg 340, i.e. the surface of the second line pattern 322 and half is admittedly It is completely concordant to change the surface of piece 340.

During actual processing, the smooth surface for pressing to the second conductive base 320 among the first board set 300 is entered The second line pattern 322 and the first board set that row etching process is exposed with exposing the second line pattern 322, and also may be such that The difference in height between prepreg 340 in 300 is less than or equal to first threshold（The span of first threshold can be 0~2 milli Rice）, by first threshold be equal to 0 millimeter in figure or substantially close to 0 millimeter exemplified by.

Subsequently, also the first board set 340 can be subjected to brown processing.

In some embodiments of the invention, the line pattern of first line figure 312 and second in the first board set 300 The distance between 322 be x mil, wherein, design between the line pattern 322 of first line figure 312 second is pressure-resistant to be lied prostrate for y, Wherein, y/x may be less than or equal to 500.The line map of first line figure 312 and second processed due to the scheme of the present embodiment The flatness on the surface of shape 322 is relatively very high, thus y/x may be less than or equal to it is 500 even more small, if being based on existing processing mode, Then y/x is typically only capable to be less than 700 or so, it is difficult to accomplishes the pressure-resistant effect that y/x is less than or equal to 500.Therefore, the skill of the present embodiment Art scheme is advantageous to improve PCB proof voltage energy on the premise of prepreg thickness in control PCB as far as possible, and then is advantageous to Effectively reduce high multi-layer PCB finally overall thickness of slab.

Fig. 3-h show by surface expose the first board set 300 of the line pattern 322 of first line figure 312 and second with At least one second board set is pressed.Fig. 3-g show in by prepreg by the first board set 300 and two the second plates Material collection 350 and two the second board sets 360 press.Wherein, the second board set 360 is conductive layer.

Wherein, in figure so that the second board set 350 has the similar structure of first board set 300 as an example, the second board set 350 is also It can process to obtain using the technique of the first board set 300 of similar processing.

In some embodiments of the invention, if by prepreg by the first board set 300 and at least one second plate Material collection 350 is pressed, and if the second board set 350 also processed using the technique similar to first board set 300 of processing Arrive, the distance of the first board set 300 and the second adjacent board set 350 be x2mil, the first board set 300 and adjacent second Design between the adjacent lines figure of board set 350 is pressure-resistant to be lied prostrate for y2, then it is even more small can be less than or equal to 500 by y2/x2. Due to the line pattern 322 of first line figure 312 and second on the surface of the first board set 300 that the scheme of the present embodiment processes The flatness on surface is relatively very high, therefore y2/x2 may be less than or equal to 500, if being based on existing processing mode, y2/x2 leads to Often it can only be less than 700 or so, it is difficult to accomplish the pressure-resistant effect that y2/x2 is less than or equal to 500.Therefore the technical scheme of the present embodiment Be advantageous to improve PCB proof voltage energy on the premise of prepreg thickness in control PCB as far as possible, and then be advantageous to effectively drop The final overall thickness of slab of low high multi-layer PCB.

Fig. 3-i show the second board set 360 being processed into surface line figure 361.

It is appreciated that the multilayer circuit board work flow of Fig. 2-a~Fig. 2-h citings is to come according to substantially similar way Exemplified by processing first line figure and the second line pattern, in the multilayer circuit board work flow of Fig. 3-a~Fig. 3-i citings It is exemplified by processing first line figure and the second line pattern according to substantially similar way.Certainly, in practical application In the mode for processing first line figure and the second line pattern of two of the example above can also necessarily be combined, That is, for example first line figure can be processed according to Fig. 2-a~Fig. 2-h way of example, and can be according to Fig. 3-a~Fig. 3-i Way of example processes the second line pattern.

It is understood that the structure shown in above-mentioned accompanying drawing needs by way of example only, in actual applications certainly also May flexibly it be adjusted as needed.

Referring to Fig. 4, the embodiment of the present invention also provides a kind of circuit board processing device, it may include figure forming apparatus 410, pressure Attach together and put 420 and Etaching device 430.

Wherein, figure forming apparatus 410, for forming first line figure on the first face of the first conductive base, its In, if the first face is the smooth surface of the first conductive base, first line figure is based on the first face being etched and/or plated conduction Material and formed, if the first face be the first conductive base hair side, first line figure be based on the first face plate conductive material And formed.

Wherein, figure forming apparatus 410 is additionally operable to, and the second line pattern is formed on the second face of the second conductive base, Wherein, if the second face is the smooth surface of the second conductive base, the second line pattern is based on that the second face is etched and/or plated to lead Electric material and formed, if the second face be the second conductive base hair side, first line figure be based on the second face plate conduction material Expect and formed.

Press fit device 420, for prepreg to be pressed to the first face and the second conductive base of the first conductive base To form the first board set between second face.

Wherein, press fit device 420 presses to prepreg the first face and second conductive base of the first conductive base Between second face with formed the first board set during, using registration holes carry out lamination contraposition.Inner line figure and fixed Position hole can drill out in same set of alignment system, to ensure that inner line figure occurs without inconsistent phenomenon in lamination as far as possible.

Etaching device 430, for being etched to the 3rd face for pressing to the first conductive base among the first board set To expose first line figure, the fourth face for pressing to the second conductive base among the first board set is etched to expose Second line pattern.

During actual processing, Etaching device 430 to the first conductive base among pressing to the first board set Three faces are etched specifically may include with exposing first line figure：To pressing to the first conductive base among the first board set The 3rd face carry out customary etch, when soon exposing above-mentioned prepreg, using microetch technique continue etch the first conductive base 3rd face of material, until above-mentioned prepreg all exposes, thus advantageously ensured that first line figure except a surface it Outer remaining circuit body is wholly embedded within prepreg, i.e. first line patterned surface is completely concordant with prepreg surface.

Similar.During actual processing, Etaching device 430 is to the second conductive base among pressing to the first board set The fourth face of material is etched specifically may include with exposing the second line pattern：Led to pressing to second among the first board set The fourth face of electric base material carries out customary etch, when soon exposing above-mentioned prepreg, continues etching second using microetch technique The fourth face of conductive base, until above-mentioned prepreg all exposes, thus advantageously ensure that the second line pattern removes one Remaining circuit body outside surface is wholly embedded within above-mentioned prepreg, i.e. the second line pattern surface and above-mentioned semi-solid preparation Piece surface is completely concordant.

Subsequently, also the first board set can be subjected to brown processing.

In some embodiments of the invention, if the first face is the smooth surface of the first conductive base, led above-mentioned first The aspect of first line figure is formed on first face of electric base material, figure forming apparatus 410 can be specifically used for：In the first conductive base The first plating resist film is covered on 3rd face of material；The second plating resist film is covered on the first face of the first conductive base and to expose first non- Line pattern area；First logicalnot circuit graph area is etched to form first line figure；Remove the second of the first face Plating resist film；Remove the first plating resist film in the 3rd face.

In other embodiments of the present invention, if the first face is the smooth surface of the first conductive base, above-mentioned first The aspect of first line figure is formed on first face of conductive base, figure forming apparatus 410 can be specifically used for：It is conductive first The first plating resist film is covered on 3rd face of base material；The second plating resist film is covered on the first face of the first conductive base and exposes first Line pattern area；Conductive material is plated to first line graph area to form first line figure；Remove second plating resist in the first face Film；Remove the first plating resist film in the 3rd face；Wherein, the thickness of first line figure is equal to the thickness of the second plating resist film.

In some embodiments of the invention, if the first face is the hair side of the first conductive base, led above-mentioned first The aspect of first line figure is formed on first face of electric base material, figure forming apparatus 410 can be specifically used for：In the first conductive base The first plating resist film is covered on 3rd face of material；The second plating resist film is covered on the first face of the first conductive base and exposes First Line Road graph area；Conductive material is plated to first line graph area to form first line figure；Remove the second plating resist film in the first face； Remove the first plating resist film in the 3rd face；Wherein the thickness of first line figure is equal to the thickness of the second plating resist film.

In some embodiments of the invention, if the second face is the smooth surface of the second conductive base, led above-mentioned second The aspect of the second line pattern is formed on second face of electric base material, figure forming apparatus 410 can be specifically used for：It is conductive second The 3rd plating resist film is covered on the fourth face of base material；The 4th plating resist film is covered on the second face of the second conductive base and exposes first Logicalnot circuit graph area；First logicalnot circuit graph area is etched to form the second line pattern；Remove the of the second face Four plating resist films；Remove the 3rd plating resist film of fourth face.

In other embodiments of the invention, if the second face is the smooth surface of the second conductive base, led above-mentioned second The aspect of the second line pattern is formed on second face of electric base material, figure forming apparatus 410 can be specifically used for：It is conductive second The 3rd plating resist film is covered on the fourth face of base material；The 4th plating resist film is covered on the second face of the second conductive base and exposes second Line pattern area；Conductive material is plated to the second line pattern area to form the second line pattern；Remove the 4th plating resist in the second face Film；Remove the 3rd plating resist film of fourth face；Wherein, the thickness of the second line pattern is equal to the thickness of the 4th plating resist film.

In some embodiments of the invention, if the second face is the hair side of the second conductive base, led above-mentioned second The aspect of the second line pattern is formed on second face of electric base material, figure forming apparatus 410 can be specifically used for：It is conductive second The 3rd plating resist film is covered on the fourth face of base material；The 4th plating resist film is covered on the second face of the second conductive base and exposes second Line pattern area；Conductive material is plated to the second line pattern area to form the second line pattern；Remove the 4th plating resist in the second face Film；Remove the 3rd plating resist film of fourth face；Wherein, the thickness of the second line pattern is equal to the thickness of the 4th plating resist film.

In some embodiments of the invention, the 3rd face of above-mentioned first conductive base in above-mentioned first board set is entered Row etching is to expose the aspect of above-mentioned first line figure, and Etaching device 430 can be specifically used for, in above-mentioned first board set 3rd face of above-mentioned first conductive base is etched to expose above-mentioned first line figure, and to expose above-mentioned first line Figure is flushed or is substantially flush with the prepreg surface in above-mentioned first board set；Or to above-mentioned in above-mentioned first board set 3rd face of the first conductive base is etched to expose above-mentioned first line figure, and to expose above-mentioned first line figure Difference in height between the prepreg in above-mentioned first board set is less than or equal to first threshold（The span of first threshold It can be 0~2 millimeter）.

In some embodiments of the invention, the fourth face of above-mentioned second conductive base in above-mentioned first board set enters Row etching is to expose the aspect of above-mentioned second line pattern, and Etaching device 430 can be specifically used for, in above-mentioned first board set The fourth face of above-mentioned second conductive base is etched to expose above-mentioned second line pattern, and to expose above-mentioned second circuit Figure is flushed or is substantially flush with the prepreg surface in above-mentioned first board set；Or to above-mentioned in above-mentioned first board set The fourth face of second conductive base is etched to expose above-mentioned second line pattern, and to expose above-mentioned second line pattern Difference in height between the prepreg in above-mentioned first board set is less than Second Threshold（The span of Second Threshold can be 0 ~2 millimeters）.

In some embodiments of the invention, press fit device 420 can be additionally used in, and surface is exposed into first line figure and First board set of two line patterns is pressed with least one second board set.

As can be seen that the multilayer line board processing device of the present embodiment is advantageous to the prepreg thickness in control PCB as far as possible PCB proof voltage energy is improved on the premise of degree, and then is advantageous to effectively reduce high multi-layer PCB finally overall thickness of slab.

It should be noted that for foregoing each method embodiment, in order to be briefly described, therefore it is all expressed as a series of Combination of actions, but those skilled in the art should know, the present invention is not limited by described sequence of movement because According to the present invention, some steps can use other orders or carry out simultaneously.Secondly, those skilled in the art should also know Know, embodiment described in this description belongs to preferred embodiment, and involved action and module are not necessarily of the invention It is necessary.In the above-described embodiments, the description to each embodiment all emphasizes particularly on different fields, and does not have the portion being described in detail in some embodiment Point, it may refer to the associated description of other embodiment.

The multilayer circuit board processing method provided above the embodiment of the present invention is described in detail, used herein Specific case is set forth to the principle and embodiment of the present invention, and the explanation of above example is only intended to help and understands The method and its core concept of the present invention；Meanwhile for those of ordinary skill in the art, according to the thought of the present invention, having There will be changes in body embodiment and application, to sum up, this specification content should not be construed as the limit to the present invention System.

Claims

A kind of 1. circuit board processing method, it is characterised in that including：

First line figure is formed on the first face of the first conductive base, wherein, if first face is described first conductive The smooth surface of base material, then the first line figure be based on first face is etched and/or plates conductive material and is formed, if First face is the hair side of first conductive base, then the first line figure is based on plating conduction material in first face Expect and formed；

The second line pattern is formed on the second face of the second conductive base, wherein, if second face is described second conductive The smooth surface of base material, then second line pattern be based on second face is etched and/or plates conductive material and is formed, if Second face is the hair side of second conductive base, then second line pattern is based on plating conduction material in second face Expect and formed；

Prepreg is pressed between the first face of first conductive base and the second face of second conductive base with Form the first board set；

3rd face of first conductive base in first board set is etched to expose the first line figure Shape, the fourth face of second conductive base in first board set is etched to expose second line map Shape.
2. according to the method for claim 1, it is characterised in that

Methods described also includes：

First board set of the first line figure and second line pattern and at least one the are exposed into surface Two board sets carry out pressing processing.
3. according to the method described in any one of claim 1 to 2, it is characterised in that

If first face is the smooth surface of the first conductive base, described to form First Line on the first face of the first conductive base Road figure, including：

The first plating resist film is covered in the 3rd face of first conductive base；Covered on the first face of first conductive base Second plating resist film simultaneously exposes the first logicalnot circuit graph area；The first logicalnot circuit graph area is etched to form first Line pattern；Remove the second plating resist film in first face；Remove the first plating resist film in the 3rd face.
4. according to the method described in any one of claim 1 to 2, it is characterised in that

If first face is the smooth surface of the first conductive base, described to form First Line on the first face of the first conductive base Road figure, including：

The first plating resist film is covered on the 3rd face of first conductive base；In the first face overlying of first conductive base Lid the second plating resist film simultaneously exposes first line graph area；Conductive material is plated to the first line graph area to form first line Figure；Remove the second plating resist film in first face；Remove the first plating resist film in the 3rd face；Wherein, it is described The thickness of first line figure is equal to the thickness of the second plating resist film.
5. according to the method described in any one of claim 1 to 2, it is characterised in that

If first face is the hair side of the first conductive base, described to form First Line on the first face of the first conductive base Road figure, including：

The first plating resist film is covered on the 3rd face of first conductive base；In the first face overlying of first conductive base Lid the second plating resist film simultaneously exposes first line graph area；Conductive material is plated to the first line graph area to form first line Figure；Remove the second plating resist film in first face；Remove the first plating resist film in the 3rd face；Wherein, it is described The thickness of first line figure is equal to the thickness of the second plating resist film.
6. according to the method described in any one of claim 1 to 2, it is characterised in that

If second face is the smooth surface of the second conductive base, described to form the second line on the second face of the second conductive base Road figure, including：

The 3rd plating resist film is covered on the fourth face of second conductive base；In the second face overlying of second conductive base The plating resist film of lid the 4th simultaneously exposes the first logicalnot circuit graph area；The first logicalnot circuit graph area is etched to form Two line patterns；Remove the 4th plating resist film in second face；Remove the 3rd plating resist film of the fourth face.
7. according to the method described in any one of claim 1 to 2, it is characterised in that

If second face is the smooth surface of the second conductive base, described to form the second line on the second face of the second conductive base Road figure, including：

The 3rd plating resist film is covered on the fourth face of second conductive base；In the second face overlying of second conductive base The plating resist film of lid the 4th simultaneously exposes the second line pattern area；Conductive material is plated to the second line pattern area to form the second circuit Figure；Remove the 4th plating resist film in second face；Remove the 3rd plating resist film of the fourth face；Wherein, it is described The thickness of second line pattern is equal to the thickness of the 4th plating resist film.
8. according to the method described in any one of claim 1 to 2, it is characterised in that

If second face is the hair side of the second conductive base, described to form the second line on the second face of the second conductive base Road figure, including：

The 3rd plating resist film is covered on the fourth face of second conductive base；In the second face overlying of second conductive base The plating resist film of lid the 4th simultaneously exposes the second line pattern area；Conductive material is plated to the second line pattern area to form the second circuit Figure；Remove the 4th plating resist film in second face；Remove the 3rd plating resist film of the fourth face；Wherein, it is described The thickness of second line pattern is equal to the thickness of the 4th plating resist film.
9. according to the method described in any one of claim 1 to 2, it is characterised in that

3rd face of first conductive base in first board set is etched to expose the First Line Road figure, including：3rd face of first conductive base in first board set is etched to expose described One line pattern, and make it that expose the first line figure flushes with the prepreg surface in first board set,

And/or

The fourth face of second conductive base in first board set is etched to expose second line Road figure, including：The fourth face of second conductive base in first board set is etched to expose described Two line patterns, and make it that expose second line pattern flushes with the prepreg surface in first board set.
A kind of 10. circuit board processing device, it is characterised in that including：

Figure forming apparatus, for forming first line figure on the first face of the first conductive base, wherein, if described first Face is the smooth surface of first conductive base, then the first line figure is based on that first face is etched and/or plated Conductive material and formed, if first face be first conductive base hair side, the first line figure be based on Plate conductive material and formed in first face；The second line pattern is formed on the second face of the second conductive base, wherein, if institute The smooth surface that the second face is second conductive base is stated, then second line pattern is based on being etched second face And/or plate conductive material and formed, if second face is the hair side of second conductive base, second line pattern Formed based on conductive material is plated in second face；

Press fit device, for the first face that prepreg is pressed to first conductive base and second conductive base To form the first board set between second face；

Etaching device, for being etched the 3rd face of first conductive base in first board set to expose First line figure is stated, the fourth face of second conductive base in first board set is etched described to expose Second line pattern.