CN104733318A - MOS transistor structure and manufacturing method thereof - Google Patents
MOS transistor structure and manufacturing method thereof Download PDFInfo
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- CN104733318A CN104733318A CN201310713804.1A CN201310713804A CN104733318A CN 104733318 A CN104733318 A CN 104733318A CN 201310713804 A CN201310713804 A CN 201310713804A CN 104733318 A CN104733318 A CN 104733318A
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- 239000010410 layer Substances 0.000 claims abstract description 149
- 239000011229 interlayer Substances 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 239000011435 rock Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
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- 125000001475 halogen functional group Chemical group 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
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- 239000011248 coating agent Substances 0.000 description 2
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- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
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- 229910052796 boron Inorganic materials 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- 229910052718 tin Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an MOS transistor manufacturing method. The method includes the steps that a, a semiconductor substrate, a pseudo gate stack layer, a side wall and a source drain region are provided; b, a first interlayer dielectric layer is formed, and the height of the interlayer dielectric layer is smaller than that of the pseudo gate stack layer; c, the parts, located at the two ends, away from the pseudo gate stack layer, of the first interlayer dielectric layer are removed to form a first vacancy; d, the first vacancy is filled with a second interlayer dielectric layer, the top of the second interlayer dielectric layer is located between the top of the first interlayer dielectric layer and the top of a gate stack layer; e, a third interlayer dielectric layer is formed to cover the first interlayer dielectric layer and the second interlayer dielectric layer; f, through holes are formed in the third interlayer dielectric layer, wherein the first interlayer dielectric layer is exposed out of the through holes; g, the first interlayer dielectric layer is removed through the through holes, and a second vacancy is formed; h, a cover layer is formed to fill the through holes. By means of the MOS transistor manufacturing method, the gate stray capacitance is effectively lowered, and device performance is improved.
Description
Technical field
The present invention relates to a kind of semiconductor device structure and manufacture method thereof, particularly, relate to a kind of mos transistor structure and manufacture method thereof.
Background technology
In MOSFET structure, parasitic gate electric capacity is the key factor affecting device frequency response and switching speed, determines grid RC time delay and RF frequency response.In order to improve device performance, we need the parasitic capacitance reducing MOSFET as much as possible, and day by day reduce along with device size, and the impact of parasitic capacitance is more and more significant, and the parasitic capacitance reducing device further significantly can improve device performance.
Parasitic capacitance is directly determined by the physical structure of device, and its size is directly related with the size of device.As shown in Figure 1, parasitic gate electric capacity mainly comprises three parts: i.e. inward flange parasitic capacitance C
if, outward flange parasitic capacitance C
ofand overlapping parasitic capacitance C
ov.Wherein, outward flange parasitic capacitance C
oftopmost part in grid parasitic capacitance, its size and grid length, gate height and the packing material between grid and source and drain closely related.By many restrictions, for the device of specific dimensions, its grid length and gate height cannot reduce further, and the change of device architecture also can cause other negative effect a lot, and the parasitic capacitance of device is difficult to be reduced further.
Summary of the invention
The embodiment provides a kind of mos transistor structure and preparation method thereof, reduce parasitic capacitance, optimize device performance.Particularly, the manufacture method that embodiments of the invention provide comprises the following steps: a. provides Semiconductor substrate, be positioned at the gate stack of described types of flexure, be positioned at the side wall of described gate stack both sides, and be arranged in the source-drain area of substrate of described gate stack both sides; B. on described semiconductor structure, form the first interlayer dielectric layer, the height of described first interlayer dielectric layer is less than the height of gate stack; C. remove the part that described first interlayer dielectric layer is positioned at the two ends away from gate stack, form the first room; D. in described first room, fill the second interlayer dielectric layer, its top is between ground floor between dielectric layer top and gate stack top; E. on described semiconductor structure, form dielectric layer between third layer cover the first interlayer dielectric layer and the second interlayer dielectric layer, and carry out chemico-mechanical polishing and make it expose top portions of gates; F. between described third layer, form the through hole exposing described first interlayer dielectric layer in dielectric layer and above described first interlayer dielectric layer; G. remove described first interlayer dielectric layer by described through hole, form the second room; H. form cap rock and fill described through hole.In one embodiment of the invention, described identical with the material of dielectric layer between third layer with the second interlayer dielectric layer, different from the material of the first interlayer dielectric layer.
In one embodiment of the invention, material that is described and dielectric layer between the second interlayer dielectric layer and third layer is silicon nitride or silica.
In one embodiment of the invention, the material of the first interlayer dielectric layer is silica or silicon nitride.
In one embodiment of the invention, between described third layer, the thickness of dielectric layer is 10 ~ 30nm.
In one embodiment of the invention, between the thickness of described first interlayer dielectric layer and described third layer, the thickness sum of dielectric layer equals the height of pseudo-gate stack.
In one embodiment of the invention, the material of described cap rock is identical with dielectric layer between third layer.
In one embodiment of the invention, described gate stack is follow-up can be removed, and such as, after step h, can also comprise step I. and remove pseudo-gate stack, form gate stack.Above-mentioned pseudo-gate stack both sides, refer to the both sides on pseudo-gate length direction.
Accordingly, embodiments of the invention additionally provide a kind of mos transistor structure, comprising: substrate; Be positioned at the gate stack of described types of flexure; Be positioned at the side wall of described gate stack both sides; Be positioned at the room of described side wall both sides; Cover the interlayer dielectric layer in described room; And be arranged in the source-drain area of described gate stack both sides substrate.Above-mentioned grid both sides, refer to the both sides in grid length direction.
In one embodiment of the invention, described interlayer dielectric layer covers described room, and its top is concordant with gate stack.
In one embodiment of the invention, the thickness of described interlayer dielectric layer is 10 ~ 30nm.
In one embodiment of the invention, described room is surrounded by interlayer dielectric layer, side wall and substrate.
According to mos transistor structure provided by the invention and manufacture method thereof, by forming hollow interlayer dielectric layer, room is formed in interlayer dielectric layer above grid and source-drain area, inter-level dielectric layer material before replacing with air, efficiently reduce the dielectric constant of outer edge zone material, weaken the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Accompanying drawing explanation
By reading the detailed description done non-limiting example done with reference to the following drawings, other features, objects and advantages of the present invention will become more obvious:
Fig. 1 is the schematic diagram of MOS device grid parasitic capacitance;
Fig. 2 ~ Figure 15 is the profile according to this each fabrication stage of MOS device in a specific embodiment of the present invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous parts.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
As shown in figure 15, An embodiment provides a kind of mos transistor structure, comprising: substrate 100; Be positioned at the gate stack 200 above described substrate 100; Be positioned at the side wall 102 of described gate stack 200 both sides; Be positioned at the room 340 of described side wall 102 both sides; Cover the interlayer dielectric layer 350 in described room 340; And be arranged in the source-drain area 202 of described gate stack 200 both sides substrate.Wherein, described interlayer dielectric layer 350 covers described room 340, and its top is concordant with gate stack 200; Wherein, the thickness of described interlayer dielectric layer 350 can be 10 ~ 30nm, and described room 340 is surrounded by interlayer dielectric layer 350, side wall 102 and substrate.
This substrate 100 is preferably a thin monocrystalline silicon layer, also can be the germanium-silicon alloy of monocrystalline.
Gate stack 200 can be only metal gates, also can be metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface have silicide.This gate stack can be that first grid technique is formed, and also can be that replacement gate process is formed, if replacement gate process formation, then the gate dielectric layer inside gate stack and metal level may cover on substrate with on the inwall of side wall.
According to the mos transistor structure that the embodiment of the present invention provides, by forming hollow interlayer dielectric layer, room is formed in interlayer dielectric layer above grid and source-drain area, inter-level dielectric layer material before replacing with air, efficiently reduce the dielectric constant of outer edge zone material, weaken the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Below in conjunction with accompanying drawing, manufacture method of the present invention is described in detail, comprises the following steps.It should be noted that, the accompanying drawing of each embodiment of the present invention is only the object in order to illustrate, so there is no necessity and draws in proportion.
As shown in Figure 2, substrate 100 is first provided.Described backing material is semi-conducting material, can be silicon, germanium, GaAs etc., and preferably, in the present embodiment, substrate 100 used is silicon substrate.Next pseudo-gate stack 101 is formed on described substrate 100 surface.Described pseudo-grid structure 101 can be individual layer, also can be multilayer.Pseudo-grid structure 101 can comprise polymeric material, amorphous silicon, polysilicon or TiN, and thickness can be 10nm ~ 200nm.In the present embodiment, pseudo-grid structure 101 comprises polysilicon and silicon dioxide, concrete, the method of chemical vapor deposition is adopted to fill polysilicon in grid room, its height is a little less than the follow-up height of side wall 10 ~ 20nm that will be formed, then square one-tenth layer of silicon dioxide dielectric layer on the polysilicon, formation method can be epitaxial growth, oxidation, CVD etc.Then the material layer of stand CMOS photoetching and the deposit of etching institute is adopted to form pseudo-gate stack.
Next, as shown in Figure 3, shallow doping is carried out to the substrate 100 of pseudo-grid structure 102 both sides, to form lightly-doped source drain region 201, can also Halo injection be carried out, to form Halo injection region.Wherein the dopant type of shallow doping is consistent with type of device, and the dopant type that Halo injects is contrary with type of device.
Next, as shown in Figure 4, deposit side wall 102 on described semiconductor structure.Concrete, such as can use the sacrifice side wall medium layer silicon nitride that LPCVD deposit 40nm ~ 80nm is thick, then be used in gate electrode both sides and form the side wall 102 that width is 30nm ~ 70nm.Side wall 102 can also by silica, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed.Side wall 102 can have sandwich construction.Side wall 102 can also be formed by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, as 30nm, 50nm or 80nm.
Next, carry out source-drain area injection as shown in Figure 5, first deposit a layer thickness is the silica dioxide medium layer (not shown) that 10nm ~ 35nm is thick, and with this dielectric layer for resilient coating, ion implantation source-drain area.For P-type crystal, dopant can be boron or boron fluoride or indium or gallium etc.For N-type crystal, dopant can be phosphorus or arsenic or antimony etc.Doping content is 5e10
19cm
-3~ 1e10
20cm
-3.
Next, described semiconductor structure forms the first interlayer dielectric layer 300, as shown in Figure 8.In order to carry out selective etch in subsequent technique, the second interlayer dielectric layer 320 that next material of described interlayer dielectric layer 300 will be formed is different with the material of dielectric layer between third layer 330.In the present embodiment, the material of described first interlayer dielectric layer 300 is silica.Wherein, the height of described first interlayer dielectric layer 300 is less than the height of pseudo-gate stack 101, and the distance at pseudo-gate stack 101 top of its distance from top can be 10 ~ 30nm.
Next, as shown in Figure 7, at described semiconductor structure top coating photoresist, and the step that exposes, develop is carried out according to the Normal practice of photoetching process, form photoresist mask plate 301, make it cover the part needing the first interlayer dielectric layer 300 retained, expose the part needing etching.Wherein, the width of the first interlayer dielectric layer 300 exposed can be 10 ~ 30nm.
Next, as shown in Figure 8, described semiconductor structure is etched, remove described first interlayer dielectric layer 300 and be positioned at two ends away from pseudo-gate stack, not by the part that photoresist mask plate 301 covers, form room.Concrete, adopt anisotropic etching, preferably, in the present embodiment, adopt dry plasma etch.
Next, in described room, fill the second interlayer dielectric layer 310, make its top between ground floor between dielectric layer 300 top and gate stack top, as shown in Figure 9.Wherein, described second interlayer dielectric layer 310 is different from the material of the first interlayer dielectric layer 300, and in the present embodiment, the material of the second interlayer dielectric layer 310 is silicon nitride.Concrete, adopt the method for chemical vapor deposition in room, fill the second interlayer dielectric layer 310, formation method can be epitaxial growth, oxidation, CVD etc.
Next, remove photoresist mask 301, described semiconductor structure is formed dielectric layer 320 between third layer, covers the first interlayer dielectric layer 300 and the second interlayer dielectric layer 310, as shown in Figure 10.Wherein, described second interlayer dielectric layer 310 can be identical with the material of dielectric layer between third layer 320, and in the present embodiment, between third layer, the material of dielectric layer 320 is silicon nitride.Concrete, adopt the method for chemical vapor deposition in room, fill the second interlayer dielectric layer 310, formation method can be epitaxial growth, oxidation, CVD etc., and between the third layer of formation, the thickness of dielectric layer 320 can be 10 ~ 30nm.
Next, between described third layer, dielectric layer 320 forms through hole 330, as shown in figure 11.Concrete, first photoetching process conveniently, described semiconductor structure is formed photoresist mask, covering will form dielectric layer 320 and pseudo-gate stack 101 between the third layer beyond through hole 330, next, adopt anisotropy and/or isotropic selective etching, form described through hole 330, until expose the first interlayer dielectric layer 300 be positioned between third layer below dielectric layer 320.
Next, adopt selective etch, by through hole 330, first interlayer dielectric layer 300 is etched, until remove the first interlayer dielectric layer 300, in its formation room, position 340, as shown in figure 12.Concrete, wet selective can be adopted to etch, and the etching selection ratio of corrosive liquid used to silica and SiClx is greater than 30:1.
Next, form cap rock 360 and fill described through hole 330, its object is to make the interlayer dielectric layer surface of this semiconductor structure complete, be convenient to the carrying out of subsequent technique.Concrete, first, deposit sacrificial material layer 400 on described semiconductor structure, the material of described sacrificial material layer 400 is identical with the material of the second interlayer dielectric layer 310, and carries out chemico-mechanical polishing, until expose gate stack top.Concrete technology step as shown in figure 13, after completing CMP, forms cap rock 360 at described through hole 330 top, as shown in figure 14.Afterwards, between described second interlayer dielectric layer 310, third layer, dielectric layer 320 and cap rock 360 form interlayer dielectric layer 350 together.
Next, remove described pseudo-grid structure 101, form pseudo-grid room.Removing pseudo-grid structure 101 can adopt wet etching and/or dry quarter to remove.In one embodiment, using plasma etching.Next, as shown in figure 15, in grid room, gate stack 200 is formed.Described gate stack 200 comprises gate dielectric layer and gate contact layer, and described gate contact layer can be only metal gates, also can be metal/Polysilicon Composite Structures grid, wherein polysilicon upper surface have silicide.
According to the method for the formation mos transistor structure that the embodiment of the present invention provides, room is formed in interlayer dielectric layer above grid and source-drain area, a part of inter-level dielectric layer material is replaced with air, efficiently reduce the dielectric constant of outer edge zone material, weaken the capacitance coupling effect between source-drain area and grid simultaneously, thus efficiently reduce parasitic capacitance, optimize device performance.
Although describe in detail about example embodiment and advantage thereof, being to be understood that when not departing from the protection range of spirit of the present invention and claims restriction, various change, substitutions and modifications can being carried out to these embodiments.For other examples, those of ordinary skill in the art should easy understand maintenance scope in while, the order of processing step can change.
In addition, range of application of the present invention is not limited to the technique of the specific embodiment described in specification, mechanism, manufacture, material composition, means, method and step.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique existed at present or be about to develop, mechanism, manufacture, material composition, means, method or step later, wherein their perform the identical function of the corresponding embodiment cardinal principle that describes with the present invention or obtain the identical result of cardinal principle, can apply according to the present invention to them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (12)
1. a manufacture method for MOS transistor, comprising:
A., Semiconductor substrate (100) is provided, is positioned at the gate stack (101) of described types of flexure, be positioned at the side wall (102) of described gate stack both sides, and be arranged in the source-drain area (202) of substrate of described gate stack both sides;
B. on described semiconductor structure, form the first interlayer dielectric layer (300), the height of described first interlayer dielectric layer (300) is less than the height of gate stack (101);
C. remove the part that described first interlayer dielectric layer (300) is positioned at the two ends away from gate stack, form the first room;
D. in described first room, fill the second interlayer dielectric layer (310), its top is between ground floor between dielectric layer top and gate stack top;
E. on described semiconductor structure, form dielectric layer between third layer (320) cover the first interlayer dielectric layer (300) and the second interlayer dielectric layer (310), and carry out chemico-mechanical polishing and make it expose top portions of gates;
F. between described third layer, in dielectric layer (320), form the through hole (330) exposing described first interlayer dielectric layer (300);
G. remove described first interlayer dielectric layer (300) by described through hole (330), form the second room (340);
H. form cap rock (360) and fill described through hole (330).
2. manufacture method according to claim 1, is characterized in that, described identical with the material of dielectric layer between third layer (320) with the second interlayer dielectric layer (310), different from the material of the first interlayer dielectric layer (300).
3. manufacture method according to claim 1 and 2, is characterized in that, between described second interlayer dielectric layer (310) and third layer, the material of dielectric layer (320) is silicon nitride or silica.
4. manufacture method according to claim 1 and 2, is characterized in that, the material of the first interlayer dielectric layer (300) is silica or silicon nitride.
5. manufacture method according to claim 1, is characterized in that, between described third layer, the thickness of dielectric layer (320) is 10 ~ 30nm.
6. manufacture method according to claim 1, is characterized in that, the material of described cap rock (360) is identical with dielectric layer between third layer (320).
7. the manufacture method according to right 7, is characterized in that, after step h, the method also comprises step:
I. remove described gate stack (101), form grid room, in described room, form alternative gate stack (200).
8. a mos transistor structure, comprising:
Substrate (100);
Be positioned at the gate stack (200) of described substrate (100) top;
Be positioned at the side wall (102) of described gate stack (200) both sides;
Be positioned at the room (340) of described side wall (102) both sides;
Cover the interlayer dielectric layer (350) of described room (340);
And be arranged in the source-drain area (202) of described gate stack (200) both sides substrate.
9. transistor arrangement according to claim 8, is characterized in that, described interlayer dielectric layer (350) covers described room (340), and its top is concordant with gate stack (200).
10. transistor arrangement according to claim 8, is characterized in that, the thickness of described interlayer dielectric layer (350) is 10 ~ 30nm.
11. transistor arrangements according to claim 8, is characterized in that, described room (340) are surrounded by interlayer dielectric layer (350), side wall (102) and substrate.
12. transistor arrangements according to claim 8, is characterized in that, described room (340) are positioned at source-drain area (202) top.
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| CN102769017A (en) * | 2011-05-04 | 2012-11-07 | 海力士半导体有限公司 | Semiconductor device and method of manufacturing the same |
| US20130134496A1 (en) * | 2011-11-30 | 2013-05-30 | Sung-Soo Ahn | Semiconductor devices and methods of manufacturing the semiconductor devices |
| CN103390644A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
-
2013
- 2013-12-20 CN CN201310713804.1A patent/CN104733318B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004128505A (en) * | 2002-09-30 | 2004-04-22 | Samsung Electronics Co Ltd | Nonvolatile memory device and its manufacturing method |
| US20070184615A1 (en) * | 2005-12-30 | 2007-08-09 | Stmicroelectronics S.R.L. | Process for Manufacturing a Non-Volatile Memory Electronic Device Integrated on a Semiconductor Substrate and Corresponding Device |
| CN102769017A (en) * | 2011-05-04 | 2012-11-07 | 海力士半导体有限公司 | Semiconductor device and method of manufacturing the same |
| US20130134496A1 (en) * | 2011-11-30 | 2013-05-30 | Sung-Soo Ahn | Semiconductor devices and methods of manufacturing the semiconductor devices |
| CN103390644A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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