CN104717484A - Video display control method, video processing circuit and video display device - Google Patents
Video display control method, video processing circuit and video display device Download PDFInfo
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Abstract
The invention provides a video display control method, a related video processing circuit and a related video display device. Particularly, the method is carried out in the video display system, the video processing circuit is located in the video display system, and the video processing circuit operates according to the method. The method comprises the steps that two of multiple buffers are dynamically utilized to serve as multiple on-screen buffers for multiple three-dimensional frames, wherein the multiple buffers are located in the video display system; any one of the two of the multiple buffers is utilized to serve as one on-screen buffer, and at least another one of the multiple buffers is dynamically utilized to serve as at least one off-screen buffer for at least one three-dimensional frame. According to the video display control method, the related video processing circuit and the related video display device, the optimal overall efficiency can be kept constantly.
Description
This case to be application number be 201080018388.8 divisional application, the original bill applying date is on November 26th, 2010, and denomination of invention is " performing the method for video display and control, video processing circuits and video display system ".
Technical field
The invention relates to three-dimensional (Three-Dimensional, hereinafter referred to as 3D) display and control, espespecially a kind ofly carry out the method for video display and control, relevant video processing circuits and relevant video display system.
Background technology
Display and control is an important subject under discussion for traditional 3D display system.According to correlation technique, be used for temporarily storing estimate the 3D picture (Frame) that will show buffer module not by under the situation that properly controls, some problem can be produced.Such as: during when the traditional video processing circuits in the 3D display system that this is traditional and without appropriate design, may occur so-calledly to tear phenomenon (Tearing Artifact), what this can bring user's extreme difference views and admires experience.Especially, in order to occupation rate of expanding market, may have the product needing to produce some low cost, such as its associated hardware resource is the product implemented with element that is cheap or low order.But, utilize these elements that are cheap or low order usually can be with and serve side effect.So traditional 3D display system cannot make user please oneself usually, therefore, need a kind of method of novelty to promote the usefulness of the display and control of a video display system.
Summary of the invention
An object of the present invention is that providing a kind of carries out the method for video display and control, relevant video processing circuits and relevant video display system, views and admires the poor problem of experience to solve user.
Another object of the present invention is to provide a kind of and carry out the method for video display and control, relevant video processing circuits and relevant video display system, to reach best overall usefulness.
Another object of the present invention is to provide a kind of and carry out the method for video display and control, relevant video processing circuits and relevant video display system, even if to be under the situation implemented with element that is cheap or low order at associated hardware resource, still can overall efficiency be maintained.
There is provided a kind of method of carrying out video display and control in preferred embodiment of the present invention, wherein the method is intended to be in a video display system and carries out video display and control.The method includes: dynamically utilize both conducts of multiple buffer for multiple three-dimensional picture (Three-Dimensional Frame, 3D Frame) multiple screen (On-Screen) buffer, wherein the plurality of buffer is arranged in this video display system, wherein, the plurality of both should be used for storing expectation respectively and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device; And in utilize the plurality of buffer this both in any one as one during ping buffer device, dynamically utilize other buffer at least one in the plurality of buffer as at least one three-dimensional picture at least one from screen (Off-Screen) buffer, wherein, alternately should store from ping buffer device should both should be used for storing expectation and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device respectively.
There is provided a kind of relevant video processing circuits in preferred embodiment of the present invention, wherein this video processing circuits is arranged in a video display system.This video processing circuits comprises a de-multiplexer (Demultiplexer), two Video Decoders, a buffer module and a controller, and wherein this controller is used to the running controlling this video processing circuits.This de-multiplexer is used to a three-dimensional video stream solution multiplex (MUX) (Demultiplex) to become a left video stream and a right video flowing, and this two Video Decoder is used to decode respectively, this left video stream and this right video flowing are to produce multiple three-dimensional picture.In addition, this buffer module is used to temporarily store these three-dimensional pictures, and wherein this buffer module comprises multiple buffer.Under the control of this controller, both multiple at ping buffer device as the three-dimensional picture at least partially in these three-dimensional pictures that this buffer module dynamically utilizes the plurality of buffer, wherein, the plurality of both should be used for storing expectation respectively and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device.In addition, under the control of this controller, in utilize the plurality of buffer this both in any one as one during ping buffer device, this buffer module dynamically utilizes at least one from ping buffer device as at least one three-dimensional picture of other buffer at least one in the plurality of buffer, wherein, alternately should store from ping buffer device should both should be used for storing expectation and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device respectively.
A kind of relevant video display system is provided in preferred embodiment of the present invention, wherein this video display system comprises a video processing circuits, and this video processing circuits comprises a de-multiplexer, two Video Decoders, a buffer module and a controller, and this controller is used to the running controlling this video processing circuits.This de-multiplexer is used to a three-dimensional video stream solution multiplex (MUX) to become a left video stream and a right video flowing, and this two Video Decoder is used to decode respectively, this left video stream and this right video flowing are to produce multiple three-dimensional picture.In addition, this buffer module is used to temporarily store these three-dimensional pictures, and wherein this buffer module comprises multiple buffer.Under the control of this controller, both multiple at ping buffer device as the three-dimensional picture at least partially in these three-dimensional pictures that this buffer module dynamically utilizes the plurality of buffer, wherein, the plurality of both should be used for storing expectation respectively and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device.In addition, under the control of this controller, in utilize the plurality of buffer this both in any one as one during ping buffer device, this buffer module dynamically utilizes at least one from ping buffer device as at least one three-dimensional picture of other buffer at least one in the plurality of buffer; Wherein, alternately should store from ping buffer device should both should be used for storing expectation and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device respectively.
Compared to prior art, method of the present invention, relevant video processing circuits and relevant video display system, even if be still can maintain overall efficiency under the situation implemented with element that is cheap or low order at associated hardware resource.
Accompanying drawing explanation
Figure 1A and Figure 1B illustrates respectively according to the combination to relevant three-dimensional display module of a kind of video display system of the present invention one first embodiment and this video display system.
Fig. 2 A and Fig. 2 B illustrate a kind of video display system of foundation the present invention one second embodiment and relevant TV station respectively.
Fig. 3 A and Fig. 3 B illustrates two 3D pictures according to one embodiment of the invention respectively.
Fig. 3 C illustrates the mistake display result of the traditional video display system in correlation technique.
Fig. 4 is a kind of flow chart carrying out the method for video display and control according to one embodiment of the invention.
Fig. 5 is the exemplary cushioning control of the multiple buffers involved in an embodiment of the method shown in Fig. 4.
Fig. 6 A to Fig. 6 D is the exemplary cushioning control of the multiple buffers involved in another embodiment of the method shown in Fig. 4.
Fig. 7 A to Fig. 7 D is the exemplary cushioning control of the multiple buffers involved in another embodiment of the method shown in Fig. 4.
Fig. 8 A to Fig. 8 C is the implementation detail involved in another embodiment of the method shown in Fig. 4.
Embodiment
Some vocabulary is employed to censure specific element in the middle of patent specification and appended claim.One of ordinary skill in the art, hardware manufacturer may call same element with different nouns.This specification and follow-up claim are not used as the mode of distinguish one element from another with the difference of title, but are used as the criterion of differentiation with element difference functionally." comprising " mentioned in the middle of specification and follow-up claim is in the whole text an open term, therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word at this is comprise directly any and be indirectly electrically connected means.Therefore, if describe a first device in literary composition to be coupled to one second device, then represent this first device and directly can be electrically connected in this second device, or be indirectly electrically connected to this second device by other devices or connection means.
Please refer to Figure 1A, Figure 1A is a kind of video display system 100 according to the present invention one first embodiment.As shown in Figure 1A, video display system 100 comprises a video processing circuits, and this video processing circuits comprises a de-multiplexer (Demultiplexer) 110, two Video Decoder 120L and 120R, controller 130, buffer module 140 and a multiplexer (Multiplexer) 150, its middle controller 130 is used to the running controlling above-mentioned video processing circuits.In the present embodiment, buffer module 140 comprises a buffering switch unit 142 and multiple buffer 144 (not being shown in Figure 1A).Such as: buffering switch unit 142 is by utilizing according at least one switch-over control signal S
sWand some commutation circuit of running is implemented.Again such as: buffering switch unit 142 is by utilizing an interface circuit to implement, and wherein this interface circuit is used to according to switch-over control signal S
sWcontrol the access to buffer 144.
According to the present embodiment, de-multiplexer 110 is used to a three-dimensional (Three-Dimensional, hereinafter referred to as " 3D ") video flowing 108 separates multiplex (MUX) (Demultiplex) becomes an a left video stream 118L and right video flowing 118R, and two Video Decoder 120L and 120R are used to decode left video stream 118L and right video flowing 118R respectively to produce the multiple 3D pictures (Frame) estimating to show.Such as: these 3D pictures can produce based on decoded material 128L and 128R.Again such as: these 3D pictures can be obtained by decoded material 128L and 128R.Again such as: these 3D pictures can produce based on decoded material 128L and 128R and or can be obtained by decoded material 128L and 128R.In addition, buffer module 140 is used to temporarily store these 3D pictures.Under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer module 140 dynamically utilize the plurality of buffer 144 both shielding (On-Screen) buffer as the multiple of the picture of 3D at least partially in these 3D pictures.In addition, under the control of controller 130, especially at switch-over control signal S
sWcontrol under, in utilize the plurality of buffer 144 this both in any one as one during ping buffer device, buffer module 140 dynamically utilize other buffer at least one in the plurality of buffer 144 as at least one 3D picture at least one from screen (Off-Screen) buffer.
By means of multiplexer 150, buffer module 140 can utilize respectively the plurality of buffer 144 this both as within the different cycles at ping buffer device, especially as in different vertical sync period (such as: the different cycle of a vertical synchronizing signal VSYNC) at ping buffer device.Specifically, signal S is selected according to carry out self-controller 130 one
sEL, multiplexer 150 can be used to the output that multiplex (MUX) selects the one in (Multiplex) these buffers 144, the output of the buffer in both these of especially buffer 144.Such as: buffer 144 this both comprise the situation of one first buffer Buf (1) and one second buffer Buf (2) under, multiplexer 150 can multiplex (MUX) select the output of the first buffer Buf (1) as one the one 3D picture estimating preferentially to show, then multiplex (MUX) selects the output of the second buffer Buf (2) as one the 2nd 3D picture estimating to show after a while, wherein estimates that the whole picture in these 3D pictures that will show all is output by exporting picture signal 158.Controller 130 can control to select signal S
sELbe in the state corresponded respectively in multiple states of these buffers 144, to notify that the output of the specific buffers that will select to be estimated by multiplexer 150 about that time.
In the present embodiment, an optical disk player is by for the example for video display system 100, and wherein this optical disk player can access a CD-RW discsCD-RW 8, and CD-RW discsCD-RW 8 stores 3D program or content; Therefore, video display system 100 is signable in Figure 1B is " optical disk player ".Video display system 100 can be coupled to a 3D display unit 58, and display unit 58 comprises an a display module 60 such as 3D display module, and wherein display module 60 such as this 3D display module can be used to show these above-mentioned 3D pictures.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, one second embodiment such as shown in Fig. 2 A and Fig. 2 B, the 3D display module being used for showing these above-mentioned 3D pictures may be implemented in the middle of above-mentioned video display system; In response to the change on framework, above-mentioned video display system changes and indicates with label 100 '.Such as: the 3D display module be implemented in video display system 100 ' can be the 3D display module 160 shown in Fig. 2 A.In this change case, a TV is by for the example for video display system 100 ', and wherein this TV can receive the broadcast singal from a TV station 4, and TV station 4 can broadcast 3D program or content; Therefore, video display system 100 ' is signable in Fig. 2 B is " TV ".
Fig. 3 A and Fig. 3 B illustrates two the 3D pictures 12 and 14 according to one embodiment of the invention respectively.Such as: two 3D pictures 12 and 14 represent a 3D picture that above-mentioned expectation will preferentially show and the 2nd 3D picture that above-mentioned expectation will show after a while respectively.Especially, 3D picture 12 is the left 3D pictures estimating to show for user's left eye, and 3D picture 14 is the right 3D pictures estimating to show for user's right eye.Based on the framework of this first embodiment (or its change case such as this second embodiment), the problem of correlation technique such as so-called phenomenon (Tearing Artifact) of tearing disturbs the subject under discussion of people by being no longer.Specifically, the all mistake display results 24 as shown in Figure 3 C of inappropriate display result of correlation technique will occur never in any video display system implemented according to the present invention, and wherein mistake display result 24 is made up of the lower part 12B in the upper part 14A in two parts 14A and the 14B in the middle of 3D picture 14 and two parts 12A and the 12B in the middle of 3D picture 12.Based on the framework of this first embodiment (or its change case such as this second embodiment), even if be under the situation implemented with element that is cheap or low order at associated hardware resource, still overall efficiency can be maintained.
Fig. 4 is a kind of flow chart carrying out the method 910 of video display and control according to one embodiment of the invention, and wherein the method carries out video display and control in all video display systems described above of a video display system.Method 910 shown in Fig. 4 can be applicable to the video display system 100 (or the video display system 100 ' shown in Fig. 2 A) shown in Figure 1A, is especially applied to the video processing circuits in the middle of any one in this first embodiment and this second embodiment (and respective change case).The method is described as follows:
In 912 steps, this video processing circuits (buffer module 140 especially under the control of controller 130) dynamically utilizes both of multiple buffer, both these of all multiple buffers 144 described above, multiple at ping buffer device as the picture of 3D at least partially in these 3D pictures.Such as: carrying out the switch-over control signal S of self-controller 130
sWcontrol under, buffer module 140 dynamically utilize the plurality of buffer 144 this both multiple at ping buffer device as the picture of 3D at least partially in these 3D pictures.
In 914 steps, in utilize the plurality of buffer 144 this both in any one as one during ping buffer device, this video processing circuits (buffer module 140 especially under the control of controller 130) dynamically utilizes at least one from ping buffer device as at least one 3D picture of other buffer at least one in the plurality of buffer 144.Such as: carrying out the switch-over control signal S of self-controller 130
sWcontrol under, in utilize the plurality of buffer 144 this both in any one as one during ping buffer device, buffer module 140 dynamically utilizes at least one from ping buffer device as at least one 3D picture of other buffer at least one in the plurality of buffer 144.
According to some change case of the present embodiment, comprise step 912 and can repeatedly carry out with the workflow of step 914.According to some change case of the present embodiment, the part running of step 912 and or the part running of step 914 can be arranged in the middle of at least one independently step.According to some change case of the present embodiment, the part running of step 912 and or the part running of step 914 can be arranged in the middle of a step of both having deposited.
Generally speaking, the quantity of the multiple buffers 144 involved by method 910 shown in Fig. 4 can be odd number or even number.Such as: in the middle of some embodiment of the present invention such as embodiment illustrated in fig. 5 and some change case, the quantity of the plurality of buffer 144 can be even number.Again such as: in the middle of each embodiment shown in some other embodiment of the present invention such as Fig. 6 A to Fig. 6 D and Fig. 7 A to Fig. 7 D and some change case thereof, the quantity of the plurality of buffer 144 can be odd number.
As shown in Figure 5, the quantity of the plurality of buffer 144 can equal four, and wherein buffer 144 comprises one first group of buffer 1441L and 1441R and one second group of buffer 1442L and 1442R.Especially, buffer 1441L and 1442L is used to temporarily store the multiple left 3D picture estimating to show for user's left eye, and buffer 1441R and 1442R is used to temporarily store the multiple right 3D picture estimating to show for user's right eye.
Under the control of controller 130, especially at switch-over control signal S
sWcontrol under, when buffer module 140 utilize one in buffer 1441L and 1442L as one at ping buffer device time, buffer module 140 utilizes another one in buffer 1441L and 1442L as one from ping buffer device.Such as: when buffer module 140 utilize buffer 1441L as one at ping buffer device time, buffer module 140 utilizes buffer 1442L as one from ping buffer device.Again such as: when buffer module 140 utilize buffer 1442L as one at ping buffer device time, buffer module 140 utilizes buffer 1441L as one from ping buffer device.
Similarly, under the control of controller 130, especially at switch-over control signal S
sWcontrol under, when buffer module 140 utilize one in buffer 1441R and 1442R as one at ping buffer device time, buffer module 140 utilizes another one in buffer 1441R and 1442R as one from ping buffer device.Such as: when buffer module 140 utilize buffer 1441R as one at ping buffer device time, buffer module 140 utilizes buffer 1442R as one from ping buffer device.Again such as: when buffer module 140 utilize buffer 1442R as one at ping buffer device time, buffer module 140 utilizes buffer 1441R as one from ping buffer device.
So, once only have a buffer can be used as one at ping buffer device in the middle of buffer 1441L and 1442L, and in the middle of buffer 1441R and 1442R, once only have a buffer can be used as one at ping buffer device, both these of multiple buffers 144 wherein described in step 912 comprise the one in buffer 1441L and 1442L and the one separately comprised in buffer 1441R and 1442R, will respectively for one group of 3D picture (that is, a left 3D picture and a right 3D picture) that user two shows for being used for exporting expectation.Label 144-1 is used to representative: in a particular moment, both these of the multiple buffers 144 described in step 912; And label 144-2 is used to representative: in this particular moment, this other buffer at least one in the multiple buffers 144 described in step 914.
Please refer to Fig. 6 A, the quantity of the plurality of buffer 144 can equal three, and wherein buffer 144 comprises buffer 1441,1442 and 1443.Especially, as shown in the upper part 144-1 in Fig. 6 A, both in buffer 1441,1442 and 1443 are chosen as both these of multiple buffers 144 described in step 912 in a particular moment.In addition, as shown in the lower part 144-2 in Fig. 6 A, the another one in buffer 1441,1442 and 1443 is chosen as this other buffer at least one in the multiple buffers 144 described in step 914 in this particular moment.For the ease of understanding, Fig. 6 A illustrates the exemplary situation in this particular moment: buffer 1441 and 1442 be chosen as multiple buffers 144 described in step 912 this both and this other buffer at least one in buffer 1443 is chosen as described in step 914 multiple buffers 144.
Under the control of controller 130, especially at switch-over control signal S
sWcontrol under, " buffer module 140 utilize buffer 1441,1442 and 1443 both as two at ping buffer device " and under the situation of " these two are used for storing the left 3D picture estimating to show for user's left eye and the right 3D picture estimating to show for user's right eye respectively at ping buffer device ", buffer module 140 utilizes other buffer in buffer 1441,1442 and 1443 as one from ping buffer device.Such as: utilize buffer 1441 and 1442 as these two under the situation of ping buffer device in buffer module 140, buffer module 140 utilizes other buffer 1443 as one from ping buffer device.So buffer 1441 and 1442 can be used to export that estimate will respectively for one group of 3D picture (such as: this left 3D picture and this right 3D picture) that user two shows.
Please refer to Fig. 6 B, conventional letter Buf (1), Buf (2) and Buf (3) are used for representing buffer 1441,1442 and 1443 respectively.In addition, symbol L (i) and R (i) are used for representing left 3D picture and right 3D picture respectively, and wherein i can be integer, especially the integer of nonnegative number.When buffer Buf (1) and Buf (2) store a left 3D picture L (0) and a right 3D picture R (0) respectively, buffer Buf (3) can be used to draw next left 3D picture L (1), and is therefore illustrated as being with hypographous block so that understand.Each transition (Transition) of the content of buffer Buf (1), Buf (2) and Buf (3) is corresponding to all vertical synchronizing signal VSYNC described above of a vertical synchronizing signal (not being shown in Fig. 6 B).Due to the method 910 shown in application drawing 4, the content of buffer Buf (1) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence { L (0), R (1), R (1), R (1), L (3) ... in relevant 3D picture.In addition, the content of buffer Buf (2) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence { R (0), R (0), L (2), L (2), L (2) ... in relevant 3D picture.In addition, the content of buffer Buf (3) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence { L (1), L (1), L (1), R (2), R (2) ... in relevant 3D picture.
Please refer to Fig. 6 C, vertical synchronizing signal VSYNC is illustrated in that this is for reference, and wherein buffer Buf (1), Buf (2) correspond to the pulse in vertical synchronizing signal VSYNC with each transition of the content of Buf (3).Some drawing for order such as drawing for order DRAW (L (0)), DRAW (R (0)), DRAW (L (1)), DRAW (R (1)), DRAW (L (2)), DRAW (R (2)) ... Deng be used for respectively drawing these 3D pictures L (0), R (0), L (1), R (1), L (2), R (2) ... Deng, some picture wherein in the middle of these 3D pictures can illustrate as being with hypographous block so that understand.In addition, some upset (Flip) instruction such as overturns that buffer Buf (1), Buf (2) and Buf (3) overturn by each pulse of then arriving time point separately that instruction Flip (1), Flip (2) and Flip (3) be used for respectively in vertical synchronizing signal VSYNC is ping buffer device (it illustrates the block into describing with thick line).In addition, the meaning representative in the present embodiment of the symbol X shown in Fig. 6 C is " undefined or determined " (Undefined/Undetermined), is wherein denoted as the normally undefined or determined of the content of buffer of symbol X.
Please note, in the present embodiment, when the one in buffer Buf (1), Buf (2) and Buf (3) be just reversed be one at ping buffer device time, the buffer storing the content just removed from screen just becomes and is in one from screen state.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, be greater than the situation of three in the quantity of buffer 144 under, both these of multiple buffers 144 described in step 912 (such as: the upper part 144-1 in Fig. 6 A) can be in one in screen state in above-mentioned particular moment simultaneously, and this other buffer at least one in multiple buffers 144 described in step 914 can be in one from screen state in this particular moment.In addition, at the end in current cycle, the time point that a certain pulse of then arriving in such as vertical synchronizing signal VSYNC occurs, two buffers of the script that those are regarded as " both these of the multiple buffers 144 described in step 912 " enter one immediately from screen state simultaneously, wherein in buffer 144 some other both instead of two buffers originally and become simultaneously and be in one in screen state.
In addition, some drawing for order such as drawing for order DRAW (L (0)), DRAW (R (0)), DRAW (L (1)), DRAW (R (1)), DRAW (L (2)), DRAW (R (2)) ... Deng by for the example of instruction for being used for producing or obtain the up-to-date 3D picture in Fig. 6 C illustrated embodiment.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, the instruction of other kind can be used to produce or obtain up-to-date 3D picture.
Please refer to Fig. 6 D, workflow 920 is the implementation detail involved in the special case of the present embodiment of the method 910 shown in Fig. 4, the source code of available virtual at least partially (Pseudo Code) wherein in these implementation details illustrates, so that understand the buffer control shown in Fig. 6 C.Especially, workflow 920 can be applicable to above-mentioned video processing circuits.Note that the workflow 920 (especially its step) shown in Fig. 6 D just for illustrative purposes, not limitation of the present invention.Workflow 920 is described as follows:
In 922 steps, controller 130 performs instruction i=0 and j=1, so that the initial value of index i and j is set as 0 and 1 respectively.
In 924-1 step, under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer module 140 (or the buffering switch unit 142 in it) selects buffer Buf (j mod 3) for left 3D picture L (i), and wherein symbol " mod " represents the operator of mould running (Modulo Operation).
In 924-2 step, above-mentioned video processing circuits (especially controller 130 and or decoder 120L) performs drawing for order Draw (L (i)), to draw left 3D picture L (i).Drawing for order Draw (L (i)) can be a program, and this program package is containing the multiple instructions for left 3D picture L (i), and therefore drawing for order Draw (L (i)) can comprise multiple sub-step.
In 924-3 step, controller 130 performs upset instruction Flip (j mod 3), being one at ping buffer device by buffer Buf (j mod 3) upset.Such as: under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer Buf (j mod 3) upset is one at ping buffer device by buffer module 140 (or the buffering switch unit 142 in it), wherein multiplexer 150 is used to from estimating that one group of 3D picture (that is, a left 3D picture and a right 3D picture) that will show for user two is respectively selected or multiplex (MUX) selects (Select/Multiplex) 3D picture.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, under the control of controller 130, especially at selection signal S
sELcontrol under, buffer Buf (j mod 3) upset is one at ping buffer device by multiplexer 150.
In 924-4 step, controller 130 performs instruction j++, to increase the numerical values recited of index j.
In 926-1 step, under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer module 140 (or the buffering switch unit 142 in it) selects buffer Buf (j mod 3) for right 3D picture R (i).
In 926-2 step, above-mentioned video processing circuits (especially controller 130 and or decoder 120R) performs drawing for order Draw (R (i)), to draw right 3D picture R (i).Drawing for order Draw (R (i)) can be a program, and this program package is containing the multiple instructions for right 3D picture R (i), and therefore drawing for order Draw (R (i)) can comprise multiple sub-step.
In 926-3 step, controller 130 performs upset instruction Flip (j mod 3), being one at ping buffer device by buffer Buf (j mod 3) upset.Such as: under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer Buf (j mod 3) upset is one at ping buffer device by buffer module 140 (or the buffering switch unit 142 in it), wherein multiplexer 150 is used to from estimating that one group of 3D picture (that is, a left 3D picture and a right 3D picture) that will show for user two is respectively selected or multiplex (MUX) selects a 3D picture.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, under the control of controller 130, especially at selection signal S
sELcontrol under, buffer Buf (j mod 3) upset is one at ping buffer device by multiplexer 150.
In 926-4 step, controller 130 performs instruction j++, to increase the numerical values recited of index j.
In 928 steps, controller 130 checks whether needs the flow process 920 that quits work.The flow process 920 that quits work is needed, then power cut-off flow process 920 when detecting; Otherwise, enter step 929.
In 929 steps, controller 130 performs instruction i++, to increase the numerical values recited of index i.After execution step 929, reenter step 924-1.
Please refer to Fig. 7 A, the quantity of the plurality of buffer 144 can equal five, and wherein buffer 144 comprises buffer 1441,1442,1443,1444 and 1445.Especially, as shown in the upper part 144-1 in Fig. 7 A, both of buffer 1441,1442,1443,1444 and 1445 are chosen as both these of multiple buffers 144 described in step 912 in a particular moment.In addition, as shown in the lower part 144-2 in Fig. 7 A, other buffer in buffer 1441,1442,1443,1444 and 1445 is chosen as this other buffer at least one in the multiple buffers 144 described in step 914 in this particular moment.For the ease of understanding, Fig. 7 A illustrates the exemplary situation in this particular moment: buffer 1441 and 1442 be chosen as multiple buffers 144 described in step 912 this both and this other buffer at least one in buffer 1443,1444 and 1445 is chosen as described in step 914 multiple buffers 144.
Under the control of controller 130, especially at switch-over control signal S
sWcontrol under, " buffer module 140 utilize buffer 1441,1442,1443,1444 and 1445 both as two at ping buffer device " and under the situation of " these two are used for storing the left 3D picture estimating to show for user's left eye and the right 3D picture estimating to show for user's right eye respectively at ping buffer device ", buffer module 140 utilizes other buffer in buffer 1441,1442,1443,1444 and 1445 as from ping buffer device.Such as: buffer module 140 utilize buffer 1441 and 1442 as above-mentioned these two under the situation of ping buffer device, buffer module 140 utilizes other buffer 1443,1444 and 1445 as from ping buffer device.So buffer 1441 and 1442 can be used to export that estimate will respectively for one group of 3D picture (such as: this left 3D picture and this right 3D picture) that user two shows.
Please refer to Fig. 7 B, conventional letter Buf (1), Buf (2), Buf (3), Buf (4) and Buf (5) are used for representing buffer 1441,1442,1443,1444 and 1445 respectively.When buffer Buf (1) and Buf (2) store a left 3D picture L (0) and a right 3D picture R (0) respectively, buffer Buf (1), Buf (2), Buf (3), Buf (4) can be used to draw next left 3D picture L (1) with another buffer such as buffer Buf (3) in Buf (5), and are therefore illustrated as being with hypographous block so that understand.Buffer Buf (1), Buf (2), Buf (3), Buf (4) correspond to all vertical synchronizing signal VSYNC described above of a vertical synchronizing signal (not being shown in Fig. 7 B) with each transition of the content of Buf (5).Due to the method 910 shown in application drawing 4, the content of buffer Buf (1) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence { L (0), L (0), L (0), R (2), R (2) ... in relevant 3D picture.In addition, the content of buffer Buf (2) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence { R (0), R (0), R (0), R (0), L (3) ... in relevant 3D picture.In addition, the content of buffer Buf (3) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence { L (1), L (1), L (1), L (1), L (1) ... in relevant 3D picture.The meaning representative in the present embodiment for buffer Buf (4) and Buf (5), the symbol X shown in Fig. 7 B is " undefined or determined ", is wherein denoted as the normally undefined or determined of the content of buffer of symbol X.So, the content of buffer Buf (4) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence X, R (1), R (1), R (1), R (1) ... in relevant element or 3D picture.In addition, the content of buffer Buf (5) in the different cycles of vertical synchronizing signal VSYNC can be respectively sequence X, X, L (2), L (2), L (2) ... in relevant element or 3D picture.
Please refer to Fig. 7 C, vertical synchronizing signal VSYNC is illustrated in that this is for reference, and wherein buffer Buf (1), Buf (2), Buf (3), Buf (4) correspond to the pulse in vertical synchronizing signal VSYNC with each transition of the content of Buf (5).Some drawing for order such as drawing for order DRAW (L (0)), DRAW (R (0)), DRAW (L (1)), DRAW (R (1)), DRAW (L (2)), DRAW (R (2)) ... Deng be used for respectively drawing these 3D pictures L (0), R (0), L (1), R (1), L (2), R (2) ... Deng, some picture wherein in the middle of these 3D pictures can illustrate as being with hypographous block so that understand.In addition, some each pulse of then arriving that upset instruction such as overturns instruction Flip (1), Flip (2), Flip (3), Flip (4) and Flip (5) are used for respectively in vertical synchronizing signal VSYNC time point separately by buffer Buf (1), Buf (2), Buf (3), Buf (4) overturns with Buf (5) is ping buffer device (it is the block described with thick line).Similarly, the meaning representative in the present embodiment of the symbol X shown in Fig. 7 C is " undefined or determined ", is wherein denoted as the normally undefined or determined of the content of buffer of symbol X.
Please note, in the present embodiment, when the one in buffer Buf (1), Buf (2), Buf (3), Buf (4) and Buf (5) be just reversed be one at ping buffer device time, the buffer storing the content just removed from screen just becomes and is in one from screen state.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, be not less than the situation of four in the quantity of buffer 144 under, both these of multiple buffers 144 described in step 912 (such as: the upper part 144-1 in Fig. 7 A) can be in one in screen state in above-mentioned particular moment simultaneously, and this other buffer at least one in multiple buffers 144 described in step 914 can be in one from screen state in this particular moment.In addition, at the end in current cycle, the time point that a certain pulse of then arriving in such as vertical synchronizing signal VSYNC occurs, two buffers of the script that those are regarded as " both these of the multiple buffers 144 described in step 912 " enter one immediately from screen state simultaneously, wherein in buffer 144 some other both instead of two buffers originally and become simultaneously and be in one in screen state.
In addition, some drawing for order such as drawing for order DRAW (L (0)), DRAW (R (0)), DRAW (L (1)), DRAW (R (1)), DRAW (L (2)), DRAW (R (2)) ... Deng by for the example of instruction for being used for producing or obtain the up-to-date 3D picture in Fig. 7 C illustrated embodiment.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, the instruction of other kind can be used to produce or obtain up-to-date 3D picture.
Please refer to Fig. 7 D, workflow 930 is the implementation detail involved in the special case of the present embodiment of the method 910 shown in Fig. 4, and the source code of available virtual at least partially wherein in these implementation details illustrates, to understand the buffer control shown in Fig. 7 C.Especially, workflow 930 can be applicable to above-mentioned video processing circuits.Note that the workflow 930 (especially its step) shown in Fig. 7 D just for illustrative purposes, not limitation of the present invention.Workflow 930 is described as follows:
In 932 steps, controller 130 performs instruction i=0 and j=1, so that the initial value of index i and j is set as 0 and 1 respectively.
In 934-1 step, under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer module 140 (or the buffering switch unit 142 in it) selects buffer Buf (j mod K) for left 3D picture L (i), and wherein K is a positive integer, and in the present embodiment, K especially equals five.
In 934-2 step, above-mentioned video processing circuits (especially controller 130 and or decoder 120L) performs drawing for order Draw (L (i)), to draw left 3D picture L (i).Drawing for order Draw (L (i)) can be a program, and this program package is containing the multiple instructions for left 3D picture L (i), and therefore drawing for order Draw (L (i)) can comprise multiple sub-step.
In 934-3 step, controller 130 performs upset instruction Flip (j mod K), being one at ping buffer device by buffer Buf (j mod K) upset.Such as: under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer Buf (j mod K) upset is one at ping buffer device by buffer module 140 (or the buffering switch unit 142 in it), wherein multiplexer 150 is used to from estimating that one group of 3D picture (that is, a left 3D picture and a right 3D picture) that will show for user two is respectively selected or multiplex (MUX) selects a 3D picture.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, under the control of controller 130, especially at selection signal S
sELcontrol under, buffer Buf (j mod K) upset is one at ping buffer device by multiplexer 150.
In 934-4 step, controller 130 performs instruction j++, to increase the numerical values recited of index j.
In 936-1 step, under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer module 140 (or the buffering switch unit 142 in it) selects buffer Buf (j mod K) for right 3D picture R (i).
In 936-2 step, above-mentioned video processing circuits (especially controller 130 and or decoder 120R) performs drawing for order Draw (R (i)), to draw right 3D picture R (i).Drawing for order Draw (R (i)) can be a program, and this program package is containing the multiple instructions for right 3D picture R (i), and therefore drawing for order Draw (R (i)) can comprise multiple sub-step.
In 936-3 step, controller 130 performs upset instruction Flip (j mod K), being one at ping buffer device by buffer Buf (j mod K) upset.Such as: under the control of controller 130, especially at switch-over control signal S
sWcontrol under, buffer Buf (j mod K) upset is one at ping buffer device by buffer module 140 (or the buffering switch unit 142 in it), wherein multiplexer 150 is used to from estimating that one group of 3D picture (that is, a left 3D picture and a right 3D picture) that will show for user two is respectively selected or multiplex (MUX) selects a 3D picture.This is not limitation of the present invention just for illustrative purposes.According to a change case of the present embodiment, under the control of controller 130, especially at selection signal S
sELcontrol under, buffer Buf (j mod K) upset is one at ping buffer device by multiplexer 150.
In 936-4 step, controller 130 performs instruction j++, to increase the numerical values recited of index j.
In 938 steps, controller 130 checks whether needs the flow process 930 that quits work.The flow process 930 that quits work is needed, then power cut-off flow process 930 when detecting; Otherwise, enter step 939.
In 939 steps, controller 130 performs instruction i++, to increase the numerical values recited of index i.After execution step 939, reenter step 934-1.
Fig. 8 A to Fig. 8 C is the implementation detail involved in another embodiment of the method 910 shown in Fig. 4.According to the present embodiment, except the element shown in Figure 1A, above-mentioned video processing circuits separately comprises a display unit detector 170, and display unit detector 170 is used to detect the type (such as: a 3D type or non-3D (Non-3D) type) of the display unit being coupled to above-mentioned video display system, wherein in response to the change on framework, above-mentioned video display system is with label 100 in fig. 8 a " represent.Such as: video display system 100 " and be coupled to video display system 100 " display unit between connection 58F can be a high-resolution multimedia interface (High-Definition Multimedia Interface, HDMI) and connect.
According to the present embodiment, display unit detector 170 is used to detection and is coupled to video display system 100 " display unit whether be a 3D display unit.Please refer to Fig. 8 B, workflow 940 is the relevant running for type detection, and can be described as follows:
In 942 steps, under the control of controller 130, display unit detector 170 detects this display unit, especially detects and is coupled to video display system 100 " the type of display unit.
In 944 steps, based on the detection that display unit detector 170 carries out, controller 130 check be coupled to video display system 100 " display unit whether be a 3D display unit.When a 3D display unit (such as: be coupled to video display system 100 in the 3D display unit 58 shown in Figure 1B " situation under) being detected, enter step 946-1; Otherwise (such as: be coupled to video display system 100 at the non-3D display unit 58N shown in Fig. 8 A " situation under), enters step 946-2.
In 946-1 step, controller 130 adopts a 3D to show configuration, and the 3D such as implementation detail disclosed in any embodiment in the middle of Fig. 6 A to Fig. 6 D and Fig. 7 A to Fig. 7 D difference illustrated embodiment and some change case thereof or change case shows configuration.So buffer module 140 operates in the 3D pattern corresponding to this 3D display configuration.
In 946-2 step, controller 130 adopts a non-3D to show configuration, such as the general configuration of 2D display.So buffer module 140 operates in the non-3D pattern corresponding to this non-3D display configuration.
Note that workflow 940 can use repeatedly when needs.Based on workflow 940, video display system 100 " dynamically switch between this 3D pattern and this non-3D pattern.Such as: when connecting 58F and being established, video display system 100 " come dynamically to switch between this 3D pattern and this non-3D pattern by execution work flow process 940 one or many.Under type (such as: this 3D type or this non-3D type) the changeable situation of display unit again such as: be coupled to video display system 100 above-mentioned "; when the type changes, video display system 100 " come dynamically to switch between this 3D pattern and this non-3D pattern by execution work flow process 940 one or many.
Fig. 8 C is the implementation detail involved in the special case of the present embodiment of the method 910 shown in Fig. 4, first group of wherein above-mentioned buffer 1441L and 1441R by for the example for buffer 144 so that the difference between this 3D pattern and this non-3D pattern is described.Suppose in the middle of the buffer 144 in this special case, to only have first group of buffer 1441L and 1441R to use.In this 3D pattern, buffer 1441L and 1441R is used for temporarily storing a left 3D picture and a right 3D picture respectively.When controller 130 determines to switch to this non-3D pattern by this 3D pattern, one in buffer 1441L and 1441R can be used as one at ping buffer device in a particular moment, and the another one in buffer 1441L and 1441R can be used as one from ping buffer device in this particular moment.Under at associated hardware resource being the situation implemented with element that is cheap or low order, the quantity of buffer may be limited to heavens, therefore the quantity of buffer in the quantity of buffer in above-mentioned part 144-1 and above-mentioned part 144-2 can reduce in some cases.Such as: under the situation shown in Fig. 8 C, the quantity of the buffer in the left part 144-1 in Fig. 8 C Lower Half equals one, and the quantity of buffer in right part 144-2 in Fig. 8 C Lower Half equals one.
According to a change case of Fig. 8 C illustrated embodiment, based on some default settings (Default Setting) and or user setting (User Setting), above-mentioned video processing circuits (especially its controller 130) allows that user manually controls the switching between this 3D pattern and this non-3D pattern.
One of benefit of the present invention is, based on the framework in each embodiment disclosed above or change case, the target maintaining best overall usefulness can be reached easily.Especially, be that under the situation implemented with element that is cheap or low order, method of the present invention, relevant video processing circuits and relevant video display system still can maintain overall efficiency at associated hardware resource.Therefore, the problem of correlation technique all no longer there occurs.
The foregoing is only preferred embodiment of the present invention, all equalizations done according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (18)
1. carry out a method for video display and control, the method carries out video display and control in a video display system, and it is characterized in that, the method includes:
Both multiple at ping buffer device as multiple three-dimensional picture dynamically utilizing multiple buffer, wherein the plurality of buffer is arranged in this video display system, wherein, the plurality of both should be used for storing expectation respectively and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device; And
In utilize the plurality of buffer should any one in both as one during ping buffer device, dynamically utilize at least one from ping buffer device as at least one three-dimensional picture of other buffer at least one in the plurality of buffer, wherein, alternately should store from ping buffer device should both should be used for storing expectation and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device respectively.
2. the method for claim 1, is characterized in that, dynamically utilizes should both separately comprising in the step of ping buffer device as those of those three-dimensional pictures of the plurality of buffer:
Utilize respectively the plurality of buffer should both as within the different cycles at ping buffer device.
3. method as claimed in claim 2, is characterized in that, dynamically utilizes should both separately comprising in the step of ping buffer device as those of those three-dimensional pictures of the plurality of buffer:
By means of multiplexer one of in this video display system, utilize respectively the plurality of buffer should both as within the different cycles at ping buffer device, wherein this multiplexer is used to the output that multiplex (MUX) selects the one in those buffers.
4. method as claimed in claim 2, it is characterized in that, those different cycles are the different cycles for a vertical synchronizing signal.
5. the method for claim 1, is characterized in that, the quantity of the plurality of buffer is odd number.
6. the method for claim 1, is characterized in that, separately comprises:
Whether detecting is coupled to one of this video display system display unit is three-dimensional display apparatus.
7. a video processing circuits, this video processing circuits is arranged in a video display system, it is characterized in that, this video processing circuits includes:
One controller, is used for controlling the running of this video processing circuits;
One de-multiplexer, is used for a three-dimensional video stream solution multiplex (MUX) to become a left video stream and a right video flowing;
Two Video Decoders, be used for decoding respectively this left video stream and this right video flowing are to produce multiple three-dimensional picture; And
One buffer module, be used for temporarily storing those three-dimensional pictures, this buffer module comprises multiple buffer, wherein under the control of this controller, both multiple at ping buffer device as the three-dimensional picture at least partially in those three-dimensional pictures that this buffer module dynamically utilizes the plurality of buffer, wherein, the plurality of both should be used for storing expectation respectively and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device; And under the control of this controller, in utilize the plurality of buffer should any one in both as one during ping buffer device, this buffer module dynamically utilizes at least one from ping buffer device as at least one three-dimensional picture of other buffer at least one in the plurality of buffer; Wherein, alternately should store from ping buffer device should both should be used for storing expectation and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device respectively.
8. video processing circuits as claimed in claim 7, is characterized in that, this buffer module utilize respectively the plurality of buffer should both as within the different cycles at ping buffer device.
9. video processing circuits as claimed in claim 8, is characterized in that, separately comprise:
One multiplexer, being used for multiplex (MUX) selects the output of the one in those buffers;
Wherein by means of this multiplexer, this buffer module utilize respectively the plurality of buffer should both as within the different cycles at ping buffer device.
10. video processing circuits as claimed in claim 8, it is characterized in that, those different cycles are the different cycles for a vertical synchronizing signal.
11. video processing circuitss as claimed in claim 7, it is characterized in that, the quantity of the plurality of buffer is odd number.
12. video processing circuitss as claimed in claim 7, is characterized in that, separately comprise:
One display unit detector, whether being used for detecting, to be coupled to one of this video display system display unit be three-dimensional display apparatus.
13. 1 video display systems, is characterized in that, it includes:
One video processing circuits, this video processing circuits comprises:
One controller, is used for controlling the running of this video processing circuits;
One de-multiplexer, is used for a three-dimensional video stream solution multiplex (MUX) to become a left video stream and a right video flowing;
Two Video Decoders, be used for decoding respectively this left video stream and this right video flowing are to produce multiple three-dimensional picture; And
One buffer module, be used for temporarily storing those three-dimensional pictures, this buffer module comprises multiple buffer, wherein under the control of this controller, both multiple at ping buffer device as the three-dimensional picture at least partially in those three-dimensional pictures that this buffer module dynamically utilizes the plurality of buffer, wherein, the plurality of both should be used for storing expectation respectively and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device; And under the control of this controller, in utilize the plurality of buffer should any one in both as one during ping buffer device, this buffer module dynamically utilizes at least one from ping buffer device as at least one three-dimensional picture of other buffer at least one in the plurality of buffer; Wherein, alternately should store from ping buffer device should both should be used for storing expectation and one of will to show left three-dimensional picture for user's left eye and estimate one of to show right three-dimensional picture for user's right eye at ping buffer device respectively.
14. video display systems as claimed in claim 13, is characterized in that, this buffer module utilize respectively the plurality of buffer should both as within the different cycles at ping buffer device.
15. video display systems as claimed in claim 14, it is characterized in that, this video processing circuits separately comprises:
One multiplexer, being used for multiplex (MUX) selects the output of the one in those buffers;
Wherein by means of this multiplexer, this buffer module utilize respectively the plurality of buffer should both as within the different cycles at ping buffer device.
16. video display systems as claimed in claim 14, is characterized in that, those different cycles are different cycles of a vertical synchronizing signal.
17. video display systems as claimed in claim 13, it is characterized in that, the quantity of the plurality of buffer is odd number.
18. video display systems as claimed in claim 13, it is characterized in that, this video processing circuits separately comprises:
One display unit detector, whether being used for detecting, to be coupled to one of this video display system display unit be three-dimensional display apparatus.
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