CN104717113A - Synchronous multi-home peer-to-peer bus communication system - Google Patents
Synchronous multi-home peer-to-peer bus communication system Download PDFInfo
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- CN104717113A CN104717113A CN201310689745.9A CN201310689745A CN104717113A CN 104717113 A CN104717113 A CN 104717113A CN 201310689745 A CN201310689745 A CN 201310689745A CN 104717113 A CN104717113 A CN 104717113A
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- synchronizing signal
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Abstract
The invention provides a synchronous multi-home peer-to-peer bus communication system which comprises a synchronizing signal interface circuit, a synchronizing signal configuration module and a data sending control module. The synchronizing signal interface circuit adopts a difference level switch chip D2 with an enable pin, and synchronizing signals enter a D1 through the D2 and an optocoupler V2 in an input mode; in an output mode, the signals are output from the D1 and then output through an optocoupler V1A and the D2; input enable signals and output enable signals of the D2 are connected together and then connected to the D1 through an optocoupler V1B; the synchronizing signal configuration module is divided into a switch type input mode and a switch type output mode and connected with the chip D1; the data sending control module sends the data start time and time length information to the chip D1 through an interface of the chip D1. According to the synchronous multi-home peer-to-peer bus communication system, the problem that important data cannot be processed in time due to collision when the mass data are transmitted in a multi-home peer-to-peer bus system is solved.
Description
Technical field
The invention belongs to electronic circuit field, particularly relate to a kind of synchronous how main reciprocity bus communication system.
Background technology
How main reciprocity bus all has the feature of high speed and high reliability usually, any node on network all initiatively can send message, adopt non-destructive arbitration to avoid bus data conflict, there is the multiple transmission meanss such as point-to-point, point to multi--point and overall situation broadcast.
Based on above advantage, how main reciprocity bus communication system is widely used in onboard system, along with improving constantly of system complexity increases with the magnanimity of communication data, in how main reciprocity bus system, data collision frequency increases greatly, causes important information to be processed in time.
Summary of the invention
In order to solve technical problem existing in background technology, the present invention proposes a kind of synchronous how main reciprocity bus communication system, solving when mass data is transmitted in how main reciprocity bus system because conflict causes significant data cannot obtain the problem of process in time.
Technical solution of the present invention is: a kind of synchronous how main reciprocity bus communication system, is characterized in that: comprise synchronizing signal interface circuit, synchronizing signal configuration module and data and send control module; Synchronizing signal adopting differential signalling form, can be configured to by writing 1 or 0 to register in D1 chip FPGA the pattern of inputing or outputing.Synchronizing signal interface circuit adopts the differential level conversion chip D2 with Enable Pin, and during input pattern, synchronizing signal enters D1 by D2 and optocoupler V2; After during output mode, signal exports from D1, by exporting after optocoupler V1A and D2; Receive on D1 by optocoupler V1B after the input and output enable signal of D2 connects together; Synchronizing signal configuration module is divided into input pattern and the output mode of suitching type, is connected with D1 chip; Data send control module by sending the initial time of data with the interface of D1 chip and time span information issues D1 chip.
Above-mentioned synchronizing signal configuration module switches input pattern and output mode, be in D1 chip FPGA register write 1 or configuration synchronization signal for after inputing or outputing pattern, it be the level of enable pin 4 pin of 1 or 0 control synchronization signal interface circuit chips D2 is high or low that the pin IO_3 arranging D1 by logic exports, and realizes the selection of synchronizing signal I/O.
When synchronizing signal configuration module is input pattern, adopt the signal of D1 synchronizing signal input pin IO_2 as benchmark; When synchronizing signal configuration module is output mode, exports from the IO_1 pin of D1 after D1 frequency as requested, duty ratio produce satisfactory synchronizing signal, after V1A and D2 chip, be supplied to miscellaneous equipment in system.
Above-mentioned V1A is connected with current-limiting resistance R1, pull-up resistor R4; V2 is connected with pull-up resistor R2, current-limiting resistance R5; V1B connects current-limiting resistance R3, pull-up resistor R5;
Current-limiting resistance R1, R3 and R5 select the resistance of 180 Ω, 180 Ω and 470 Ω resistances; Pull-up resistor R2, R4 and R6 all select the resistance of 1k Ω resistance.
A kind of synchronous how main reciprocity bus communication, comprises the following steps:
1] transmitting time is distributed:
According to information such as the quantity of equipment in system, the size sending data and priority facilities, using the rising edge of synchronizing signal as initial time T0, distribute the time started T0+Ti and time span Li that send data to each equipment, wherein i is device number;
2] synchronizing signal configuration:
Synchronizing signal configuration module configures the synchronizing signal of this equipment for inputing or outputing pattern, realizes the selection of synchronizing signal I/O;
3] each equipment sends data to bus at (T0+Ti)-(T0+Ti+Li) in the time period:
3.1] each equipment is using the synchronizing signal self produced as reference amble signal, sends to respective data to send control module together with data;
3.2] data send control module timing from synchronizing signal arrives, and (T0+Ti) to (T0+Ti+Li) that only distribute in bus system sends data in the time period;
3.2] data are supplied to miscellaneous equipment in system after synchronizing signal interface and bus;
4] data are received:
Data are received at any time after the synchronizing signal interface and data transmission control module of receiving equipment.
Because bus collision causes significant data can not obtain the problem of process in time when the present invention's design can effectively avoid mass data to transmit on how main reciprocity bus communication system, be applied to CJSJ006 navigational computer circuit and CJSJ016 navigational computer circuit, respond well.
Accompanying drawing explanation
Fig. 1 is synchronizing signal interface circuit figure of the present invention;
Embodiment
See Fig. 1, this patent is for typical how main reciprocity bus CAN, propose a kind of method for designing of synchronous CAN, comprise synchronizing signal interface circuit design and software/logical design two parts, main thought is the information such as the quantity according to equipment in system, the size sending data and priority facility, using the rising edge of synchronizing signal as initial time T
0, the time started T sending data is distributed to each equipment
0+ T
i(i is device number) and time span L
i, ensure that each equipment is at (T by logic
0+ T
i)-(T
0+ T
i+ L
i) sending data to bus in the time period, equipment receiving data is by the restriction of time.
Synchronizing signal interface circuit design: synchronizing signal adopting differential signalling form, can be configured to by writing 1 or 0 to register in D1 chip FPGA the pattern of inputing or outputing.Synchronizing signal interface circuit adopts the differential level conversion chip D2 with Enable Pin, and during input pattern, synchronizing signal enters D1 by D2 and optocoupler V2; After during output mode, signal exports from D1, by exporting after optocoupler V1A and D2; Receive on D1 by optocoupler V1B after the input and output enable signal of D2 connects together, annexation between chip D1, D2, V1A, V1B and V2 as shown in Figure 1, the current limliting that wherein current-limiting resistance R1, R3 and R5 of V1A, V1B and V2 meet optocoupler requires, the design recommends the resistance selecting 180 Ω, 180 Ω and 470 Ω resistances; Pull-up resistor R2, R4 and R6 all recommend the resistance selecting 1k Ω resistance.
Software/logical design: software/logical design comprises synchronizing signal configuration and data send control.
1) synchronizing signal configuration
Synchronizing signal I/O pattern can be selected, in D1 chip FPGA register write 1 or configuration synchronization signal for after inputing or outputing pattern, it be the level of enable pin 4 pin of 1 or 0 control synchronization signal interface circuit chips D2 is high or low that the pin IO_3 arranging D1 by logic exports, and realizes the selection of synchronizing signal I/O.
When synchronizing signal is configured to input pattern, this equipment adopts the signal (see figure 1) of D1 synchronizing signal input pin IO_2 as benchmark; When synchronizing signal is configured to output mode, export from the IO_1 pin of D1 after the parameters such as D1 frequency as requested, duty ratio produce satisfactory synchronizing signal, after V1A and D2 chip, be supplied to miscellaneous equipment in system, this equipment is using the synchronizing signal self produced as benchmark.
2) data send and control
Software is by after issuing D1 with the interface of D1 by information such as the initial time of this equipment sending data and time spans, D1 is according to these information, timing from synchronizing signal arrives, only within the time period that bus system is distributed, send data, avoid in bus, produce conflict and cause significant data not processed in time.
A kind of synchronous how main reciprocity bus communication, comprises the following steps:
1] transmitting time is distributed:
According to information such as the quantity of equipment in system, the size sending data and priority facilities, using the rising edge of synchronizing signal as initial time T
0, the time started T sending data is distributed to each equipment
0+ T
iwith time span L
i, wherein i is device number;
2] synchronizing signal configuration:
Synchronizing signal configuration module configures the synchronizing signal of this equipment for inputing or outputing pattern, realizes the selection of synchronizing signal I/O;
3] each equipment is at (T
0+ T
i)-(T
0+ T
i+ L
i) send data to bus in the time period:
3.1] each equipment is using the synchronizing signal self produced as reference amble signal, sends to respective data to send control module together with data;
3.2] data send control module timing from synchronizing signal arrives, only at the (T that bus system is distributed
0+ T
i) to (T
0+ T
i+ L
i) time period interior transmission data;
3.2] data are supplied to miscellaneous equipment in system after synchronizing signal interface and bus;
4] data are received:
Data are received at any time after the synchronizing signal interface and data transmission control module of receiving equipment.
Claims (6)
1. a synchronous how main reciprocity bus communication system, is characterized in that: comprise synchronizing signal interface circuit, synchronizing signal configuration module and data and send control module; Synchronizing signal adopting differential signalling form, can be configured to by writing 1 or 0 to register in D1 chip FPGA the pattern of inputing or outputing; Synchronizing signal interface circuit adopts the differential level conversion chip D2 with Enable Pin, and during input pattern, synchronizing signal enters D1 by D2 and optocoupler V2; After during output mode, signal exports from D1, by exporting after optocoupler V1A and D2; Receive on D1 by optocoupler V1B after the input and output enable signal of D2 connects together; Synchronizing signal configuration module is divided into input pattern and the output mode of suitching type, is connected with D1 chip; Data send control module by sending the initial time of data with the interface of D1 chip and time span information issues D1 chip.
2. synchronous how main reciprocity bus communication system according to claim 1, it is characterized in that: described synchronizing signal configuration module switches input pattern and output mode, be in D1 chip FPGA register write 1 or configuration synchronization signal for after inputing or outputing pattern, it be the level of enable pin 4 pin of 1 or 0 control synchronization signal interface circuit chips D2 is high or low that the pin IO_3 arranging D1 by logic exports, and realizes the selection of synchronizing signal I/O.
3. synchronous how main reciprocity bus communication system according to claim 2, is characterized in that: when synchronizing signal configuration module is input pattern, adopts the signal of D1 synchronizing signal input pin IO_2 as benchmark; When synchronizing signal configuration module is output mode, exports from the IO_1 pin of D1 after D1 frequency as requested, duty ratio produce satisfactory synchronizing signal, after V1A and D2 chip, be supplied to miscellaneous equipment in system.
4. the synchronous how main reciprocity bus communication system according to Claims 2 or 3, is characterized in that: described V1A is connected with current-limiting resistance R1, pull-up resistor R4; V2 is connected with pull-up resistor R2, current-limiting resistance R5; V1B connects current-limiting resistance R3, pull-up resistor R5.
5. synchronous how main reciprocity bus communication system according to claim 4, is characterized in that: current-limiting resistance R1, R3 and R5 select the resistance of 180 Ω, 180 Ω and 470 Ω resistances; Pull-up resistor R2, R4 and R6 all select the resistance of 1k Ω resistance.
6. a synchronous how main reciprocity bus communication, is characterized in that: comprise the following steps:
1] transmitting time is distributed:
According to information such as the quantity of equipment in system, the size sending data and priority facilities, using the rising edge of synchronizing signal as initial time T
0, the time started T sending data is distributed to each equipment
0+ T
iwith time span L
i, wherein i is device number;
2] synchronizing signal configuration:
Synchronizing signal configuration module configures the synchronizing signal of this equipment for inputing or outputing pattern, realizes the selection of synchronizing signal I/O;
3] each equipment is at (T
0+ T
i)-(T
0+ T
i+ L
i) send data to bus in the time period:
3.1] each equipment is using the synchronizing signal self produced as reference amble signal, sends to respective data to send control module together with data;
3.2] data send control module timing from synchronizing signal arrives, only at the (T that bus system is distributed
0+ T
i) to (T
0+ T
i+ L
i) time period interior transmission data;
3.2] data are supplied to miscellaneous equipment in system after synchronizing signal interface and bus;
4] data are received:
Data are received at any time after the synchronizing signal interface and data transmission control module of receiving equipment.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689745.9A CN104717113B (en) | 2013-12-14 | 2013-12-14 | It is a kind of to synchronize how main reciprocity bus communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310689745.9A CN104717113B (en) | 2013-12-14 | 2013-12-14 | It is a kind of to synchronize how main reciprocity bus communication system |
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| Publication Number | Publication Date |
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| CN104717113A true CN104717113A (en) | 2015-06-17 |
| CN104717113B CN104717113B (en) | 2018-09-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106155014A (en) * | 2016-06-23 | 2016-11-23 | 北京东土科技股份有限公司 | A kind of industry internet field layer wideband bus real-time implementation method |
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| CN101056241A (en) * | 2006-06-13 | 2007-10-17 | 华为技术有限公司 | Bus communication system, data link establishment and data transmission method |
| CN101398796A (en) * | 2007-09-30 | 2009-04-01 | 北京国通创安信息技术有限公司 | Multipath serial communication controller and multipath control method thereof |
| CN101820372A (en) * | 2010-03-17 | 2010-09-01 | 浙江大学 | TDM (Time Division Multiplexing) single-bus communication system of power supply, data signals and audio analog signals |
| CN103155492A (en) * | 2010-08-09 | 2013-06-12 | 国立大学法人名古屋大学 | Communication system and communication apparatus |
| CN103218331A (en) * | 2012-12-07 | 2013-07-24 | 浙江大学 | Bus device and method by adopting synchronous mode switching and automatic adjustment of frame priority |
-
2013
- 2013-12-14 CN CN201310689745.9A patent/CN104717113B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101056241A (en) * | 2006-06-13 | 2007-10-17 | 华为技术有限公司 | Bus communication system, data link establishment and data transmission method |
| CN101398796A (en) * | 2007-09-30 | 2009-04-01 | 北京国通创安信息技术有限公司 | Multipath serial communication controller and multipath control method thereof |
| CN101820372A (en) * | 2010-03-17 | 2010-09-01 | 浙江大学 | TDM (Time Division Multiplexing) single-bus communication system of power supply, data signals and audio analog signals |
| CN103155492A (en) * | 2010-08-09 | 2013-06-12 | 国立大学法人名古屋大学 | Communication system and communication apparatus |
| CN103218331A (en) * | 2012-12-07 | 2013-07-24 | 浙江大学 | Bus device and method by adopting synchronous mode switching and automatic adjustment of frame priority |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106155014A (en) * | 2016-06-23 | 2016-11-23 | 北京东土科技股份有限公司 | A kind of industry internet field layer wideband bus real-time implementation method |
| CN106155014B (en) * | 2016-06-23 | 2019-07-23 | 北京东土科技股份有限公司 | Industry internet field layer wideband bus real-time implementation method |
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| CN104717113B (en) | 2018-09-21 |
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