CN104715795B - Row decoding circuit and memory - Google Patents
Row decoding circuit and memory Download PDFInfo
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- CN104715795B CN104715795B CN201410844130.3A CN201410844130A CN104715795B CN 104715795 B CN104715795 B CN 104715795B CN 201410844130 A CN201410844130 A CN 201410844130A CN 104715795 B CN104715795 B CN 104715795B
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Abstract
Present invention is disclosed a kind of row decoding circuit, including n+1 control gate decoding circuit and current limliting biasing circuit；The current limliting biasing circuit includes the first mirror image nmos pass transistor and resistance element, the source electrode of the first mirror image nmos pass transistor inputs an input voltage, the grid of the first mirror image nmos pass transistor and drain electrode connect, resistance element described in the drain series of the first mirror image nmos pass transistor, the grid of the first mirror image nmos pass transistor export an offset signal；Each control gate decoding circuit includes：First nmos pass transistor, the first PMOS transistor, the second nmos pass transistor, the second mirror image nmos pass transistor, the grid of the second mirror image nmos pass transistor receives the offset signal, and the source electrode of the second mirror image nmos pass transistor connects the drain electrode of first nmos pass transistor.Present invention further teaches a kind of memory for including described row decoding circuit.The row decoding circuit and memory can provide voltage conversioning rate controllable negative pressure for control gate.
Description
Technical field
The present invention relates to technical field of circuit design, more particularly to a kind of row decoding circuit and memory.
Background technology
As a kind of integrated circuit memory devices, flash memory has the function of electrically-erasable storage information, and therefore, flash memory is wide
It is general to be applied in such as portable computer, mobile phone, digital music player electronic product.Flash memory is needed memory cell to be adapted to
The array of operation itself is arranged, and each memory cell is all used for storing the data of single position.
Fig. 1 is the schematic diagram of memory cell in flash memory in the prior art, and Fig. 2 is memory cell in flash memory in the prior art
Array schematic diagram.The flash memory includes multiple memory cell being arranged in array, and for selecting the memory cell and carrying
For drive signal multiple bit lines (BL0, BL1, BL2, BL3 ..., BLm), wordline (WL) and control gate (such as CG0, CG1 etc.
Deng).As shown in figure 1, each memory cell includes two storage positions, the first storage position A and the second storage position B, and two are deposited
The shared wordline of storage space, each storage position include a bit line and a control gate.In fig. 2, two control gates are depicted：Control
Grid CG0 and control gate CG1, still, in the flash memory of reality, can also include more control gates (such as CG0, CG1, CG2,
CG3 ..., CGn etc.), this is the common knowledge of this area, and therefore not to repeat here.
In the prior art, negative pressure is provided to each control gate by row decoding circuit 1 as shown in Figure 3.Such as Fig. 3 institutes
Show, the row decoding circuit 1 includes the first logic decoding circuit 110, the first negative pressure level shifter 120 and n+1 control
Grid decoding circuit 130 (control gate decoding circuit 130/0, control gate decoding circuit 130/1 ..., control gate decoding circuit 130/
N), control gate decoding circuit 130/0, control gate decoding circuit 130/1 ..., control gate decoding circuit 130/n is respectively to control gate
CG0, CG1, CG3 ..., CGn provide negative pressure.
As shown in figure 4, existing control gate decoding circuit 130 includes the first nmos pass transistor N1, the first PMOS transistor
P1 and the second nmos pass transistor N2, the first nmos pass transistor N1 grid input one selection signal SEL, described first
PMOS transistor P1 grid inputs the inverted signal SELb of the selection signal SEL, the source electrode of the first PMOS transistor P1
Pass through the source electrode of first node a connections the first nmos pass transistor N1；The grid input of the second nmos pass transistor N2
The inverted signal, the source electrode of the second nmos pass transistor N2 pass through section point b connections the first PMOS transistor P1
Drain electrode, the grounded drain of the second nmos pass transistor N2.The first node a is used to connect the first negative pressure level shifter
120, the section point b are used to provide negative pressure to control gate.
When the first storage position A carries out erasing operation in the memory cell shown in Fig. 1, need to apply malleation on wordline WL
Need to apply negative pressure (such as -7V voltage) on (such as 8V voltage), bit line CG0 and bit line CG1.However, control gate CG1,
CG2 ..., CGn there is load, the load on control gate CG0 is smaller, the section point b of control gate decoding circuit 130/0 negative pressure
Voltage conversioning rate (slew rate, i.e. voltage drop to the speed of -7V negative pressure from 0V or malleation) it is whard to control, to storage
The reliability of unit brings influence.
The content of the invention
It is an object of the present invention to provide a kind of row decoding circuit and memory, and voltage can be provided for control gate and is turned
Change the negative pressure of controllable-rate.
In order to solve the above technical problems, the present invention provides a kind of row decoding circuit, for a memory the 0th, 1,
2nd ... or n rows control gate provides voltage, and the row decoding circuit includes n+1 control gate decoding circuit and current limliting biasing circuit, n
For the natural number more than 2；
The current limliting biasing circuit includes the first mirror image nmos pass transistor and resistance element, the first mirror image NMOS crystal
The source electrode of pipe inputs an input voltage, and the grid of the first mirror image nmos pass transistor and drain electrode connect, first mirror image
Resistance element described in the drain series of nmos pass transistor, the grid of the first mirror image nmos pass transistor export an offset signal；
Each control gate decoding circuit includes：
First nmos pass transistor, the grid of first nmos pass transistor input a selection signal；
First PMOS transistor, the grid of first PMOS transistor inputs the inverted signal of the selection signal, described
The source electrode of first PMOS transistor connects the source electrode of first nmos pass transistor by a first node；
Second nmos pass transistor, the grid of second nmos pass transistor input the inverted signal, and the 2nd NMOS is brilliant
The source electrode of body pipe connects the drain electrode of first PMOS transistor, the drain electrode of second nmos pass transistor by a section point
Ground connection；And
Second mirror image nmos pass transistor, the grid of the second mirror image nmos pass transistor receives the offset signal, described
The source electrode of second mirror image nmos pass transistor connects the drain electrode of first nmos pass transistor, the second mirror image nmos pass transistor
Drain electrode connects the section point；
Wherein, the section point be used for the 0th, 1,2 ... or control gate described in n rows provides voltage.
Further, the row decoding circuit also includes the first logic decoding circuit and the first negative pressure level shifter, institute
State one end that the first logic decoding circuit connects the first negative pressure level shifter, the first negative pressure level shifter it is another
One end connects the first node of each control gate decoding circuit respectively, and the first negative pressure level shifter input is described defeated
Enter voltage.
Further, the row decoding circuit includes first logic decoding circuit and the first negative pressure level
Shift unit, the first negative pressure level shifter connect the first node of the n+1 control gate decoding circuits respectively.
Further, the row decoding circuit also includes the second logic decoding circuit and the second negative pressure level shifter, institute
State one end that the second logic decoding circuit connects the second negative pressure level shifter, the second negative pressure level shifter it is defeated
Go out end and export the selection signal and inverted signal respectively, the second negative pressure level shifter inputs the input voltage.
Further, the row decoding circuit includes second logic decoding circuit and the second negative pressure level
Shift unit, the second negative pressure level shifter provides the selection to the n+1 control gate decoding circuits respectively to be believed
Number and inverted signal.
Further, the section point of n+1 control gate decoding circuits respectively to the 0th, 1,2 ... control described in n rows
Grid provide voltage.
Further, the row decoding circuit includes a current limliting biasing circuit, a current limliting biasing circuit
Respectively the offset signal is provided to the n+1 control gate decoding circuits.
Further, the resistance element includes a resistance and the 3rd nmos pass transistor, one end connection institute of the resistance
The drain electrode of the first mirror image nmos pass transistor is stated, the other end of the resistance connects the source electrode of the 3rd nmos pass transistor, described
The grid of 3rd nmos pass transistor inputs an enable signal, the grounded drain of the 3rd nmos pass transistor.
According to the another side of the present invention, the present invention also provides a kind of memory, includes the memory cell of array, in addition to such as
Row decoding circuit described in upper any one.
Further, the memory is flash memory.
Compared with prior art, row decoding circuit and memory provided by the invention have advantages below：
In row decoding circuit provided by the invention and memory, the current limliting biasing circuit includes the first mirror image NMOS
Transistor and resistance element, the source electrode of the first mirror image nmos pass transistor input an input voltage, the first mirror image NMOS
The grid of transistor and drain electrode connect, resistance element described in the drain series of the first mirror image nmos pass transistor, and described first
The grid of mirror image nmos pass transistor exports an offset signal, and the grid of the second mirror image nmos pass transistor receives the biasing letter
Number, the source electrode of the second mirror image nmos pass transistor connects the drain electrode of first nmos pass transistor, the second mirror image NMOS
The drain electrode of transistor connects the section point, and the first mirror image nmos pass transistor and the second mirror image nmos pass transistor form one
Individual current mirror, the electric current for flowing through the second mirror image nmos pass transistor and the electric current for flowing through the first mirror image nmos pass transistor are in
Ratio, flows through the controlled current flow of the first mirror image nmos pass transistor, so that flowing through the second mirror image nmos pass transistor
Controlled current flow.
Brief description of the drawings
Fig. 1 is the schematic diagram of memory cell in flash memory in the prior art；
Fig. 2 is the array schematic diagram of memory cell in flash memory in the prior art；
Fig. 3 is the schematic diagram of row decoding circuit in the prior art；
Fig. 4 is the schematic diagram of control gate decoding circuit in the prior art；
Fig. 5 is the schematic diagram of row decoding circuit in one embodiment of the invention；
Fig. 6 is the schematic diagram of control gate decoding circuit in one embodiment of the invention；
Fig. 7 is the schematic diagram of the second logic decoding circuit and the second negative pressure level shifter in one embodiment of the invention.
Embodiment
The row decoding circuit and memory of the present invention are described in more detail below in conjunction with schematic diagram, wherein table
Showing the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, description below is appreciated that for the widely known of those skilled in the art, and
It is not intended as limitation of the present invention.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
The core concept of the present invention is, there is provided a kind of row decoding circuit and memory, for the of a memory
0th, 1,2 ... or n rows control gate provides voltage, and the row decoding circuit includes n+1 control gate decoding circuit and current limliting biased electrical
Road, n are the natural number more than 2；The current limliting biasing circuit includes the first mirror image nmos pass transistor and resistance element, and described first
The source electrode of mirror image nmos pass transistor inputs an input voltage, and the grid of the first mirror image nmos pass transistor and drain electrode connect, institute
State resistance element described in the drain series of the first mirror image nmos pass transistor, the grid output one of the first mirror image nmos pass transistor
Offset signal；Each control gate decoding circuit includes：First nmos pass transistor, the grid of first nmos pass transistor are defeated
Enter a selection signal；First PMOS transistor, the grid of first PMOS transistor input the inverted signal of the selection signal,
The source electrode of first PMOS transistor connects the source electrode of first nmos pass transistor by a first node；2nd NMOS is brilliant
Body pipe, the grid of second nmos pass transistor input the inverted signal, and the source electrode of second nmos pass transistor passes through one the
Two nodes connect the drain electrode of first PMOS transistor, the grounded drain of second nmos pass transistor；And second mirror image
Nmos pass transistor, the grid of the second mirror image nmos pass transistor receive the offset signal, the second mirror image NMOS crystal
The source electrode of pipe connects the drain electrode of first nmos pass transistor, the drain electrode connection described second of the second mirror image nmos pass transistor
Node；Wherein, the section point be used for the 0th, 1,2 ... or control gate described in n rows provides voltage.
The first mirror image nmos pass transistor and the second mirror image nmos pass transistor form a current mirror, flow through described second
The electric current of mirror image nmos pass transistor and the electric current for flowing through the first mirror image nmos pass transistor are in ratio, flow through first mirror image
The controlled current flow of nmos pass transistor, so that flowing through the controlled current flow of the second mirror image nmos pass transistor.
Fig. 5-Fig. 7 is refer to below to illustrate the row decoding circuit of the present embodiment and memory, and Fig. 5 is the present invention
The schematic diagram of row decoding circuit in one embodiment；Fig. 6 is the schematic diagram of control gate decoding circuit in one embodiment of the invention；Fig. 7
For the second logic decoding circuit in one embodiment of the invention and the schematic diagram of the second negative pressure level shifter.In the present embodiment,
The control gate that the row decoding circuit is used for the memory cell of array into flash memory provides voltage.
As shown in figure 5, the row decoding circuit 2 include n+1 control gate decoding circuit (control gate decoding circuit 230/0,
Control gate decoding circuit 230/1 ..., control gate decoding circuit 230/n) and current limliting biasing circuit 240, wherein, the current limliting is inclined
Circuits 240 include the first mirror image nmos pass transistor M1 and resistance element 241, the source electrode of the first mirror image nmos pass transistor M1
Input an input voltage VNEG, the input voltage VNEG be used for control gate CG0, CG1, CG2 ..., CGn voltage, institute are provided
The grid and drain electrode for stating the first mirror image nmos pass transistor M1 connect, between the drain electrode of the first mirror image nmos pass transistor M1 and ground
Connect the resistance element, the grid of the first mirror image nmos pass transistor M1 exports an offset signal VNB.
Preferably, the resistance element 241 includes a resistance R and the 3rd nmos pass transistor N3, one end of the resistance R connects
The drain electrode of the first mirror image nmos pass transistor M1 is connect, the other end of the resistance R connects the 3rd nmos pass transistor N3's
Source electrode, the grid of the 3rd nmos pass transistor N3 input an enable signal EN, and the drain electrode of the 3rd nmos pass transistor M1 connects
Ground.
Preferably, the row decoding circuit 2 includes a current limliting biasing circuit 240, a current limliting biased electrical
Road 240 is respectively to n+1 control gate decoding circuit (control gate decoding circuit 230/0, the control gate decoding circuits 230/
1st ..., control gate decoding circuit 230/n) the offset signal VNB is provided, to save circuit structure.
The described control gate decoding circuits of n+1 (control gate decoding circuit 230/0, control gate decoding circuit 230/1 ..., control
Grid decoding circuit 230/n processed) be respectively used to control gate CG0, CG1, CG2 ..., CGn provide voltage.As shown in fig. 6, each institute
Stating control gate decoding circuit includes：First nmos pass transistor N1, the first PMOS transistor P1, the second nmos pass transistor N2 and second
Mirror image nmos pass transistor M2.
Wherein, the grid of the first nmos pass transistor N1 inputs a selection signal SEL.The first PMOS transistor P1
Grid input the inverted signal SELb of the selection signal SEL, the source electrode of the first PMOS transistor P1 passes through a first segment
Point a connections the first nmos pass transistor N1 source electrode., the grid input inverted signal of the second nmos pass transistor N2
SELb, the second nmos pass transistor N2 source electrode by the drain electrode of section point b connections the first PMOS transistor P1,
The grounded drain of the second nmos pass transistor N2.
The grid of the second mirror image nmos pass transistor M2 receives the offset signal VNB, and the second mirror image NMOS is brilliant
Body pipe M2 source electrode connects the drain electrode of the first nmos pass transistor N1, the drain electrode connection of the second mirror image nmos pass transistor M2
The section point b.Wherein, the section point b be used for the 0th, 1,2 ... or control gate CG0, CG1 described in n rows,
CG2 ..., CGn provide voltage.The section point b of n+1 control gate decoding circuits respectively to the 0th, 1,2 ... described in n rows
Control gate CG0, CG1, CG2 ..., CGn provide voltage.
As shown in figure 5, the row decoding circuit 2 also includes the first logic decoding circuit 210 and the first negative pressure level shift
Device 220, first logic decoding circuit 210 connect one end of the first negative pressure level shifter 220, first negative pressure
Level shifter 220 inputs the input voltage VNEG, and the other end of the first negative pressure level shifter 220 connects often respectively
The individual control gate decoding circuit (control gate decoding circuit 230/0, control gate decoding circuit 230/1 ..., control gate decoding electricity
Road 230/n) first node a.
Preferably, the row decoding circuit 2 includes first logic decoding circuit 210 and first negative pressure electricity
Translational shifting device 220, the first negative pressure level shifter 220 connect the n+1 control gate decoding circuit (controls respectively
Grid decoding circuit 230/0, control gate decoding circuit 230/1 ..., control gate decoding circuit 230/n) first node a, with save
Circuit structure.
The row decoding circuit 2 also includes the second logic decoding circuit 250 and the second negative pressure level shifter 260, described
Second logic decoding circuit 250 connects one end of the second negative pressure level shifter 260, the second negative pressure level shifter
260 output end exports the selection signal SEL and inverted signal SELb respectively, and the second negative pressure level shifter 260 inputs
The input voltage VNEG.The particular circuit configurations of the negative pressure level shifter 260 of second logic decoding circuit 250 and second
For it will be understood by those skilled in the art that, therefore not to repeat here.
Preferably, the row decoding circuit 2 includes second logic decoding circuit 250 and second negative pressure electricity
Translational shifting device 260, the second negative pressure level shifter 260 is respectively to the n+1 control gate decoding circuit (control gates
Decoding circuit 230/0, control gate decoding circuit 230/1 ..., control gate decoding circuit 230/n) the selection signal SEL is provided
With inverted signal SELb.
In the present embodiment, the first mirror image nmos pass transistor M1 and the second mirror image nmos pass transistor M2 forms an electricity
Mirror is flowed, flows through the electric current I of the second mirror image nmos pass transistor M22With the electric current for flowing through the first mirror image nmos pass transistor M1
I1In ratio.
Flow through the electric current I of the first mirror image nmos pass transistor M11=(VN- Vt)/r, wherein, VNFor input voltage VNEG
Magnitude of voltage, Vt be the first mirror image nmos pass transistor M1 threshold voltage, r be the resistance element 241 resistance value, institute
To flow through the electric current I of the first mirror image nmos pass transistor M11It is controllable.
When needing the section point b of the control gate decoding circuit 130/0 voltage being adjusted to negative pressure, the control gate
The section point b of decoding circuit 130/0 voltage transition time t=(C × VN)/ICG, C is the load on the control gate CG0,
ICGFor the electric current on the control gate CG0.
Flow through the electric current I of the second mirror image nmos pass transistor M22With the electric current I on the control gate CG0CGCorrelation, together
When, flow through the electric current I of the second mirror image nmos pass transistor M22With the electric current I for flowing through the first mirror image nmos pass transistor M11
In ratio, so, the electric current I on the control gate CG0CGWith the electric current I for flowing through the first mirror image nmos pass transistor M11Phase
Close.
Due to flowing through the electric current I of the first mirror image nmos pass transistor M11It is controllable, so, the electricity on the control gate CG0
Flow ICGIt is controllable so that section point b voltage transition time t=(C × VN)/ICG, section point b voltage transition time speed
It is controllable, so as to improve the reliability of memory cell.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (9)
1. a kind of row decoding circuit, for a memory the 0th, 1,2 ... or n rows control gate provides voltage, and its feature exists
In the row decoding circuit includes n+1 control gate decoding circuit and current limliting biasing circuit, and n is the natural number more than 2；
The current limliting biasing circuit includes the first mirror image nmos pass transistor and resistance element, the first mirror image nmos pass transistor
Source electrode inputs an input voltage, and the grid of the first mirror image nmos pass transistor and drain electrode connect, and the first mirror image NMOS is brilliant
Resistance element described in the drain series of body pipe, the grid of the first mirror image nmos pass transistor export an offset signal；
Each control gate decoding circuit includes：
First nmos pass transistor, the grid of first nmos pass transistor input a selection signal；
First PMOS transistor, the inverted signal of the grid input selection signal of first PMOS transistor, described first
The source electrode of PMOS transistor connects the source electrode of first nmos pass transistor by a first node；
Second nmos pass transistor, the grid of second nmos pass transistor input the inverted signal, second nmos pass transistor
Source electrode the drain electrode of first PMOS transistor is connected by a section point, the drain electrode of second nmos pass transistor connects
Ground；And
Second mirror image nmos pass transistor, the grid receiving offset signal of the second mirror image nmos pass transistor, described second
The source electrode of mirror image nmos pass transistor connects the drain electrode of first nmos pass transistor, the drain electrode of the second mirror image nmos pass transistor
Connect the section point；
Wherein, the section point be used for the 0th, 1,2 ... or control gate described in n rows provides voltage.
2. row decoding circuit as claimed in claim 1, it is characterised in that the row decoding circuit also includes the first logic and decoded
Circuit and the first negative pressure level shifter, first logic decoding circuit connect the one of the first negative pressure level shifter
End, the other end of the first negative pressure level shifter connect the first node of each control gate decoding circuit, institute respectively
State the first negative pressure level shifter and input the input voltage.
3. row decoding circuit as claimed in claim 2, it is characterised in that the row decoding circuit is patrolled including one described first
Decoding circuit and the first negative pressure level shifter are collected, the first negative pressure level shifter connects n+1 institute respectively
State the first node of control gate decoding circuit.
4. row decoding circuit as claimed in claim 1, it is characterised in that the row decoding circuit also includes the second logic and decoded
Circuit and the second negative pressure level shifter, second logic decoding circuit connect the one of the second negative pressure level shifter
End, the output end of the second negative pressure level shifter export the selection signal and inverted signal, the second negative pressure electricity respectively
Translational shifting device inputs the input voltage.
5. row decoding circuit as claimed in claim 4, it is characterised in that the row decoding circuit is patrolled including one described second
Decoding circuit and the second negative pressure level shifter are collected, the second negative pressure level shifter is described to n+1 respectively
Control gate decoding circuit provides the selection signal and inverted signal.
6. the row decoding circuit as any one of claim 1 to 5, it is characterised in that the row decoding circuit includes one
The individual current limliting biasing circuit, a current limliting biasing circuit is respectively to described in the n+1 control gate decoding circuits offers
Offset signal.
7. the row decoding circuit as any one of claim 1 to 5, it is characterised in that the resistance element includes an electricity
Resistance and the 3rd nmos pass transistor, one end of the resistance connect the drain electrode of the first mirror image nmos pass transistor, the resistance
The other end connects the source electrode of the 3rd nmos pass transistor, and the grid of the 3rd nmos pass transistor inputs an enable signal, institute
State the grounded drain of the 3rd nmos pass transistor.
8. a kind of memory, include the memory cell of array, it is characterised in that also including any one of claim 1 to 7
Row decoding circuit.
9. memory as claimed in claim 8, it is characterised in that the memory is flash memory.
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| CN201410844130.3A CN104715795B (en) | 2014-12-25 | 2014-12-25 | Row decoding circuit and memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410844130.3A CN104715795B (en) | 2014-12-25 | 2014-12-25 | Row decoding circuit and memory |
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| CN104715795A CN104715795A (en) | 2015-06-17 |
| CN104715795B true CN104715795B (en) | 2018-03-30 |
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| CN105655322B (en) * | 2016-03-31 | 2018-07-31 | 上海华虹宏力半导体制造有限公司 | Flash memory decoding circuit test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077742A (en) * | 2012-12-21 | 2013-05-01 | 上海宏力半导体制造有限公司 | Row decoding circuit and memory |
| CN103117085A (en) * | 2013-01-25 | 2013-05-22 | 上海宏力半导体制造有限公司 | Bias voltage generating circuit and memory of line decoder |
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| US8295087B2 (en) * | 2008-06-16 | 2012-10-23 | Aplus Flash Technology, Inc. | Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077742A (en) * | 2012-12-21 | 2013-05-01 | 上海宏力半导体制造有限公司 | Row decoding circuit and memory |
| CN103117085A (en) * | 2013-01-25 | 2013-05-22 | 上海宏力半导体制造有限公司 | Bias voltage generating circuit and memory of line decoder |
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