CN104715793B

CN104715793B - The circuit of power consumption is read for analog memory IP

Info

Publication number: CN104715793B
Application number: CN201310671222.1A
Authority: CN
Inventors: 冯国友; 姚翔
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2013-12-11
Filing date: 2013-12-11
Publication date: 2018-02-06
Anticipated expiration: 2033-12-11
Also published as: CN104715793A

Abstract

The invention discloses a kind of circuit that power consumption is read for analog memory IP, including：Correspond that the periodic current source of N number of starting point dislocation circulation, N number of hilted broadsword are double to put switch, N number of d type flip flop with reset function and N number of with rising edge delay function time delay module, the cyclic pulse signal of N number of starting point dislocation circulation, and N number of internal dc voltage source.Each hilted broadsword is double to put switch, and its first termination external power source, the corresponding internal dc voltage source of its second termination, it controls the Q ends for terminating corresponding d type flip flop, the corresponding current source of its public termination；Each d type flip flop, its CP termination external timing signals, its R end connect its Q end by its corresponding time delay module, and its D terminates corresponding pulse signal.The present invention is used for analog memory IP and reads power consumption, and it reads frequency and time point is controlled by external signal, and its power consumption waveform simulated can be used in any reading frequency, the design of Simulation of any read time point.

Description

The circuit of power consumption is read for analog memory IP

Technical field

The present invention relates to semiconductor integrated circuit field, and power digital circuit is read more particularly to a kind of analog memory IP.

Background technology

It is being related to third party NVM（Non Volatile Memory, nonvolatile memory）In IP product design, The emulation netlist of third party manufacturer offer or power consumption waveform is needed to be used to emulate.Generally, third party manufacturer is for letter The consideration of safety is ceased, is reluctant to provide emulation netlist, power consumption waveform is only provided；And the power consumption waveform that third party manufacturer provides is fixed Frequency is read, and time point is also fixed.Need to enter third party manufacturer offer power consumption waveform in product design simulation Row adaptive processes, reading it, frequency is consistent, and time point aligns.The power consumption waveform that third party manufacturer provides can not be directly using production Ability use after carrying out adaptive processes is needed to cause product design progress to be delayed in product design.

The content of the invention

The simulation controlled the technical problem to be solved in the present invention is to provide a kind of reading frequency and time point by external signal is deposited Reservoir IP reads power digital circuit.

In order to solve the above technical problems, the analog memory IP of the present invention reads power digital circuit, including：

N number of periodic current source, the periodic current source are starting point dislocation circulations, and waveform is identical, and its cycle is fixed For the most fast read cycle T of memory I P memory I P reading power consumption；

Wherein, the precision that N is triggered by cycle T and user to power consumption determines, it is assumed that error td, then N taken for T/td Integer；

N number of hilted broadsword is double to put switch, is corresponded with N number of current source, whether controls the power supply respectively as outside Power source loads；

N number of d type flip flop, corresponded with the double switches of putting of N number of hilted broadsword, there is reset function, a fixation arteries and veins can be exported Wide pulse signal, control its corresponding hilted broadsword is double to put switch, make its current loading of the corresponding current source as external power source；

N number of time delay module, corresponded with N number of d type flip flop, there is rising edge delay function, it is delayed to be above-mentioned Cycle T；

External power source, the cycle of its current loading and start time point are all controlled by external read clock signal, and simulation is actual Reading power consumption；

Each hilted broadsword is double to put switch, its first termination external power source, the corresponding internal dc voltage of its second termination Source, it controls the Q ends for terminating corresponding d type flip flop, the corresponding current source of its public termination；

Each d type flip flop, its CP termination external timing signals, its R end meets its Q end, its D by its corresponding time delay module Terminate corresponding pulse signal.

The present invention is when each external timing signal Aclk rising edges come, when at external power source vpwr ends, one section of generation continues Between be T power consumption.Thus actual reading power consumption can be simulated, the power consumption frequency is by external timing signal Aclk in product simulation Frequency determines, and produces the time point of power consumption and the time error of external timing signal Aclk rising edges and be less than T/N.

The analog memory IP of the present invention reads its reading frequency of power digital circuit and time point is controlled by external signal, what it was simulated Power consumption waveform can be used in any reading frequency, the design of Simulation of any read time point.

Brief description of the drawings

The present invention is further detailed explanation with embodiment below in conjunction with the accompanying drawings：

Fig. 1 is the structural representation of the embodiment of the present invention.

Fig. 2 is the implementation sequential and power consumption waveform diagram of the embodiment of the present invention.

Embodiment

As shown in figure 1, one embodiment of the invention, including：

Current source Idd1, Idd2, Idd3 ... IddN, be starting point dislocation circulation, waveform is identical, and the cycle fixes (memory The most fast read cycle T of IP) storage stack IP reading power consumption, wherein, the precision that N is triggered by cycle T and user to power consumption Determine, it is assumed that error td, then N is T/td round numbers；

Hilted broadsword is double put switch S1, S2 ... SN, with the current source Idd1, Idd2, Idd3 ... IddN is corresponded, respectively Control whether the current source is used as external power load；

D type flip flop D1, D2 ... DN, with hilted broadsword it is double put switch S1, S2 ... SN is corresponded, and has a reset function, and energy is defeated Go out the pulse signal of a fixed pulse width, control its corresponding hilted broadsword is double to put switch, make its corresponding current source as external power source Current loading；

Time delay module del1, del2 ... delN, with trigger D1, D2 ... DN correspond, have rising edge delay work( Can, it is cycle T that it, which is delayed, and T is the most fast read cycle of the IP；

External power source wpwr, the cycle of its current loading and start time point are all controlled by external read clock signal Aclk, Simulate actual reading power consumption；

Each hilted broadsword is double to put switch, and its first end a connects external power source, and its second end b connects corresponding internal direct current electricity Potential source, its control terminal g connect the Q ends of corresponding d type flip flop, the corresponding current source of its public termination；

Each d type flip flop, its CP termination external timing signals, its R end meets its D of its Q end by its corresponding time delay module Terminate corresponding pulse signal.

Emulation obtains NVM IP reading power consumption waveform first, and its cycle T is the most fast read cycle of the IP.And use piecewise linearity Power consumption waveform, power consumption waveform as shown in Figure 2 are read in current source Idd1 simulations.A then, it is determined that parameter N（N is by cycle T and makes The precision that user triggers to power consumption（Assuming that error time is no more than td）Determine, then N is T/td round numbers）, Idd1 is prolonged respectively When T*1/N, T*2/N ..., T* (N-1)/N obtains current source Idd2, Idd3 ..., IddN；Obtaining high pulse width simultaneously is T/N, cycle are T pulse voltage source Vp1, Vp2 ... VpN, and its trailing edge aligns with the trigger point of power consumption waveform.Wherein, V1, V2 ... VN is direct voltage source；

Current source Idd1, Idd2 of analog power consumption waveform, Idd3 ... IddN respectively order knife it is double put switch S1, S2 ... SN Common port c, when the control terminal g of switch is low level, current source by inside circuit dc source provide electric current, work as switch Control terminal g when being high level, current source is connected on external power source vpwr, the current power dissipation as external power source vpwr.

Concrete operations mode：

When external signal Aclk rising edges arrive, the pulse voltage source that one of output is just high level can be triggered The d type flip flop connected, by the output signal of the d type flip flop（G1, G2 ... one in GN）Put height.So the signal controls The double common port c for putting switch of hilted broadsword meet first end a, the current source that so the double common port c for putting switch of the hilted broadsword connect is connected to outside On portion power supply vpwr, current power dissipation is produced on external power source vpwr.Its corresponding rising edge time delay module del is in the D simultaneously The output signal of trigger is delayed after T time after uprising, and produces a high level, the d type flip flop is resetted, puts its output It is low.So as to put switch by the way that hilted broadsword is double, current source is connect into internal source voltage, external power source vpwr becomes to open a way, without power consumption.Together When rising edge time delay module del output also become low.The circuit returns to original state.When next Aclk rising edges arrive When, equally, the power consumption that one section of duration is T can be produced on external power source vpwr.

Realize in summary：When each Aclk rising edges arrive, all one section of power consumption can be produced at external power source vpwr ends, Effectively simulate actual reading power consumption.

The present invention is described in detail above by embodiment and embodiment, but these are not composition pair The limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change Enter, these also should be regarded as protection scope of the present invention.

Claims

1. a kind of circuit that power consumption is read for analog memory IP, it is characterized in that, including：

N number of periodic current source, N number of periodic current source are starting point dislocation circulations, and waveform is identical, and its cycle is fixed as The most fast read cycle T of memory I P；

Wherein, N is T/td round numbers, and td is time mistake of the time point with external timing signal Aclk rising edges for producing power consumption Difference；

N number of hilted broadsword is double to put switch, is corresponded with N number of periodic current source, controls N number of seasonal power to be respectively It is no to be used as external power load；

N number of d type flip flop, corresponded with the double switches of putting of N number of hilted broadsword, there is reset function, a fixed pulse width can be exported Pulse signal, control its corresponding hilted broadsword is double to put switch, make hilted broadsword is double to put electricity of the current source as external power source corresponding to switch Current load；

N number of time delay module, corresponded with N number of d type flip flop, there is rising edge delay function, its delay is the above-mentioned cycle T；

External power source, the cycle of its current loading and start time point are all controlled by external read clock signal, simulate actual reading Power consumption；

Each hilted broadsword is double to put switch, its first termination external power source, the corresponding internal dc voltage source of its second termination, its Control terminates the Q ends of corresponding d type flip flop, the corresponding current source of its public termination；

Each d type flip flop, its CP termination external timing signals, its R end connect its Q end, its D terminations by its corresponding time delay module Corresponding pulse signal.