CN104699633B - Virtual physical address converting system and its management method - Google Patents

Virtual physical address converting system and its management method Download PDF

Info

Publication number
CN104699633B
CN104699633B CN201310648140.5A CN201310648140A CN104699633B CN 104699633 B CN104699633 B CN 104699633B CN 201310648140 A CN201310648140 A CN 201310648140A CN 104699633 B CN104699633 B CN 104699633B
Authority
CN
China
Prior art keywords
conversion
entrance
virtual
physical address
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310648140.5A
Other languages
Chinese (zh)
Other versions
CN104699633A (en
Inventor
卢彦儒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Realtek Semiconductor Corp
Original Assignee
Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to CN201310648140.5A priority Critical patent/CN104699633B/en
Publication of CN104699633A publication Critical patent/CN104699633A/en
Application granted granted Critical
Publication of CN104699633B publication Critical patent/CN104699633B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention discloses virtual physical address converting system and its management methods.The management method of virtual physical address converting system includes: providing one first memory space, wherein first memory space includes multiple buffering entrances；One second memory space is provided, wherein second memory space includes that multiple conversion entrances and multiple conversion entrance correspond to multiple conversion indexes；And when receiving a write instruction with by a specific buffering entrance of the multiple buffering entrance of one first virtual physical address conversion write-in, first virtual physical address conversion is stored in the write-in conversion entrance among multiple conversion entrance by the position of one first part of one first virtual address corresponding according to first virtual physical address conversion, and a write-in conversion index corresponding to first virtual address and write-in conversion entrance is stored in the specific buffering entrance.

Description

Virtual physical address converting system and its management method
Technical field
The present invention relates to memory managements, and in particular, to a kind of position of a part with a virtual address is as index Virtual physical address converting system management method and its relevant virtual physical address converting system.
Background technique
Memory management unit (memory management unit) is by translation lookaside buffer (translation Lookaside buffer, TLB) Lai Tisheng page table (page table) access efficiency.For example, no interlock lines rank Used by the microprocessor (microcomputer without interlocked pipeline stages, MIPS) of section Translation lookaside buffer can have multiple (for example, 64) entrances (entry) to carry out high speed access, wherein each entrance can be deposited The virtual physical address for storing up a virtual address (virtual address) and a physical address (physical address) turns Change (virtual-to-physical address translation).
However, when being consulted among above-mentioned translation lookaside buffer, need to be intended to the virtual address consulted and every The virtual address that one entrance is stored is mapped (that is, full relationship type mapping (fully-associative mapping)), That is, multiple (for example, 64) comparison circuits are needed, therefore, if increasing the entrance number of translation lookaside buffer to mention System effectiveness is risen, the circuit area of translation lookaside buffer can also increase therewith, and processing speed can also decline, however, if will turn The entrance number for changing look-aside buffer reduces, then can reduce system effectiveness (for example, translation lookaside buffer loses (TLB miss) Probability increase).
Therefore, it is necessary to it is a kind of can lifting system efficiency without sacrifice circuit area and processing speed virtual physical address Converting system.
Summary of the invention
In view of this, one of the objects of the present invention is to provide a kind of positions of a part with a virtual address as rope The virtual physical address converting system management method and its relevant virtual physical address converting system drawn, to solve above-mentioned ask Topic.
An embodiment according to the present invention discloses a kind of management method of virtual physical address converting system.The management Method, which comprises the steps of, provides one first memory space, and wherein first memory space includes multiple buffering entrances；There is provided one Second memory space, wherein second memory space corresponds to more comprising multiple conversion entrances and multiple conversion entrance A conversion index；And multiple buffering entrance is written to convert one first virtual physical address when receiving a write instruction When one specific buffering entrance, a first part of one first virtual address corresponding according to first virtual physical address conversion Position by first virtual physical address conversion be stored in it is multiple conversion entrance among one write-in conversion entrance, and will A write-in conversion index corresponding to first virtual address and write-in conversion entrance is stored in the specific buffering entrance.
Another embodiment according to the present invention separately discloses a kind of management method of virtual physical address converting system.It should Management method, which comprises the steps of, provides a memory space, and wherein the memory space includes multiple conversion entrances, multiple conversion Entrance is to store the conversion of an at least virtual physical address, and correspond respectively to multiple conversion indexes；And refer to when receiving one and reading When enabling to read a physical address corresponding to a virtual address, a part of position according to the virtual address is with empty from the storage Between read the physical address.
An embodiment according to the present invention discloses a kind of virtual physical address converting system.The virtual physical address turns Changing system includes one first memory space, one second memory space and a processing circuit.First memory space includes multiple Buffer entrance.Second memory space includes multiple conversion entrances, wherein multiple conversion entrance is to correspond respectively to multiple turns Change index.The processing circuit is coupled to first memory space and second memory space.When the system receives a write-in When instruction is with the specific buffering entrance buffered among entrance that the conversion write-in of one first virtual physical address is multiple, the processing Circuit is that the position of a first part of one first virtual address corresponding according to first virtual physical address conversion should The conversion of first virtual physical address is stored in the write-in conversion entrance among multiple conversion entrance, and this is first virtual A write-in conversion index corresponding to address and write-in conversion entrance is stored in the specific buffering entrance.
Another embodiment according to the present invention separately discloses a kind of virtual physical address converting system.The physical vlan Location converting system includes a memory space and a processing circuit.The memory space includes multiple conversion entrances, wherein multiple Conversion entrance is to store the conversion of an at least virtual physical address, and correspond respectively to multiple conversion indexes.The processing circuit is coupling It is connected to the memory space, wherein when the system receives a sense order to read a physical address corresponding to a virtual address When, which is a part of position according to the virtual address to read the physical address from the memory space.
Virtual physical address converting system and its management method provided by the present invention can store a large amount of change data, and Relevant virtual physical address can be converted and merge or be stored in adjacent entrance, therefore, physical vlan provided by the present invention Address conversion system and its management method can lifting system efficiency without will increase dramatically circuit area, processing speed will not be reduced Degree.In addition, virtual physical address converting system provided by the present invention and its management method are compatible in no interlock lines stage Microprocessor instruction.
Detailed description of the invention
Fig. 1 is the schematic diagram of an embodiment of virtual physical address converting system of the present invention.
Fig. 2 is the schematic diagram of another embodiment of virtual physical address converting system of the present invention.
Fig. 3 is the schematic diagram of an implementation example of the first memory space shown in FIG. 1 and the second memory space.
Fig. 4 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Fig. 5 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Fig. 6 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Fig. 7 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Fig. 8 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Fig. 9 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Figure 10 is the flow chart of an embodiment of the management method of virtual physical address converting system of the present invention.
Figure 11 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Figure 12 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Figure 13 is that the first memory space shown in Fig. 3 and the second memory space carry out virtual physical address conversion operation One implements the schematic diagram of example.
Figure 14 is the flow chart of an embodiment of the management method of virtual physical address converting system of the present invention.
Symbol description
100,200 virtual physical address converting system
110,210,310 first memory space
120,220,320 second memory space
130,230 processing circuit
224 virtual address tables
226 physical address tables
234 comparators
236 selectors
1000、1002、1004、1006、1007、1008、1010、1400、1402、1404、1406、1407、1408、 1409,1410,1412,1414 step
C_W write instruction
C_R sense order
The conversion of V2P, V2Px virtual physical address
B1, B2, Bi, Bm buffer entrance
T1, T2, Tx, Tn convert entrance
I1, I2, Ix, In, idx(0), idx(1), idx(2), idx(3) conversion index
I virtual index
VA, VAx1~VAx8 virtual address
PA, PAx1~PAx8 physical address
The road W1, W2
V, the effective bit field of v1, v2
Idx converts index field
Vaddr, vaddr1, vaddr2 virtual address field
Paddr, paddr1, paddr2 physical address field
Pastart1, pastart2 paging start field
Mp1, mp2 multipage field
Num_e loses a digital section
The search range ran_s field
IND(0), IND(1), IND(2), IND(3), IND(4), IND(5), IND(6), IND(7) buffer index
Specific embodiment
In order to which lifting system efficiency is without will increase dramatically circuit area, the present invention is by a part of position of a virtual address As an index, to consult the corresponding physical address of the virtual address according to the index, and deposited by the way that capacity is biggish Reservoir provides more translation lookaside buffer entrance, and then system effectiveness is substantially improved and can reduce system is being consulted The comparison circuit of Shi Suoxu.
Referring to Fig. 1, it is for the schematic diagram of an embodiment of virtual physical address converting system of the present invention.It can by Fig. 1 Know, virtual physical address converting system 100 includes one first memory space 110, one second memory space 120 and a processing electricity Road 130, wherein the first memory space 110 includes that the storage of multiple buffering entrance (buffer entry) B1~Bm and second is empty Between 120 include multiple conversion entrance (translation entry) T1~Tn.In this embodiment (but the present invention does not limit to In this), static random access memory (Static can be used in the first memory space 110 and the second memory space 120 Random access memory, SRAM) implement to provide more buffering entrance number and conversion entrance number.Separately Outside, multiple conversion entrance T1~Tn can correspond respectively to multiple conversion index (translation index) I1~In.
Processing circuit 130 is coupled to the first memory space 110 and the second memory space 120.When virtual physical address turns It changes system 100 and receives its instruction of a write instruction C_W(for the multiple buffering entrance B1 of virtual physical address conversion V2P write-in A specific buffering entrance Bi among~Bm) when, processing circuit 130 can be converted one corresponding to V2P according to virtual physical address The a part of position of virtual address VA is by virtual physical address conversion V2P(for example, virtual address VA and its a corresponding object Reason address PA) be written/be stored in it is multiple conversion entrance T1~Tn among one write-in conversion entrance Tx, and by virtual address VA with A write-in conversion index Ix corresponding to write-in conversion entrance Tx is written/is stored in specific buffering entrance Bi.For example, it handles Circuit 130 can be using the position of the part of a virtual address VA as a virtual index I, and is indexed to phase according to virtual index I Corresponding conversion index (for example, write-in conversion index Ix), and then virtual physical address conversion V2P is written/is stored to write-in Conversion entrance Tx(assumes that write-in conversion entrance Tx can use (available)).First memory space 110 is then by will virtually Location VA and write-in conversion index Ix are written/are stored in specific buffering entrance Bi, are to deposit to represent virtual physical address conversion V2P It is stored in the write-in conversion entrance Tx of the second memory space 120.In this way, when virtual physical address converting system 100 receives Physical address PA corresponding to its instruction of one sense order C_R(reading/access virtual address VA) when, processing circuit 130 According to virtual address VA the part position (that is, virtual index I) with from the second memory space 120 read physical address PA, Without virtual address VA is mapped with virtual address all among the first memory space 110 is stored in.
First memory space 110 can be considered that a translation lookaside buffer enters oral thermometer (TLB entry table), can be used Traditional translation lookaside buffer instructs to control, in addition, the second memory space 120 can be considered a virtual physical address conversion table (virtual-to-physical address translation table), plurality of conversion entrance T1~Tn is at least One may include that multiple holding tanks (slot) and multiple holding tank can be respectively to store multiple virtual physical address conversions To increase the transfer efficiency of lifting system.Referring to Fig. 2, it is for another implementation of virtual physical address converting system of the present invention The schematic diagram of example.The structure of virtual physical address converting system 200 is based on virtual physical address converting system shown in FIG. 1 100 structure, therefore, virtual physical address converting system 200 may include one first memory space 210, one second memory space 220 and a processing circuit 230, wherein the first memory space 210, the second memory space 220 and processing circuit 230 can be distinguished For being embodied as the first memory space 110, the second memory space 120 and processing circuit 130 shown in FIG. 1.In this embodiment In (but the present invention is not limited thereto), the first memory space 210 may include 1024 buffering entrances and the second memory space 220 may include 128 conversion entrances.Second memory space 220 may include a virtual address table 224 and a physical address table 226, to store multiple virtual addresses and multiple physical address respectively, in addition, multichannel can be used in the second memory space 220 (multi-way) mode accessed is come what is implemented, and therefore, each conversion entrance may include that multiple holding tanks are multiple virtual to store Physical address translations (for example, multiple virtual addresses and multiple physical address).
Processing circuit 230 includes a comparator 234 and a selector 236.When virtual physical address converting system 200 is intended to It, can be using a part of position of virtual address VA as a virtual rope when consulting the corresponding physical address PA of a virtual address VA Draw I, and is indexed to a conversion entrance Tx accordingly.Comparator can deposit virtual address VA with conversion the multiple of entrance Tx is stored in Multiple virtual address VAx1~VAx8 among storage tank (for example, 8 holding tanks) make comparisons, and selector 236 is further according to comparator 234 output corresponds respectively to multiple virtual address VAx1~VAx8 from multiple physical address PAx1~PAx8() among obtain Physical address (that is, physical address PA corresponding to virtual address VA) appropriate.As shown in Figure 2, processing circuit 230 can be used Single comparison circuit 234 completes lookup operations, therefore the service speed of virtual physical address converting system 200 can be substantially improved, Also required circuit area is reduced.
In order to have further understanding to technical characteristic of the invention, with please referring to Fig. 3~physical vlan shown in Fig. 9 The implementation example of the management operation of location converting system.Fig. 3 is for the first memory space 110 shown in FIG. 1 and the second memory space The one of 120 implements the schematic diagram of example.Implement in example herein, the first memory space 310 includes multiple buffering entrances, wherein should Multiple buffering entrances correspond respectively to multiple buffer index IND(0 with index value 0~7)~IND(7).Each buffering entrance Include effective bit field (valid bit field) v, conversion index field (translation index field) idx And virtual address field (virtual address field) vaddr.Effective bit field v's of each buffering entrance is first Initial value can be set as 0, and representative does not have data deposit.Conversion index field idx can be used to store a conversion and index, and virtual address word Section vaddr then can be used to store a virtual address.It note that succinct for purposes of explanation, do not show that address space identifier (ASID) herein Field (address-space identifier field, ASID field), change bit field (dirty bit field) with And global bit field (global bit field) in the first memory space 310(for example, translation lookaside buffer enters oral thermometer) it In, in addition, those skilled in the art should be appreciated that address space identifier (ASID) field, change bit field and global bit field institute The meaning of representative, therefore relevant explanation just repeats no more herein.
Second memory space 320(is for example, virtual physical address conversion table) it may include multiple conversion entrances, wherein multiple Conversion entrance corresponds respectively to multiple conversions index idx(0 with index value 0~3)~idx(3).In addition, the second storage is empty Between 320 using multichannel (multi-way) access by the way of (that is, multiple roads (way) W1 and W2), Road W1 include one effectively Bit field v1, a virtual address field vaddr1, a physical address field (physical address field) paddr1, one Physical paging start field (physical page start field) pa_start1 and multipage field (multi-page Field) mp1.The initial value of effective bit field v1 can be set as 0, and can represent does not have data deposit.Virtual address field vaddr1 A virtual address can be stored, physical address field paddr1 can store the corresponding physical address of the virtual address, Physical Page Start field pa_start1 can then store an initial address of the affiliated Physical Page of the physical address, and multipage field mp1 can be indicated Number of pages of at least physical address among affiliated Physical Page stored among corresponding holding tank (slot) out.About more The further instruction Rong Houzai of page field mp1/mp2 is chatted.Similarly, road W2 includes an effective bit field v2, a virtual address Field vaddr2, a physical address field paddr2, a physical paging start field pa_start2 and a multipage field mp2. In other words, each conversion entrance includes two holding tanks to store multiple virtual physical address conversions.
In addition, each conversion entrance may include a shift state field (offset status field), can indicate The virtual physical address conversion number to another conversion entrance is stored (that is, losing because a current conversion entrance is unavailable out Lose digital section (escape number field) num_e), and can indicate that another conversion entrance apart from the current conversion The conversion entrance number (that is, search range field (search range field) ran_s) of entrance.About the shift state The further instruction Rong Houzai of field is chatted.
Note that it is above only for explanation need, be not used as limitation of the invention.For example, the first storage is empty Between the numbers of the 310 buffering entrances for being included be not limited to 8 and conversion entrance that the second memory space 320 is included Number is not limited to 4, in addition, the second memory space 320 can also use the access side on more multichannel (that is, more than three tunnels) Formula.
Please come together with Fig. 3 refering to Fig. 4.Fig. 4 is for the first memory space 310 and the second memory space 320 shown in Fig. 3 Carry out the one of the virtual physical address conversion operation schematic diagram for implementing example.Implement in example herein, the first memory space 310 with A virtual physical address converting system (being not shown in Fig. 4) corresponding to second memory space 320 is to receive a write instruction (for example, instruction TLBWI/TLBWR of the microprocessor without the interlock lines stage) is indicated a virtual address 0x0000_ Virtual physical address conversion between 8000 and corresponding physical address 0x9000_0000, is written/is stored in a conversion Look-aside buffer enters the buffering entrance among oral thermometer (that is, first memory space 310) corresponding to buffer index IND(3).It please infuse Meaning, virtual address 0x0000_8000/ physical address 0x9000_0000 is with 16 carries (that is, " 0x ") come what is indicated.
Implement in example herein, is that (but the present invention is simultaneously as a paging (page) with 4 kilobytes (4kilobytes, 4KB) It is without being limited thereto), therefore, the 1st~12 position of virtual address (for example, virtual address 0x0000_8000) is (from least significant bit (LSB) (least significant bit, LSB) is counted) [11:0] correspond to a paging range and physical address (for example, Physical address 0x9000_0000) the 1st~12 position (being counted from least significant bit (LSB)) [11:0] correspond to the model of a paging It encloses.13rd, 14 position [13:12] of virtual address can be used to indicate annexable paging number of pages, for example (but the present invention is not Be limited to this), due to the digit of the 13rd of virtual address the, 14 position [13:12] can be formed 4 kinds of position patterns (bit pattern) " 00 ", " 01 ", " 10 " and " 11 ", therefore four continuous physical pagings can be merged into a merging page.More specifically, if it is multiple Virtual address 0x0000_8000,0x0000_9000,0x0000_a000 and 0x0000_b000 correspond respectively to it is multiple physically Location 0x9000_0000,0x9000_1000,0x9000_2000 and 0x9000_3000, then can be (right by four continuous physical pagings It should be in multiple physical address 0x9000_0000,0x9000_1000,0x9000_2000 and 0x9000_3000；Corresponding position The position pattern of [13:12] is respectively " 00 ", " 01 ", " 10 " and " 11 ") merge into one and merge page, and can by it is multiple physically Location 0x9000_0000,0x9000_1000,0x9000_2000 are respectively seen as merging the 1st~4 among page with 0x9000_3000 Paging.
15th, 16 position [15:14] of virtual address can be used to indicate to be indexed to virtual physical address conversion table (that is, Second memory space 320) virtual index, for example (however, the present invention is not limited thereto), virtual address 0x0000_8000(its Position [15:14] position pattern be " 10 ") can be indexed to correspond to conversion index idx(2) conversion entrance in other words can foundation The a part of position (for example, the 15th of virtual address 0x0000_8000 the, 16 position [15:14]) of virtual address come be indexed to The position pattern of the part position is corresponding, which to convert entrance, (for example, value corresponding to position pattern " 10 " is 2, therefore can be indexed to conversion Index idx(2)).In addition, the 17th~32 position [31:16] of virtual address then can be used to identify the content of the virtual address.
Significantly, since this implement example be with virtual address among two positions as one index, therefore appoint What virtual address may both correspond to one of multiple conversion entrances that the second memory space 320 is included.In other words, second Multiple conversion entrances that memory space 320 is included are to correspond respectively to a part of position according to a virtual address (that is, the 15,16 positions [15:14]) digit (that is, 2) be formed by multiple patterns (that is, " 00 ", " 01 ", " 10 " and " 11 ")
Implement in example herein, is written when receiving the virtual physical address conversion by virtual address 0x0000_8000 One specific buffering entrance (correspond to buffer index IND(3)) instruction when, the first memory space 310 and the second memory space 320 Corresponding processing circuit (for example, implement according to processing circuit 130 shown in FIG. 1 or processing circuit shown in Fig. 2 230 Processing circuit；It is not shown in Fig. 4) it can come according to the position [15:14] (that is, virtual index) of virtual address 0x0000_8000 Virtual physical address conversion is stored in write-in conversion entrance.More specifically, which first can be according to virtual The position pattern (that is, " 10 ") of the position [15:14] of address 0x0000_8000 come be indexed to it is multiple conversion entrance among one turn Change to the conversion entrance of mouth (that is, correspond to conversion index idx(2)) conversion entrance to be indexed at present as one, wherein Conversion index idx(2) correspond to virtual address 0x0000_8000 position [15:14] position pattern " 10 ", in other words, conversion Index idx(2) index value " 2 " be equal to the values of binary number " 10 ".
Next, the processing circuit can determine whether the conversion entrance indexed at present can be used, to generate a judgement knot Fruit, and the virtual physical address is converted according to the judging result and stores write-in conversion entrance.From the figure 3, it may be seen that due to right Idx(2 should be indexed in conversion) conversion entrance do not store the conversion of any virtual physical address, indicate that this was indexed at present turns It is available for changing to mouth, therefore can directly store virtual address 0x0000_8000 and physical address 0x9000_0000 in wherein, with complete Write-in conversion entrance is stored in (that is, corresponding to conversion at by the virtual physical address conversion of virtual address 0x0000_8000 Index idx(2) conversion entrance) operation (as shown in Figure 4).In addition, effectively bit field v1 can be set as " 1 " to indicate data It is stored in wherein, physical paging start field pa_start1, which can be set as " 0x9000_0000 " and multipage field mp1, to be set It is " 0x1 " (that is, the corresponding paging of physical address 0x9000_0000 is to be the of physical paging start field 0x9000_0000 1 paging)
Furthermore the processing circuit separately can write virtual address 0x0000_8000 with corresponding to write-in conversion entrance one Enter conversion index (that is, conversion index idx(2)) it is stored in the specific buffering entrance (corresponding to buffer index IND(3)), it lifts Example for, this it is specific buffering entrance conversion index field idx can be set as conversion index idx(2) index value " 2 ", in addition, Effective bit field v of the specific buffering entrance can be set as " 1 ".
Please come together with Fig. 4 refering to Fig. 5.Fig. 5 is for the first memory space 310 and the second memory space 320 shown in Fig. 3 The one of the virtual physical address conversion operation schematic diagram for implementing example is carried out, wherein address conversion management shown in fig. 5 operation is Connect address conversion management operation shown in Fig. 4.Implement in example herein, above-mentioned virtual physical address converting system is to receive separately One write instruction, instruction will be between a virtual address 0x0000_9000 and corresponding physical address 0x8000_1000 Buffering entrance of the one virtual physical address conversion write-in corresponding to buffer index IND(6).Due to virtual address 0x0000_9000 The position pattern of position [15:14] (that is, virtual index) be also " 10 ", therefore above-mentioned processing circuit can also be indexed to corresponding conversion rope Draw idx(2) conversion entrance of the conversion entrance to be indexed at present as one.As shown in Figure 4, what this was indexed at present is converted into The holding tank of the road the Kou W2 and conversion of not stored any virtual physical address is (that is, the conversion entrance indexed at present is not It is occupied full (occupied)), the conversion entrance indexed at present is represented to be available, and therefore, above-mentioned processing circuit can foundation Virtual address 0x0000_9000 and physical address 0x8000_1000 are respectively stored in by process described in the related description of Fig. 4 Virtual address field vaddr2 and physical address field paddr2.Significantly, since physical address 0x8000_1000 institute Corresponding paging is for the 2nd paging of physical paging start field 0x8000_0000, therefore multipage field mp2 can be set as " 0x2 " (that is, binary format " 0010 ").Other are just repeated no more herein with the above-mentioned similar place of implementation example.
Please come together with Fig. 5 refering to Fig. 6.Fig. 6 is for the first memory space 310 and the second memory space 320 shown in Fig. 3 The one of the virtual physical address conversion operation schematic diagram for implementing example is carried out, wherein address conversion management shown in fig. 6 operation is Connect address conversion management operation shown in fig. 5.Implement in example herein, above-mentioned virtual physical address converting system is to receive separately One write instruction, instruction will be between a virtual address 0x0000_a000 and corresponding physical address 0x8000_2000 Buffering entrance of the one virtual physical address conversion write-in corresponding to buffer index IND(1).Due to virtual address 0x0000_a000 The position pattern of position [15:14] be also " 10 ", therefore above-mentioned processing circuit can also be indexed to corresponding conversion index idx(2) conversion Conversion entrance of the entrance to be indexed at present as one.As shown in Figure 5, although corresponding to the conversion entrance indexed at present Holding tank has been occupied full, but the processing circuit still can determine whether virtual address 0x0000_a000 and physical address 0x8000_ Whether 2000 is right adjacent to any virtual physical address conversion institute being stored among the conversion entrance indexed at present respectively The virtual address and physical address answered.Since virtual address 0x0000_a000 and physical address 0x8000_2000 is adjacent respectively In virtual address 0x0000_9000 with physical address 0x8000_1000(that is, meeting the condition for merging paging), processing electricity It is available that road, which still judges the conversion entrance indexed at present, and accordingly by virtual address 0x0000_a000 and physical address The virtual physical address conversion of 0x8000_2000 is stored in the conversion entrance indexed at present.
In fact, multipage field mp2 can be updated to " 0x6 " (as shown in Figure 6) using as will virtually by the processing circuit The virtual physical address conversion of location 0x0000_a000 and physical address 0x8000_2000 is stored in the conversion indexed at present The operating result of entrance.It note that multipage field mp2 is updated to " 0x6 " and represents physical paging start field 0x8000_0000 The 2nd paging (the position pattern " 01 " of the position [13:12] corresponding to physical address 0x8000_1000) and the 3rd paging (correspond to object Manage the position pattern " 10 " of the position [13:12] of address 0x8000_2000) it is merged into a merging page, it means that virtual address The virtual physical address conversion of 0x0000_9000 is stored in the virtual physical address conversion of virtual address 0x0000_a000 Corresponding conversion index idx(2) conversion entrance among.Other are just repeated no more herein with the above-mentioned similar place of implementation example.
Please come together with Fig. 6 refering to Fig. 7.Fig. 7 is for the first memory space 310 and the second memory space 320 shown in Fig. 3 The one of the virtual physical address conversion operation schematic diagram for implementing example is carried out, wherein address conversion management shown in Fig. 7 operation is Connect address conversion management operation shown in fig. 6.Implement in example herein, above-mentioned virtual physical address converting system is to receive separately One write instruction, instruction will be between a virtual address 0x0010_8000 and corresponding physical address 0x8010_0000 Buffering entrance of the one virtual physical address conversion write-in corresponding to buffer index IND(0).Due to virtual address 0x0010_8000 The position pattern of position [15:14] be also " 10 ", therefore above-mentioned processing circuit can also be indexed to corresponding conversion index idx(2) conversion Conversion entrance of the entrance to be indexed at present as one.It will be appreciated from fig. 6 that storage corresponding to the conversion entrance indexed at present Slot has been occupied full, and virtual address 0x0010_8000 and physical address 0x8010_0000 be not current adjacent to this is stored in Any virtual physical address conversion among conversion entrance indexed corresponding virtual address and physical address therefore should Processing circuit judges that the conversion entrance indexed at present is unavailable, which is just indexed to adjacent to current institute's rope The conversion entrance of another conversion entrance (for example, correspond to conversion index idx(3) of the conversion entrance drawn) using as the current institute The conversion entrance of index, and repeat it is above-mentioned judge the conversion entrance indexed at present whether can with the step of (for example, should Whether the conversion entrance indexed at present is occupied full, or whether has adjacent virtual address and physical address), to generate the judgement As a result.
It will be appreciated from fig. 6 that due to correspond to conversion index idx(3) conversion entrance do not store any virtual physical address Conversion, therefore the judging result can indicate that the conversion entrance indexed at present is available.The processing circuit can be by the current institute The conversion entrance of index converts entrance as the write-in, by virtual address 0x0010_8000's and physical address 0x8010_0000 Virtual physical address conversion stores the conversion entrance indexed at present.It is worth noting that, the processing circuit separately updates correspondence In conversion index idx(2) conversion entrance shift state field.In fact, the processing circuit can will lose a digital section Num_e is set as " 1 " and search range field ran_s is set as " 1 " (as shown in Figure 7), wherein search range field ran_s table Show the conversion entrance of the conversion entrance indexed at present (that is, corresponding to conversion index idx(3)) apart from what is stored originally The conversion entrance of conversion entrance (that is, correspond to conversion index idx(2)) entrance number of converting be 1, and lose an a digital section Num_e " 1 " indicate by the conversion entrance to be stored originally is unavailable and store to other conversion entrance indexed (that is, The conversion entrance indexed at present；Corresponding to conversion index idx(3) conversion entrance) virtual physical address conversion Number is 1.In addition, the virtual physical address conversion due to virtual address 0x0010_8000 and physical address 0x8010_0000 is to deposit Be stored in correspond to conversion index idx(3) conversion entrance, therefore, correspond to buffer index IND(0) buffering entrance conversion Index field idx can be set as 3.
It is worth noting that, the selection of conversion entrance is only to need for explanation above.In a design variation, when the judgement As a result the conversion entrance of the conversion entrance indexed at present (for example, corresponding to conversion index idx(2) is indicated) it is unavailable When, which can also be indexed to being converted into for other adjacent conversion entrance (for example, corresponding to conversion index idx(1) Mouthful) conversion entrance to be indexed at present as this, and carry out subsequent operation.From the foregoing, it will be observed that relevant virtual physical address Conversion is storable in adjacent conversion entrance, therefore system operation efficiency can be substantially improved.Other with above-mentioned implementation example it is similar it This is in just to repeat no more.
Please come together with Fig. 7 refering to Fig. 8.Fig. 8 is for the first memory space 310 and the second memory space 320 shown in Fig. 3 The one of the virtual physical address conversion operation schematic diagram for implementing example is carried out, wherein address conversion management shown in Fig. 8 operation is Connect address conversion management operation shown in Fig. 7.Implement in example herein, above-mentioned virtual physical address converting system is to receive separately One write instruction, instruction will be between a virtual address 0x0000_c000 and corresponding physical address 0x0000_0000 Buffering entrance of the one virtual physical address conversion write-in corresponding to buffer index IND(2).Due to virtual address 0x0000_c000 The position pattern of position [15:14] be " 11 ", therefore above-mentioned processing circuit can be indexed to corresponding conversion index idx(3) conversion entrance Using the conversion entrance indexed at present as one.As shown in Figure 7, this indexed at present conversion entrance road W2 holding tank simultaneously Not stored any virtual physical address conversion, therefore, above-mentioned processing circuit can process described in the related description according to Fig. 4 divide Not by virtual address 0x0000_c000 and physical address 0x0000_0000 be stored in virtual address field vaddr2 with physically Location field paddr2.Other are just repeated no more herein with the above-mentioned similar place of implementation example.
Please come together with Fig. 8 refering to Fig. 9.Fig. 9 is for the first memory space 310 and the second memory space 320 shown in Fig. 3 The one of the virtual physical address conversion operation schematic diagram for implementing example is carried out, wherein address conversion management shown in Fig. 9 operation is Connect address conversion management operation shown in Fig. 8.Implement in example herein, above-mentioned virtual physical address converting system is to receive separately One write instruction, instruction will be between a virtual address 0x0020_8000 and corresponding physical address 0x8020_0000 Buffering entrance of the one virtual physical address conversion write-in corresponding to buffer index IND(4).Due to virtual address 0x0020_8000 The position pattern of position [15:14] be " 10 ", therefore above-mentioned processing circuit can be indexed to corresponding conversion index idx(2) conversion entrance Using the conversion entrance indexed at present as one.As shown in Figure 8, holding tank corresponding to the conversion entrance indexed at present is equal It has been be occupied full that, and virtual address 0x0020_8000 and physical address 0x8020_0000 be not adjacent to being stored in current institute's rope Any virtual physical address conversion among conversion entrance drawn corresponding virtual address and physical address, therefore, the processing Circuit can be indexed to another conversion entrance adjacent to the conversion entrance indexed at present (for example, corresponding to conversion index Idx(3 conversion entrance)) conversion entrance to be indexed at present as this.However, due to corresponding to conversion index idx(3) Conversion entrance is also occupied full, and does not meet the condition of above-mentioned merging paging, and therefore, which is indexed to again adjacent to this The conversion entrance of a conversion entrance (that is, corresponding to conversion index idx(0) for the conversion entrance indexed at present).
As shown in Figure 8, due to correspond to conversion index idx(0) conversion entrance do not store any virtual physical address Conversion, therefore the conversion entrance that this is indexed at present can be converted entrance as the write-in by the processing circuit, by virtual address The virtual physical address conversion of 0x0020_8000 and physical address 0x8020_0000 stores the conversion entrance indexed at present. Similarly, the processing circuit separately will correspond to conversion index idx(2) conversion entrance loss digital section num_e be updated to " 2 ", and search range field ran_s is set as " 2 " (as shown in Figure 9).Other with the above-mentioned similar place of implementation example herein just It repeats no more.
Note that it is above only for explanation need, be not used as limitation of the invention.For example, virtual address it In correspond to paging range, merge the visual actual design demand of digit of page and/or virtual index to adjust.In addition, multipage word The embodiment of section is not limited to above-mentioned implementation example, for example, can also only with the position patterns of two positions (that is, " 00 ", " 01 ", " 10 ", " 11 ") indicate the numbers of pages of 4 pagings.Furthermore the embodiment of shift state field is also not necessarily limited to State implementation example, for example, shift state field can store a byte (byte), and wherein first four position is (effective from minimum Count position) it can correspond to search range field ran_s and rear four positions can correspond to lose a digital section num_e.
In addition to write operation, virtual physical address converting system provided by the present invention can also promote access/read operation Operational paradigm.Referring to Fig. 9.Implement in example herein, when 320 institute of the first memory space 310 and the second memory space Corresponding virtual physical address converting system receives a sense order, and (it indicates that one virtual address 0x0020_8000 institute of reading is right When the physical address answered, the processing circuit can according to virtual address 0x0020_8000 a part of position (for example, position [15: 14]) to read the physical address from the second memory space 320.
For example, which can come according to the position pattern " 10 " of the position [15:14] of virtual address 0x0020_8000 Be indexed to correspond to conversion index idx(2) a particular conversion entrance.Next, the processing circuit can virtual address 0x0020_ 8000 convert corresponding multiple virtual addresses with the multiple virtual physical address being stored among the particular conversion entrance 0x0000_8000,0x0000_9000 make comparisons with 0x0000_a000.Virtual address can be found among the particular conversion entrance When 0x0020_8000, which can read the physical address from the particular conversion entrance；When the processing circuit does not exist When the particular conversion entrance finds matched virtual address, which separately can refer to the shift state of the particular conversion entrance Field, to read the physical address from other conversion entrances.Implement in example herein, since the processing circuit is specific not at this Conversion entrance finds virtual address 0x0020_8000, therefore the processing circuit will be referring to the loss number of the particular conversion entrance Field num_e and search range field ran_s try to read the physical address.
The loss digital section num_e of the particular conversion entrance is set to " 2 ", and representative has 2 virtual physical address conversions It stores because the particular conversion entrance is unavailable at least one other conversion entrances, in addition, the search of the particular conversion entrance Range field ran_s is also set as " 2 ", represents turn that the distance particular conversion entrance is most among at least one other conversion entrances Changing to mouth number is 2.Therefore, the processing circuit can successively be indexed to correspond to conversion index idx(3) conversion entrance and Corresponding to conversion index idx(0) conversion entrance, to check whether there is matched virtual address.In this way, the processing circuit Conversion index idx(0 can corresponded to) conversion entrance find matched virtual address, and read the physical address (that is, Physical address 0x8020_0000).
Implement in example herein, when the received sense order of institute is that one virtual address 0x0020_c000 institute of instruction reading is right When the physical address answered, those skilled in the art should be appreciated that the processing circuit can not be found via above-mentioned related description The virtual address matched, therefore, the processing circuit can one translation lookaside buffer of feedback loss (TLB miss).In other words, this hair The compatible microprocessor with no interlock lines stage of virtual physical address converting system provided by bright.
Above-mentioned lookup operations see flow chart shown in Fig. 10.Figure 10 is for virtual physical address converting system of the present invention Management method an embodiment flow chart, wherein this method, which can be used for consulting, is stored in a physical vlan of a memory space (for example, in Fig. 9, access is stored among the second memory space 320 corresponding to virtual address 0x0020_8000 address conversion Physical address), and can simply be summarized as follows:
Step 1000: starting.
Step 1002: using a part of position of the virtual address as a virtual index (for example, it is shown in Fig. 9 virtually The position pattern " 10 " of the position [15:14] of location 0x0020_8000).
Step 1004: the particular conversion entrance corresponding to particular conversion index is indexed to according to the virtual index The conversion entrance of (for example, corresponding to conversion index idx(2)), wherein particular conversion index corresponds to the virtual index.
Does step 1006: the memory space, which has, store the conversion of a virtual physical address corresponding to the virtual address? if Have, executes step 1008；Conversely, executing step 1007.
Step 1007: increase the index value (for example, the virtual index is updated to a pattern " 11 ") of the virtual index, and Index value corresponding to the position of the part of the index value (for example, 3) and the virtual address of the virtual index after judgement increase The index value " 2 " of (for example, correspond to conversion index idx(2)) between gap whether be greater than the part of the virtual address The search range field of a search range field (for example, corresponding to conversion index idx(2) for conversion entrance corresponding to position Ran_s " 2 ")? if so, executing step 1009；Anti-, execute step 1004.
Step 1008: returning a physical address corresponding to the virtual address.
Step 1009: one translation lookaside buffer of feedback is lost.
Step 1010: terminating.
For consulting physical address corresponding to virtual address 0x0020_8000 shown in Fig. 9, in step 1007, When the virtual index self-alignment pattern " 10 " is updated to a pattern " 11 ", corresponding index value also can be updated to " 3 " from " 2 ", In addition, separately can by after increase index value " 3 " and conversion index idx(2) index value " 2 " between difference (that is, " 1 ") with turn Change index idx(2) corresponding to search range field ran_s " 2 " make comparisons, to determine whether will be according to updated virtual rope It attracts and carries out subsequent index operation.If the difference of above-mentioned index value is less than (or being equal to) search range field, it means that updating Conversion entrance corresponding to virtual index afterwards (correspond to conversion index idx(3)) it might have stored and should be stored in originally Corresponding conversion index idx(2) conversion entrance virtual physical address conversion, therefore, step 1004 can be executed again.However, If the poor great-than search range field of above-mentioned index value, it means that conversion entrance corresponding to updated virtual index is (right Should in conversion index idx(3)) and not stored script should be stored in corresponding conversion index idx(2) conversion entrance it is virtual Therefore step 1009 can be performed with feedback translation lookaside buffer loss in physical address translations.Due to those skilled in the art After reading related description shown in FIG. 1 to FIG. 9, the operation of each step in method shown in Fig. 10 should can will readily appreciate that Details, therefore further instruction just repeats no more herein.
In addition, in a part of position according to a virtual address come before carrying out above-mentioned dependent write operation, processing electricity Road can separately check whether to be written one specific buffering entrance can be used.If the specific buffering entrance is available, which can Carry out above-mentioned dependent write operation: conversely, if the specific buffering entrance is unavailable (for example, the one of one particular virtual address of storage Specific virtual physical address conversion), then the processing circuit will need to first be stored in the specific buffering entrance and second storage is empty Between among specific virtual physical address conversion delete, the virtual physical address of the virtual address is then converted into write-in again. Please come refering to fig. 11 together with Fig. 9.Figure 11 is to carry out void for the first memory space 310 shown in Fig. 3 and the second memory space 320 The one of quasi- physical address translations operation implements the schematic diagram of example, and the wherein operation of address conversion management shown in Figure 11 is hookup The operation of address conversion management shown in 9.Implement in example herein, which is to receive another write-in to refer to It enables, indicates the virtual object between a virtual address 0x0000_4000 and corresponding physical address 0x0000_0000 Manage the buffering entrance of the specific buffering entrance (that is, corresponding to buffer index IND(0) of address conversion write-in one).As shown in Figure 9, The specific buffering entrance has stored transitional information corresponding to virtual address 0x0010_8000, and therefore, which needs elder generation It will be stored among the first memory space 310 and the second memory space 320 one corresponding to virtual address 0x0010_8000 Specific virtual physical address conversion is deleted.
In fact, the particular conversion index that the processing circuit can first be stored the specific buffering entrance is (that is, conversion Index idx(3) index value " 3 ") and a part of position (that is, position [15:14]) of virtual address 0x0010_8000 carry out Mapping, and the specific virtual physical address being stored among the first memory space 310 and the second memory space 320 is deleted accordingly Conversion.
When particular conversion index corresponds to position [15:14] of virtual address 0x0010_8000, it means that the spy Determine virtual physical address conversion and be stored in scheduled conversion entrance originally, which can be by deleting the second memory space The specific virtual physical address conversion (example that the corresponding particular conversion entrance of particular conversion index is stored among 320 Such as, update effective bit field, virtual address field, physical address field, physical paging start field and/or multipage field), delete The virtual address 0x0010_8000 stored except the first memory space 310 and the particular conversion index, and to update this specific slow Effective bit field of mouth is poured, to complete to remove the operation of the specific virtual physical address conversion.However, implementing example herein In, since the particular conversion indexes and does not correspond to the position [15:14] of virtual address 0x0010_8000, it means that this is specific Virtual physical address conversion is not stored in scheduled conversion entrance originally, and therefore, which separately will be updated originally predetermined Conversion entrance shift state field.As shown in figure 11, be stored in corresponding to buffer index IND(0) buffering entrance and Be stored in and correspond to conversion index idx(3) the specific virtual physical address of conversion entrance convert and be removed, in addition, The processing circuit is will to correspond to conversion index idx(2) the loss digital section num_e of conversion entrance be updated to " 1 ".
Next, the processing circuit can be by the void of virtual address 0x0000_4000 and physical address 0x0000_0000 Quasi- physical address translations are stored among the first memory space 310 and the second memory space 320 (as shown in figure 12).Due to ability After the technical staff in domain is via the related description for reading Fig. 3~Fig. 9, it should be appreciated that storing the behaviour of virtual physical address conversion Make details, therefore further instruction just repeats no more herein.
Please come refering to fig. 13 together with Figure 12.Figure 13 is for the first memory space 310 shown in Fig. 3 and the second memory space 320 carry out the schematic diagram of an implementation example of virtual physical address conversion operation, and wherein address conversion management shown in Figure 13 is grasped Work is the operation of address conversion management shown in hookup 12.Implement in example herein, which is to connect Receive another write instruction, instruction by a virtual address 0x0030_0000 and corresponding physical address 0x0000_0000 it Between virtual physical address conversion write-in one specific buffering entrance (that is, correspond to buffer index IND(4) being buffered into Mouthful).As shown in Figure 12, which has stored transitional information corresponding to virtual address 0x0020_8000, therefore, The processing circuit needs first be stored among the first memory space 310 and the second memory space 320 about virtual address A specific virtual physical address conversion corresponding to 0x0020_8000 is deleted, be then written again virtual address 0x0030_0000 with Virtual physical address conversion between physical address 0x0000_0000.Significantly, since deleting virtual address The relationship of specific virtual physical address conversion corresponding to 0x0020_8000, the processing circuit can will correspond to conversion index idx (2) the loss digital section num_e of conversion entrance is updated to " 0 " (as shown in figure 13), it means that corresponding to conversion index Idx(2 the address conversion that conversion entrance) has not been lost is corresponding, and therefore, which can will also correspond to conversion Index idx(2) the search range field ran_s of conversion entrance be updated to " 0 ".Since those skilled in the art is via reading After the related description of Fig. 3~Figure 12, it should be appreciated that the details of operation of virtual physical address conversion is stored, therefore further It is bright just to repeat no more herein.
Also referring to Fig. 9, Figure 11, Figure 12 and Figure 14.Figure 14 is for virtual physical address converting system of the present invention The flow chart of one embodiment of management method, wherein this method be for virtual physical address conversion write operation (for example, In implementation example shown in Fig. 9, Figure 11 and Figure 12, by the virtual physical address of virtual address 0x0000_4000 conversion write-in/ Buffering entrance of the storage corresponding to buffer index IND(0)).This method can be simply summarized as follows:
Step 1400: starting.
Step 1402: with a part of position of one first virtual address (for example, the position of virtual address 0x0000_4000 The position of [15:14]) as one first conversion index (that is, a virtual index).
Step 1404: reading the slow of the specific buffering entrance of will be replicated one (for example, corresponding to buffer index IND(0) Pour mouth), it is indexed with obtaining one second conversion that the specific buffering entrance is stored (for example, the switching cable with index value " 3 " Draw).
Step 1406: deleting one second corresponding conversion entrance of the second conversion index (for example, the second memory space Among 320 correspond to conversion index idx(3) conversion entrance) stored one second virtual physical address conversion.
Step 1407: attracting the particular conversion for being indexed to and indexing corresponding to a particular conversion according to first switching cable and enter The conversion entrance of mouth (for example, corresponding to conversion index idx(1 among second memory space 320)), wherein the particular conversion indexes Corresponding to the first conversion index.
Step 1408: judging whether the particular conversion entrance has available road.If so, executing step 1410；Conversely, executing Step 1409.
Step 1409: increasing the index value of the first conversion index.
Step 1410: by one first virtual physical address conversion one second memory space of write-in of first virtual address (for example, the virtual physical address conversion write-in of virtual address 0x0000_4000 is corresponded to conversion index idx(1) is converted into Mouthful).
Step 1412: updating one first memory space (for example, by the virtual physical address of virtual address 0x0000_4000 Buffering entrance of the conversion write-in corresponding to buffer index IND(0)).
Step 1414: terminating.
Since those skilled in the art is via reading shown in Fig. 1~Figure 13 after related description, should can will readily appreciate that The details of operation of each step in method shown in Figure 14, therefore further instruction just repeats no more herein.

Claims (34)

1. a kind of management method of virtual physical address converting system, includes:
There is provided one first memory space, wherein first memory space includes multiple buffering entrances；
There is provided one second memory space, wherein second memory space includes multiple conversion entrances and the multiple conversion Entrance is indexed corresponding to multiple conversions；And
When one write instruction of reception is with specific slow by the one of the multiple buffering entrance of one first virtual physical address conversion write-in When pouring mouthful, the position of a first part of one first virtual address corresponding according to first virtual physical address conversion is come First virtual physical address conversion is stored in the write-in conversion entrance among the multiple conversion entrance, and by institute It states a write-in conversion index corresponding to the first virtual address and said write conversion entrance and is stored in the specific buffering entrance,
Wherein, the multiple conversion index is the position for corresponding respectively to the first part according to first virtual address Digit is formed by multiple patterns.
2. according to the method described in claim 1, wherein, first virtual physical address conversion being stored in said write and is turned The step of changing to mouth includes:
The position of the first part according to first virtual address is virtual with described first by first virtual address Corresponding one first physical address in address is stored in said write conversion entrance.
3. at least one of the multiple conversion entrance includes multiple holding tanks according to the method described in claim 1, wherein, And the multiple holding tank is to store multiple virtual physical address conversions.
4. according to the method described in claim 1, wherein, first virtual physical address conversion being stored in said write and is turned The step of changing to mouth includes:
The position pattern of the position of the first part according to first virtual address come be indexed to the multiple conversion entrance it In one first conversion entrance of the conversion entrance to be indexed at present as one, wherein one first turn of the first conversion entrance Change the position pattern that index corresponds to the position of the first part；And
Judge whether the conversion entrance indexed at present can be used, to generate a judging result；And
First virtual physical address conversion is stored to said write according to the judging result and converts entrance.
5. according to the method described in claim 4, wherein, when the judging result indicate it is described indexed at present be converted into When mouth is available, first virtual physical address is converted to the step of storage said write conversion entrance according to the judging result Suddenly include:
Entrance is converted using the conversion entrance indexed at present as said write, and first virtual physical address is turned It changes and stores to the conversion entrance indexed at present.
6. according to the method described in claim 4, wherein, the step of whether the conversion entrance indexed at present can be used judged Include:
Judge whether the conversion entrance indexed at present has taken；
Wherein, when the conversion entrance indexed at present does not take, the judging result indicates described current indexed Conversion entrance be available.
7. according to the method described in claim 6, wherein, the step of whether the conversion entrance indexed at present can be used judged It additionally comprises:
When the conversion entrance indexed at present has taken, first virtual address and first virtual address are judged Whether corresponding first physical address is respectively adjacent to one second be stored among the conversion entrance indexed at present Virtual physical address conversion corresponding one second virtual address and one second physical address；
Wherein, when first virtual address and first physical address respectively adjacent to second virtual address with it is described When the second physical address, the judging result indicates that the conversion entrance indexed at present is available.
8. the conversion entrance indexed at present includes a multipage field according to the method described in claim 7, wherein, with And when the judging result indicates that the conversion entrance indexed at present is available, according to the judging result by institute The step of stating the first virtual physical address conversion storage said write conversion entrance includes:
Described current indexed is stored in by updating the multipage field as by first virtual physical address conversion Conversion entrance operating result, wherein it is described indexed at present convert entrance be into said write convert entrance.
9. according to the method described in claim 8, wherein, by updating the multipage field as by first virtual object The step of reason address conversion is stored in the operating result of the conversion entrance indexed at present includes:
One second part according to first virtual address is located at position corresponding among first physical address, described One second part of the second virtual address is located at position corresponding among second physical address to update the multipage word Section makes the multipage field indicate the corresponding number of pages of first physical address and second physical address institute；
Wherein, the position of second part of first virtual address being located among first virtual address is identical In the position of second part of second virtual address being located among second virtual address.
10. according to the method described in claim 4, wherein, when the judging result indicates the conversion indexed at present When entrance is unavailable, described first of first virtual address corresponding according to first virtual physical address conversion The said write that first virtual physical address conversion is stored among the multiple conversion entrance is converted by the position of part The step of mouth, additionally comprises:
The one second conversion entrance adjacent to the conversion entrance indexed at present is indexed to current to be indexed as described Conversion entrance, and repeat and judge whether the conversion entrance indexed at present can be used to generate the judging result Step.
11. according to the method described in claim 10, wherein, each conversion entrance includes a shift state field；It is repeating to hold Row judge the conversion entrance indexed at present whether can with the step of after, the judging result indicates the current institute When the conversion entrance of index can be used, first virtual physical address is converted into storage said write according to the judging result The step of converting entrance includes:
Entrance is converted using the conversion entrance indexed at present as said write to turn first virtual physical address The storage conversion entrance indexed at present is changed, and updates shift state field corresponding to the first conversion entrance, In, the updated shift state field is to indicate that the conversion entrance indexed at present is converted into apart from described first The conversion entrance number of mouth, and indicate and store since the first conversion entrance is unavailable to turn indexed at present The virtual physical address for changing to mouth converts number.
12. according to the method described in claim 1, wherein, instructing when receiving said write with by first physical vlan When the specific buffering entrance of the multiple buffering entrance of location conversion write-in, the method is additionally comprised:
Check whether the specific buffering entrance can be used；And
When the specific buffering entrance has stored particular conversion index and a particular virtual address, empty by described first Quasi- physical address translations are stored in front of said write conversion entrance, map particular conversion index and described specific virtual The position of one first part of address, and delete be stored in institute among first memory space and second memory space accordingly A specific virtual physical address conversion corresponding to particular virtual address is stated, wherein described first of the particular virtual address The position being located among the particular virtual address of part is the same as the position of the first part of first virtual address Position among first virtual address.
13. according to the method for claim 12, wherein deletion is stored in first memory space and second storage The step of specific virtual physical address corresponding to particular virtual address described in space is converted includes:
Delete the institute that the corresponding particular conversion entrance of the index of particular conversion described in second memory space is stored State specific virtual physical address conversion；And
Delete the particular virtual address and particular conversion index that first memory space is stored.
14. according to the method for claim 13, wherein the position of the first part of the particular virtual address is corresponding The one first conversion entrance among the multiple conversion entrance, one first corresponding conversion entrance of the first conversion index Include a shift state field；The shift state field is to indicate to store and arrive since the first conversion entrance is unavailable The number of at least virtual physical address conversion of at least one second conversion entrance, and indicate at least one second conversion Conversion entrance number of the entrance apart from the first conversion entrance；And when the particular conversion indexes and does not correspond to the spy When determining the position of the first part of virtual address, deletion be stored in first memory space and second memory space it Described in the conversion of the specific virtual physical address corresponding to particular virtual address the step of additionally comprise:
Update the shift state field of the first conversion entrance.
15. a kind of management method of virtual physical address converting system, includes:
One memory space is provided, wherein the memory space include multiple conversion entrances, the multiple conversion entrance be store to Few virtual physical address conversion, and correspond respectively to multiple conversion indexes；And
When receive a sense order to read a physical address corresponding to a virtual address when, according to the virtual address one The position of part to read the physical address from the memory space,
Wherein, the multiple conversion index is the digit institute for corresponding respectively to the position of some according to the virtual address The multiple patterns formed.
16. according to the method for claim 15, wherein the position of the part according to the virtual address from described to deposit What storage space read the physical address step includes:
The particular conversion entrance being indexed among the multiple conversion entrance, wherein one specific turn of the particular conversion entrance Change the position that index corresponds to the part of the virtual address；And
The virtual address is converted at least at least virtual physical address being stored among the particular conversion entrance One virtual address is made comparisons, and reads the physical address accordingly.
17. according to the method for claim 16, wherein the particular conversion entrance includes a shift state field；It is described Shift state field is to indicate to store at least one other conversion entrances extremely since the particular conversion entrance is unavailable The number of few virtual physical address conversion, and indicate that described at least one other conversion entrances enter apart from the particular conversion The conversion entrance number of mouth；And among the particular conversion entrance and when the not stored virtual address, from the storage The step of space reading physical address, includes:
Carry out other conversion entrances from described at least one according to the shift state field and reads the physical address.
18. a kind of virtual physical address converting system, includes:
One first memory space includes multiple buffering entrances；
One second memory space, includes multiple conversion entrances, and the multiple conversion entrance is to correspond respectively to multiple conversion indexes； And
One processing circuit is coupled to first memory space and second memory space, wherein when the system receives The conversion of one first virtual physical address to be written the specific buffering entrance among the multiple buffering entrance by one write instruction When, the processing circuit is one first of one first virtual address corresponding according to first virtual physical address conversion First virtual physical address conversion is stored in the write-in conversion entrance among the multiple conversion entrance by the position of part, And a write-in conversion index corresponding to first virtual address and said write conversion entrance is stored in described specific Entrance is buffered,
Wherein, the multiple conversion index is the position for corresponding respectively to the first part according to first virtual address Digit is formed by multiple patterns.
19. system according to claim 18, wherein the processing circuit is according to described in first virtual address The position of first part stores first virtual address, one first physical address corresponding with first virtual address Entrance is converted in said write, first virtual physical address conversion is stored in said write conversion entrance.
20. system according to claim 18, wherein at least one of the multiple conversion entrance includes multiple storages Slot and the multiple holding tank are to store multiple virtual physical address conversions.
21. system according to claim 18, wherein the processing circuit be to:
The position pattern of the position of the first part according to first virtual address come be indexed to the multiple conversion entrance it In one first conversion entrance of the conversion entrance to be indexed at present as one, wherein one first turn of the first conversion entrance Change the position pattern that index corresponds to the position of the first part；
Judge whether the conversion entrance indexed at present can be used, to generate a judging result；And
First virtual physical address is converted into storage said write according to the judging result and converts entrance.
22. system according to claim 21, wherein when the judging result indicates the conversion indexed at present When entrance can be used, the processing circuit is conversion entrance using the conversion entrance indexed at present as said write, and will The first virtual physical address conversion is stored to the conversion entrance indexed at present.
23. system according to claim 21, wherein the processing circuit is by checking the conversion indexed at present Whether entrance has taken to judge whether the conversion entrance indexed at present can be used；And when turn indexed at present When change mouth does not take, the judging result is to indicate that the conversion entrance indexed at present is available.
24. system according to claim 23, wherein described when the conversion entrance indexed at present has taken Processing circuit separately judges whether first virtual address the first physical address corresponding with first virtual address is distinguished Adjacent to the one second virtual physical address conversion being stored among the conversion entrance indexed at present it is corresponding one the Two virtual addresses and one second physical address；And when first virtual address and first physical address respectively adjacent to When second virtual address and second physical address, the judging result is to indicate the conversion indexed at present Entrance is available.
25. system according to claim 24, wherein the conversion entrance indexed at present includes a multipage field, When the judging result indicates that the conversion entrance indexed at present is available, the processing circuit is through described in update Multipage field is as the operation that first virtual physical address conversion is stored in the conversion entrance indexed at present As a result, wherein the entrance of converting indexed at present is to convert entrance into said write.
26. system according to claim 25, wherein the processing circuit is one according to first virtual address Two parts be located at position corresponding among first physical address, one second part of second virtual address is located at Corresponding position updates the multipage field among second physical address, and the multipage field is made to indicate described first The corresponding number of pages of physical address and second physical address institute, wherein described second of first virtual address The position being located among first virtual address of part is the same as the position of second part of second virtual address Position among second virtual address.
27. system according to claim 21, wherein when the judging result indicates the conversion indexed at present When entrance is unavailable, the processing circuit is to be indexed to be converted into adjacent to the one second of the conversion entrance indexed at present Mouthful using as the conversion entrance indexed at present, and repeat to judge whether the conversion entrance indexed at present can be used, To generate the judging result.
28. system according to claim 27, wherein each conversion entrance includes a shift state field；It is repeating to sentence After whether the conversion entrance indexed at present that breaks is available, the judging result indicates the conversion indexed at present When entrance can be used, the processing circuit is that entrance is converted using the conversion entrance indexed at present as said write by institute It states the conversion of the first virtual physical address and stores the conversion entrance indexed at present, and it is right to update the first conversion entrance institute The shift state field answered；And the updated shift state field is to indicate the conversion entrance indexed at present Apart from it is described first conversion entrance conversion entrance number, and indicate due to it is described first conversion entrance it is unavailable and store to The virtual physical address conversion number of the conversion entrance indexed at present.
29. system according to claim 18, wherein the processing circuit separately checks that the specific buffering entrance whether may be used With；And when the specific buffering entrance has stored particular conversion index and when a particular virtual address, by described the One virtual physical address conversion be stored in said write conversion entrance before, the processing circuit separately to:
The position of a first part of the particular conversion index and the particular virtual address is mapped, and deletes be stored in accordingly A specific physical vlan corresponding to particular virtual address described in first memory space and second memory space Address conversion, wherein the position of the first part of the particular virtual address being located among the particular virtual address is It is identical to the position of the first part of first virtual address being located among first virtual address.
30. system according to claim 29, wherein the processing circuit is to delete institute among second memory space The specific virtual physical address conversion that the corresponding particular conversion entrance of particular conversion index is stored is stated, and is deleted The particular virtual address and particular conversion index that first memory space is stored.
31. system according to claim 30, wherein the position of the first part of the particular virtual address is corresponding The one first conversion entrance among the multiple conversion entrance, one first corresponding conversion entrance of the first conversion index Include a shift state field；The shift state field is to indicate to store and arrive since the first conversion entrance is unavailable The number of at least virtual physical address conversion of at least one second conversion entrance, and indicate at least one second conversion Conversion entrance number of the entrance apart from the first conversion entrance；And when the particular conversion indexes and does not correspond to the spy When determining the position of the first part of virtual address, the processing circuit separately updates the offset shape of the first conversion entrance State field.
32. a kind of system for virtual physical address conversion, includes:
One memory space includes multiple conversion entrances, and the multiple conversion entrance is to store the conversion of an at least virtual physical address, And correspond respectively to multiple conversion indexes；And
One processing circuit is coupled to the memory space, wherein when the system receives a sense order to read one virtually When a physical address corresponding to location, the processing circuit is a part of position according to the virtual address with from the storage Space reads the physical address,
Wherein, the multiple conversion index is the digit institute for corresponding respectively to the position of some according to the virtual address The multiple patterns formed.
33. system according to claim 32, wherein the processing circuit be to:
The particular conversion entrance being indexed among the multiple conversion entrance, wherein one specific turn of the particular conversion entrance Change the position that index corresponds to the part of the virtual address；And
The virtual address is converted at least at least virtual physical address being stored among the particular conversion entrance One virtual address is made comparisons, and reads the physical address accordingly.
34. system according to claim 33, wherein the particular conversion entrance includes a shift state field；It is described Shift state field is to indicate to store at least one other conversion entrances extremely since the particular conversion entrance is unavailable The number of few virtual physical address conversion, and indicate that described at least one other conversion entrances enter apart from the particular conversion The conversion entrance number of mouth；And among the particular conversion entrance and when the not stored virtual address, the processing electricity Road is to carry out other conversion entrances from described at least one according to the shift state field to read the physical address.
CN201310648140.5A 2013-12-04 2013-12-04 Virtual physical address converting system and its management method Active CN104699633B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310648140.5A CN104699633B (en) 2013-12-04 2013-12-04 Virtual physical address converting system and its management method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310648140.5A CN104699633B (en) 2013-12-04 2013-12-04 Virtual physical address converting system and its management method

Publications (2)

Publication Number Publication Date
CN104699633A CN104699633A (en) 2015-06-10
CN104699633B true CN104699633B (en) 2019-04-23

Family

ID=53346782

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310648140.5A Active CN104699633B (en) 2013-12-04 2013-12-04 Virtual physical address converting system and its management method

Country Status (1)

Country Link
CN (1) CN104699633B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101178701A (en) * 2007-12-11 2008-05-14 华为技术有限公司 Communicating method and system between multi-processor
CN101727405A (en) * 2008-10-20 2010-06-09 株式会社东芝 Effective address cache memory, processor and effective address caching method
CN103052945A (en) * 2010-08-06 2013-04-17 阿尔卡特朗讯 A method of managing computer memory, corresponding computer program product

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6519684B1 (en) * 1999-11-23 2003-02-11 Motorola, Inc. Low overhead method for selecting and updating an entry in a cache memory
US7805588B2 (en) * 2005-10-20 2010-09-28 Qualcomm Incorporated Caching memory attribute indicators with cached memory data field
CN102662860B (en) * 2012-03-15 2015-07-01 天津国芯科技有限公司 Translation lookaside buffer (TLB) for process switching and address matching method therein

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101178701A (en) * 2007-12-11 2008-05-14 华为技术有限公司 Communicating method and system between multi-processor
CN101727405A (en) * 2008-10-20 2010-06-09 株式会社东芝 Effective address cache memory, processor and effective address caching method
CN103052945A (en) * 2010-08-06 2013-04-17 阿尔卡特朗讯 A method of managing computer memory, corresponding computer program product

Also Published As

Publication number Publication date
CN104699633A (en) 2015-06-10

Similar Documents

Publication Publication Date Title
CN107832013B (en) A method of management solid-state hard disc mapping table
CN104090730B (en) Method and device for conducting data reading and writing on storage device
TWI417722B (en) Hierarchical immutable content-addressable memory processor
CN102981963B (en) A kind of implementation method of flash translation layer (FTL) of solid-state disk
US9871727B2 (en) Routing lookup method and device and method for constructing B-tree structure
US20020138648A1 (en) Hash compensation architecture and method for network address lookup
CN103176916B (en) The address conversion method of flash memory and flash memory
CN101510176B (en) Control method of general-purpose operating system for accessing CPU two stage caching
KR102437775B1 (en) Page cache device and method for efficient mapping
CN103907099B (en) Short address conversion table uncached in cache coherence computer system
JP6088951B2 (en) Cache memory system and processor system
JP4920378B2 (en) Information processing apparatus and data search method
KR20000052480A (en) System and method for cache process
CN107463447A (en) B + tree management method based on remote direct nonvolatile memory access
US20130297877A1 (en) Managing buffer memory
US9292549B2 (en) Method and system for index serialization
CN101826107A (en) Hash data processing method and device
CN116383102B (en) Translation look-aside buffer access method, device, equipment and storage medium
CN109918316A (en) A kind of method and its system reducing FTL address of cache space
CN101707881A (en) Caching of microcode emulation memory
CN103077198B (en) A kind of operating system and file cache localization method thereof
CN107766258A (en) Memory storage method and apparatus, memory lookup method and apparatus
US9824023B2 (en) Management method of virtual-to-physical address translation system using part of bits of virtual address as index
CN113253926A (en) Memory internal index construction method for improving query and memory performance of novel memory
CN104699633B (en) Virtual physical address converting system and its management method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant