CN104681482B - String selection line of 3 D memory array and preparation method thereof - Google Patents

Abstract

A kind of string selection line the invention discloses 3 D memory array and preparation method thereof, the string selection line of the 3 D memory array includes：Dielectric substrate, string selection cable architecture, the second conductive layer and oxide layer.String selection cable architecture is located in dielectric substrate, including alternately multiple dielectric layers and multiple first conductive layers of storehouse.Second conductive layer, the side wall of covering string selection cable architecture and top.Oxide layer be located between these first conductive layers and second conductive layer, and with these first conductive layers and second conductive layers make contact.

Description

String selection line of 3 D memory array and preparation method thereof

Technical field

The invention relates to a kind of semiconductor element, and in particular to a kind of string selection of 3 D memory array Line (string select line, SSL) and preparation method thereof.

Background technology

Because nonvolatile memory has the advantages that the data being stored in will not also disappear after a loss of power, therefore much electrical equipment Must possess such memory in product, to maintain normal operating when electric equipment products are started shooting.

With the size reduction of electronic component, the size of the memory being made up of memory cell array also reduces therewith.So And, current photoetching technique is limited to, the memory cell array of General Two-Dimensional (for example reduces adjacent storage single in size reduction Spacing between unit) it is restricted.

Designer is seeking the multiple membrane structure of storehouse to constitute the technology of memory cell, and this technology is potential to be reached Sizable storage volume and relatively low cost of bit.Here it is Present Attitude is subject to the three-dimensional storage of industry concern Array.However, the complexity of current 3 D memory array technique is higher, and existing photoetching is still subject in the reduction of size The limitation of technology.

The content of the invention

The present invention provides a kind of string selection line of 3 D memory array and preparation method thereof, can allow the grid of string selection line Pole is more easily controlled, and can avoid going here and there the grid situation that is programmed or wipes of selection line.

The preparation method of the string selection line of 3 D memory array of the invention is comprised the following steps：First, there is provided dielectric Substrate, has formd lamination and hard mask layer in the dielectric substrate, wherein lamination includes alternately multiple dielectric layers of storehouse and many Individual first conductive layer, and with two first openings of the dielectric substrate are exposed, lamination is located between two first openings Part is used to form string selection line；Hard mask layer covers lamination and with the second opening, and the second opening is located at these the first openings Top and expose these first opening between lamination.Then, it is heat-treated and is formed with the side wall of the part of lamination Oxide layer.Then, the second conductive layer is formed in these first openings and second opening, second conductive layer and the oxide layer Contact.Then, part lamination, part hard mask layer and the conductive layer of part second are removed, to form string selection line and bit line pattern, Wherein string selection line includes the second conductive layer of the part of the part of lamination and cladding lamination.

In one embodiment of this invention, the method for oxide layer being formed on the side wall of the part of lamination is included in lamination The part in these the first conductive layers side wall on form oxide layer.

In one embodiment of this invention, the superiors of the lamination are dielectric layer.

In one embodiment of this invention, second opening includes shape identical Part I and Part II, and Connection Part I and Part II and the Part III of lamination is exposed, the shape of Part I and Part II is respectively and often One first opening is identical.

In one embodiment of this invention, the method for removing part lamination is dry etching method, and this dry etching method pair Dielectric layer and the first conductive layer do not have selectivity.

In one embodiment of this invention, the forming method of the second opening is comprised the following steps.In dielectric substrate sequentially Form the stacked material and layer of hard mask material of covering dielectric substrate comprehensively.The shape in stacked material and layer of hard mask material It is open to form the lamination with these the first openings into two the 3rd.Remove the hard mask material between these the 3rd openings Layer with formed with this second opening the hard mask layer.

In one embodiment of this invention, remove these the 3rd opening between the layer of hard mask material method include with Lower step.The material layer filled up these the 3rd openings and cover the layer of hard mask material is formed in dielectric substrate.In the material Patterning photoresist layer is formed on layer.To pattern photoresist layer as mask, remove the part material layer and these the 3rd are opened Layer of hard mask material between mouthful.Remove the remaining material layer.

In one embodiment of this invention, the material layer includes organic dielectric materials layer and Silicon-rich polymeric layer, You Jijie Material layer fills up these the 3rd openings, and Silicon-rich polymeric layer covers dielectric substrate comprehensively.

In one embodiment of this invention, the material of dielectric layer is oxide.

In one embodiment of this invention, the material of the first conductive layer is polysilicon.

In one embodiment of this invention, the material of the second conductive layer is polysilicon.

The string selection line of 3 D memory array of the invention includes dielectric substrate；String selection cable architecture, positioned at dielectric base On bottom, string selection cable architecture includes multiple dielectric layers and multiple first conductive layers of alternately storehouse；Second conductive layer, covering string choosing Select side wall and the top of cable architecture；And oxide layer, between the first conductive layer and the second conductive layer, and with the first conductive layer With the second conductive layers make contact.

In one embodiment of this invention, the superiors of string selection cable architecture are dielectric layer.

Based on a kind of above-mentioned, preparation method of the string selection line of novel 3 D memory array of present invention proposition.Will string The technique of selection line and the technique of wordline are separated.Using gate oxide as the gate dielectric layer of grid in string selection line, this can be with The Vt is allowed to reduce, the phenomenon that the grid of selection line that will not also occur to go here and there is programmed unintentionally or wipes.

It is that features described above of the invention and advantage can be become apparent, special embodiment below is described in detail below.

Brief description of the drawings

Figure 1A to Figure 10 B are a kind of string selections of the 3 D memory array according to depicted in first embodiment of the invention The flow chart of the preparation method of line, wherein Figure 1A to Fig. 6 A, Fig. 8 A, Fig. 9 and Figure 10 A are top views, other schemas be then along Profile or partial enlarged drawing depicted in the hatching of each top view.

【Symbol description】

100：Dielectric substrate

101：Opening

102：Stacked material

102a：Dielectric layer

102b：First conductive layer

103：Opening

104：Layer of hard mask material

105：Opening

105a：Part I

105b：Part II

105c：Part III

106：Lamination

108：Material layer

109：Hard mask layer

110：Organic dielectric materials layer

112：Silicon-rich polymeric layer

114：Patterning photoresist layer

120：Second conductive layer

122：Oxide layer

124：Patterning photoresist layer

124a：Part I

124b：Part II

124c：Part III

200：Part

300：String selection line

400：Bit line pattern

500：Connection pad pattern

Specific embodiment

First embodiment of the invention proposes a kind of preparation method of the string selection line of 3 D memory array.

Figure 1A to Figure 10 is a kind of system of the string selection line of the 3 D memory array according to depicted in first embodiment Make the flow chart of method, wherein Figure 1A to Fig. 6 A, Fig. 8 A, Fig. 9 and Figure 10 are top views, other schemas are regarded along on each Profile or partial enlarged drawing depicted in the hatching of figure.

The preparation method of the string selection line of the 3 D memory array of first embodiment is comprised the following steps.Refer to figure The 1A and Figure 1B that illustrates of AA hatching lines along Figure 1A, first, there is provided dielectric substrate 100.The material of dielectric substrate 100 can be oxidation Thing, such as silica.The stacked material 102 of covering dielectric substrate 100 comprehensively is sequentially formed in dielectric substrate 100 and is covered firmly Mold materials layer 104.Although stacked material 102 is depicted as single layer structure by Figure 1B, stacked material 102 actually includes handing over For multiple dielectric layer 102a and multiple first conductive layer 102b of storehouse, for this point, the Fig. 7 that will hereafter arrange in pairs or groups makees more detailed Explanation.For example, the number of plies of the first conductive layer 102b may respectively be four layers, eight layers, 16 layers or three Floor 12s, and each Dielectric layer 102a then can be only fitted to the up or down side of every 1 first conductive layer 102b.In one embodiment, stacked material 102 the superiors are dielectric layer 102a.In another embodiment, the orlop of stacked material 102 is also dielectric layer 102a.

The material of dielectric layer 102a can be oxide, such as silica, and the material of the first conductive layer 102b then can be with It is polysilicon.The material of layer of hard mask material 104 can be nitride, such as silicon nitride.Certainly, the present invention not as Limit.For example, in other examples, the material of dielectric layer 102a can also be nitride or nitrogen oxides.Storehouse material The bed of material 102 (dielectric layer 102a and the first conductive layer 102b) and the forming method of layer of hard mask material 104 are, for example, chemical gaseous phase Sedimentation.

Fig. 2A and Fig. 2 B that illustrate of AA hatching lines along Fig. 2A is refer to, then, a part for stacked material 102 is removed With a part for layer of hard mask material 104, there is the lamination 106 and the hard mask material with multiple openings of multiple openings to be formed The bed of material 104, wherein, the opening in opening and layer of hard mask material 104 in lamination 106 together constitutes and exposes dielectric substrate 100 opening 101.The method for removing stacked material 102 and layer of hard mask material 104 is, for example, dry etching method.

Fig. 3 A and Fig. 3 B that illustrate of AA hatching lines along Fig. 3 A are refer to, then, material layer is formed in dielectric substrate 100 108, material layer 108 fills up opening 101, and comprehensively covers dielectric substrate 100.Specifically, in the present embodiment, material Layer 108 is a kind of composite construction, and it includes organic dielectric materials layer (organic dielectric layer, ODL) 110 and richness Silicon polymer layer 112.Organic dielectric materials layer 110 has preferably clearance filling capability, can successfully fill up these openings 101.Organic dielectric materials layer 110 is, for example, the trade name ODL-61 or ODL-50 of SHIN-ETSU HANTOTAI (Shin-Etsu) company production Product.Silicon-rich polymeric layer 112 is then formed on organic dielectric materials layer 110, dielectric substrate 100 is comprehensively covered, as rear Hard mask in continuous photoetching process.Silicon-rich polymeric layer 112 is, for example, the trade name of SHIN-ETSU HANTOTAI (Shin-Etsu) company production The product of SHB.

Fig. 4 A and Fig. 4 B that illustrate of AA hatching lines along Fig. 4 A are refer to, then, patterning light is formed in material layer 108 Photoresist layer 114.The forming method for patterning photoresist layer 114 is, for example, that one layer of photoetching glue material is first coated with dielectric substrate 100 The bed of material (is not illustrated), and then exposed and developed step is with by the Other substrate materials pattern layers.It is noted that due to Fig. 4 A AA photoresist layers 114 that line is not patterned through part, therefore Fig. 4 B and Fig. 3 B are identicals.In order to clearly show that patterning Photoresist layer 114 and the relativeness of opening 101, opening 101 is depicted in Fig. 4 A with dotted line in addition.

Fig. 5 A and Fig. 5 B that illustrate of AA hatching lines along Fig. 5 A are refer to, then, to pattern photoresist layer 114 to cover Mould, removes a part for material layer 108, and removes the layer of hard mask material 104 of (please with reference to Fig. 4 A) between opening 101. The method for removing material layer 108 and layer of hard mask material 104 can be dry etching method, such as reaction equation ion etching (reactive ion etching, RIE).Additionally, if the superiors of lamination 106 were dielectric layer 106a, the dielectric layer 106a can be used as etch stop layer in this dry etch process.After etching, the quilt of Silicon-rich polymeric layer 112 of material layer 108 Completely removes, only leave the organic dielectric materials layer 110 in the opening 103 of lamination 106.

Fig. 6 B, Fig. 6 C and Fig. 6 D that Fig. 6 A and the AA hatching lines respectively along Fig. 6 A, BB hatching lines and CC hatching lines are illustrated are refer to, Then, patterning photoresist layer 114 is removed, (the i.e. remaining organic dielectric materials layer of remaining material layer 108 is then removed again 110), forming lamination 106 and hard mask layer 109.The method for removing patterning photoresist layer 114 and material layer 108 can divide It is not that dry type or wet type remove photoresist method and dry type or wet etching.

As shown in Fig. 6 A to Fig. 6 D, lamination 106 has multiple openings 103；Hard mask layer 109 has opening 105.Opening 103 expose dielectric substrate 100.The part that lamination 106 is located between two openings 103 is please noted, i.e. with square void in Fig. 6 B The part 200 of line wire frame representation, a part for bunchiness selection line will be produced in follow-up technique.Opening 105 is located at opening Lamination 106 between 103 tops (see Fig. 6 A and Fig. 6 D), and exposure opening 103 (see Fig. 6 C).

More specifically, Fig. 6 A are refer to, opening 105 includes shape identical Part I 105a and Part II 105b, and connect Part I 105a and Part II 105b and expose the Part III 105c of lamination 106, Part I The shape of 105a and Part II 105b is identical with opening 103 respectively, and 103 alignment that are open with respectively.It is so-called herein Shape refers to the shape obtained by top view observation.

Referring back to Fig. 6 B, part 200 will be formed the string selection of 3 D memory array in follow-up technique Line, the first conductive layer of each of which 102b is respectively as grid.Therefore, gate dielectric layer need to be formed on the side wall of part 200. In the technique of known 3 D memory array, string selection line and wordline (word line) are simultaneously formed, therefore selection grid The gate dielectric layer of pole can be formed with " gate dielectric layer (charge storing structure) " of memory cell by the depositing operation along with, that is, Both materials and size will be identical, such as be probably thicknessArriveBetween oxide/nitride/oxidation Thing (ONO) film.However, in the present embodiment, the gate dielectric layer of string selection line is not formed in the way of depositing, but thoroughly Overheating Treatment step is formed, and is that thickness is situated betweenArrive(for example) between single thin film, than known The thickness of ONO structure is small a lot.In this regard, collocation Fig. 7 is described in detail below.

Fig. 7 individually depicts the enlarged drawing of part 200 and its partial structurtes.Fig. 7 is refer to, as being described above, Part 200 includes multiple dielectric layer 102a and multiple first conductive layer 102b of alternately storehouse.Then, it is heat-treated with portion Divide and oxide layer 122 is formed on 200 side wall.More specifically, it is that each first conductive layer 102b in part 200 is exposed Side wall on formed oxide layer 122.For example, the material in the first conductive layer 102b is in the example of polysilicon, oxide layer 122 Material is exactly silica.Additionally, the influence of dielectric layer 102a not heat-treateds in the present embodiment.Additionally, GOX (gate Oxide, gate oxide) can also through CVD or LPCVD (low pressure chemical vapor deposition, Low-pressure chemical vapor deposition) or the work such as HTO (High temperature oxide deposition, high temperature oxide deposition) Skill is formed.

Fig. 8 B, Fig. 8 C and Fig. 8 D that Fig. 8 A and the AA hatching lines respectively along Fig. 8 A, BB hatching lines and CC hatching lines are illustrated are refer to, Then, the second conductive layer 120 is formed in opening 103 and opening 105.Fig. 8 B are refer to, in opening 103, the second conductive layer 120 and lamination 106 contact, that is, the second conductive layer 120 will be contacted (referring to Fig. 7) with the oxide layer 122 for being formed just now.The The material of two conductive layers 120 can be polysilicon, and its forming method is, for example, first to be formed to fill up out with chemical vapour deposition technique Mouth 103 and the conductive material (not illustrating) of opening 105, then carry out the chemical machinery with hard mask layer 109 as suspension layer and grind again Grinding process (CMP), removes unnecessary conductive material.

Fig. 9 is refer to, then, patterning photoresist layer 124 is formed in dielectric substrate 100, pattern photoresist layer 124 Including defining the Part I 124a of bit line (bit line) pattern, defining the Part II 124b of string selection line and fixed Justice goes out the Part III 124c of connection pad pattern, and its forming method is similar with the forming method of the patterning photoresist layer 114 of Fig. 5 A, Repeated no more in this.

Figure 10 A and Figure 10 B that illustrate of AA hatching lines along Figure 10 A are refer to, then, a part for lamination 106, hard is removed A part for a part for mask layer 109 and the second conductive layer 120, to form string selection line 300, bit line pattern 400 and connection pad Pattern 500.It to pattern photoresist layer 124 is the dry etching of mask that the method for removing these materials is, such as reactivity from Son etching.Significantly, since lamination 106 is to replace heap by two kinds of materials (dielectric layer 102a and the first conductive layer 102b) The structure that stack gets up, in order to ensure resulting structures have vertically profiling (vertical profile), removes the etching of lamination 106 Technique is preferably to dielectric layer 102a and the not selective techniques of the first conductive layer 102b.

The string selection line of the 3 D memory array that second embodiment of the invention is provided is illustrated by taking Figure 10 B as an example below. String selection line 300 includes dielectric substrate 100, string selection cable architecture 302 (part 200 i.e. depicted in Fig. 6 B), the second conductive layer 120 and oxide layer 122 (can refer to Fig. 7).String selection cable architecture 300 is located in dielectric substrate 100, and it includes replacing storehouse Multiple dielectric layer 102a and multiple first conductive layer 102b (can refer to Fig. 7).The covering string selection cable architecture of second conductive layer 120 300 side wall and top.Oxide layer 122 is located between each the first conductive layer 102b and the second conductive layer 120, and is led with first Electric layer 102b and the second conductive layer 120 are contacted (can refer to Fig. 7).

It is central the step of Figure 10 A are illustrated, and string selection line 300 together formed, also bit line pattern 400.Then, may be used To re-form charge storing structure (such as ONO films or ONONO films) and conductive material on bit line pattern 400, and warp must The Patternized technique wanted extends perpendicularly to the wordline (not illustrating) of bit line pattern 400 to be formed.Thereby, three-dimensional storage is completed The making of device array.The formation of charge storing structure and wordline is known to one skilled in the art, herein no longer Repeat.

It is worth noting that, in the first embodiment, string selection line 300 is formed with bit line pattern 400, also simultaneously That is, string selection line 300 was formed before wordline is not yet formed.This is different with the technique of known 3 D memory array. Among the technique of known 3 D memory array, string selection line generally and wordline formation simultaneously, and is gone here and there in selection line, grid Gate dielectric will be ONO films.Problem is that the effect of string selection line is to switched on/off, it is not necessary to store electric charge, this It is different from wordline.Therefore, if using common ONO structure as the gate dielectric layer of string selection line, grasped in 3 D memory array Selection line of being gone here and there when making may be " programmed " or be " erased ".And the thickness of ONO structure it is too big (generally betweenArriveBetween), the raising of threshold voltage (threshold voltage, Vt) is caused, also it is unfavorable for each grid in string selection line Control.All this kind all increases the degree of difficulty of memory array control.Additionally, string selection line is a kind of island (island) knot Structure, and wordline is strip (strip) structure, when both make jointly, need to be directed to them and design different mask patterns, this The complexity of technique can be increased.

Appreciate problem above, the present invention thus propose a kind of system of the string selection line of the 3 D memory array of novelty Make method.The technique of string selection line and the technique of wordline are separated.Grid in using the gate oxide of standard as string selection line Pole dielectric medium, this can reduce the thickness (so as to reduce Vt) of gate dielectric layer, allow string selection line in grid be more easily controlled.And And, due to no longer carrying charge storing structure, the phenomenon that the grid of string selection line is programmed unintentionally or wipes will not also occur.

Although being explained as above to the present invention with embodiment, however, it is not limited to the present invention.Skill belonging to any Art has usually intellectual in field, in the premise for not departing from the spirit and scope of the present invention, when can make a little change with Retouching.Therefore the protection domain of present application is when by being defined that appended claims scope is defined.

Claims (8)

1. the preparation method of the string selection line of a kind of 3 D memory array, including：

Dielectric substrate is provided, lamination and hard mask layer have been formd in the dielectric substrate, the wherein lamination includes what is be alternately stacked Multiple dielectric layers and multiple first conductive layers, and with two first openings of the dielectric substrate are exposed, the lamination is located at this Part between a little first openings is used to form string selection line；The hard mask layer covers the lamination and with the second opening, and this Two openings are located at these first overthe openings and expose the part of the lamination；

It is heat-treated and is formed oxide layer with the side wall of the part of the lamination；

The second conductive layer is formed in these first openings and second opening, second conductive layer and the oxide layer are contacted；With And

The part lamination, the part hard mask layer and part second conductive layer are removed, to form string selection line and bit line pattern, Wherein the string selection line includes the part of the lamination and coats second conductive layer of the part of the lamination.

2. the preparation method of the string selection line of 3 D memory array according to claim 1, wherein in the lamination should The method that oxide layer is formed on partial side wall includes：

Oxide layer is formed on the side wall of these the first conductive layers in the part of the lamination.

3. the preparation method of the string selection line of 3 D memory array according to claim 1, the wherein lamination most go up Layer is the dielectric layer.

4. the preparation method of the string selection line of 3 D memory array according to claim 1, wherein the second opening bag Shape identical Part I and Part II are included, and is connected the Part I and the Part II and is exposed the lamination Part III, the Part I and the shape of the Part II are identical with every 1 first opening respectively.

5. the preparation method of the string selection line of 3 D memory array according to claim 1, wherein this is folded to remove part The method of layer is dry etching method, and the dry etching method does not have selectivity to these dielectric layers and these first conductive layers.

6. the preparation method of the string selection line of 3 D memory array according to claim 1, wherein second opening Forming method includes：

The stacked material layers and layer of hard mask material for covering the dielectric substrate comprehensively are sequentially formed in the dielectric substrate；

Two the 3rd openings are formed in the stacked material layers and the layer of hard mask material to be formed with these the first openings The lamination；And

The layer of hard mask material between these the 3rd openings is removed to form the hard mask layer with second opening.

7. the preparation method of the string selection line of 3 D memory array according to claim 6, wherein remove these the 3rd The method of the layer of hard mask material between opening includes：

The material layer filled up these the 3rd openings and cover the layer of hard mask material is formed in the dielectric substrate；

Patterning photoresist layer is formed in the material layer；

With the patterning photoresist layer as mask, the hard mask material between the part material layer and these the 3rd openings is removed The bed of material；And

Remove the remaining material layer.

8. the preparation method of the string selection line of 3 D memory array according to claim 7, wherein material layer includes Organic dielectric materials layer and Silicon-rich polymeric layer, organic dielectric materials layer fill up these the 3rd openings, the Silicon-rich polymeric layer The dielectric substrate is covered comprehensively.