CN104681405A - Acquisition method of electrically matched symmetric circuit - Google Patents
Acquisition method of electrically matched symmetric circuit Download PDFInfo
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- CN104681405A CN104681405A CN201310616533.8A CN201310616533A CN104681405A CN 104681405 A CN104681405 A CN 104681405A CN 201310616533 A CN201310616533 A CN 201310616533A CN 104681405 A CN104681405 A CN 104681405A
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Abstract
The invention provides two kinds of acquisition methods of an electrically matched symmetric circuit. The first method comprises the following steps: when performing laser thermal annealing on a wafer with a symmetric circuit, making a laser beam parallel to the wafer surface, and controlling the range of an included angle between the direction of the laser beam and the crystal orientation of the wafer to be 60-90 degrees. The second method comprises the following steps: when forming a gate oxide layer of a logic circuit area and a gate oxide layer of a peripheral circuit area, firstly, forming oxide layers with the same thickness on the wafer surfaces of the logic circuit area and the peripheral circuit area, and then covering the peripheral circuit area, removing the oxide layer of the logic circuit area by wet process, wherein in the process of removing by wet process, the range of an included angle between a flow direction of corrosive liquid and a symmetric axis of the symmetric circuit is 0-30 degrees. The above schemes can both improve the electrical mismatching of the symmetric circuit.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the acquisition methods of the symmetric circuit of electrically coupling.
Background technology
In semiconductor processing, some device need be arranged to symmetrical structure to complete some functions, and the circuit with the device composition of above-mentioned functions is symmetric circuit.
In prior art, due to the precision of manufacturing process, in making symmetric circuit technique, the performance realizing each device is identical more difficult, for these reasons, cause electrically not mating of the symmetric circuit of making, this makes symmetric circuit electrically uncontrollable in actual use.
For the problems referred to above, prior art generally adopts compensating circuit to improve above-mentioned electrical mismatch problem.But this can cause increasing of circuit devcie, failure rate increases.
In view of this, the invention provides the acquisition methods of the symmetric circuit of two kinds of new electrical couplings, from technological angle, the problems referred to above are improved.
Summary of the invention
The problem that the present invention solves improves the electrical mismatch problem of symmetric circuit.
For solving the problem, the invention provides the acquisition methods of the symmetric circuit that two kinds electrically mate, first method comprises:
Laser thermal anneal is carried out to the wafer with symmetric circuit, wherein, laser beam parallel wafer surface, and the angular range in the crystal orientation of the direction of laser beam and described wafer is 60 degree to 90 degree.
Alternatively, the angle in the direction of described laser beam and the crystal orientation of described wafer is 90 degree.
Alternatively, described symmetric circuit is positioned at the logic circuit area of wafer, and described wafer also has peripheral circuit region, and the transistor gate oxidated layer thickness of described peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area; Described acquisition methods also comprises: when forming the grid oxic horizon of the grid oxic horizon of logic circuit area and peripheral circuit region, the oxide layer of consistency of thickness is first formed at the crystal column surface of logic circuit area and peripheral circuit region, then described peripheral circuit region is hidden, wet method removes the described oxide layer of logic circuit area, in described wet method removal process, the angular range between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree to 30 degree.
Alternatively, in described wet method removal process, the angle between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree.
Alternatively, described symmetric circuit is binary channels D/A converting circuit or current mirror.
Alternatively, when described symmetric circuit is current mirror, described current mirror is many times of amplifications, arranges dummy argument between current source transistor and multiple current-copying transistor.
In addition, present invention also offers the acquisition methods of the another kind of electrically symmetric circuit of coupling, described symmetric circuit is positioned at the logic circuit area of wafer, described wafer also has peripheral circuit region, and the transistor gate oxidated layer thickness of described peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area; Described acquisition methods comprises: when forming the grid oxic horizon of the grid oxic horizon of logic circuit area and peripheral circuit region, the oxide layer of consistency of thickness is first formed at the crystal column surface of logic circuit area and peripheral circuit region, then described peripheral circuit region is hidden, wet method removes the described oxide layer of logic circuit area, in described wet method removal process, the angular range between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree to 30 degree.
Alternatively, in described wet method removal process, the angle between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree.
Alternatively, described symmetric circuit is binary channels D/A converting circuit or current mirror.
Alternatively, when described symmetric circuit is current mirror, described current mirror is many times of amplifications.
Compared with prior art, technical scheme of the present invention has the following advantages: 1) in transistor fabrication process, many places relate to thermal annealing, such as source, the activation of drain region Doped ions, release of metal interconnect structure thermal stress etc., research finds, the hot rate of heat transfer along the direction, crystal orientation of wafer (such as monocrystalline silicon or monocrystalline germanium) is greater than the rate of heat transfer along other direction, the present invention utilizes above-mentioned rule, when carrying out laser thermal anneal to the wafer with symmetric circuit, make laser beam parallel wafer surface, and the angular range controlling the direction of laser beam and the crystal orientation of described wafer is 60 degree to 90 degree, so, avoid above-mentioned heat diffusion vector component on wafer crystal orientation excessive, thus realize crystal column surface and be heated evenly, the each device of symmetric circuit is heated properly, performance obtains impartial lifting.
2) in possibility, the angle in the direction of described laser beam and the crystal orientation of described wafer is 90 degree, this kind of scheme makes above-mentioned heat diffusion vector component on wafer crystal orientation be 0, realize crystal column surface to be further heated evenly, thus each device of symmetric circuit is heated properly, performance obtains impartial lifting.
3) in possibility, be heated evenly except controlling crystal column surface, also provide a kind of scheme: particularly, a certain chip will realize certain function, generally except the logic circuit area at symmetric circuit place, also need to coordinate input/output circuitry, the region at above-mentioned imput output circuit place is peripheral circuit region, in general, the transistor of peripheral circuit region is high voltage transistor, thus, the thickness of grid oxide layer of the transistor of peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area, namely crystal column surface need form the grid oxic horizon (Dual gate oxide) of two kinds of thickness.The one formation method of the grid oxic horizon of above-mentioned two kinds of thickness is: the oxide layer first forming a layer thickness equalization at the crystal column surface of logic circuit area and peripheral circuit region, then the oxide layer of logic circuit area is removed, retain the oxide layer of peripheral circuit region, then, the oxide layer of a layer thickness equalization is formed again at the crystal column surface of logic circuit area and peripheral circuit region, so, oxide layer due to peripheral circuit region is the superposition of two-layer oxidated layer thickness, the thickness of the oxide layer that logic circuit area only has second time to be formed, thus, the above-mentioned grid oxic horizon defining logic circuit area and peripheral circuit region, wherein, the thickness of the grid oxic horizon of peripheral circuit region is larger.But, research finds, isolate owing to adopting fleet plough groove isolation structure (STI) between each transistor of logic circuit area, material in fleet plough groove isolation structure has been generally the oxide of insulating effect, thus when removing the oxide layer of logic circuit area, certain corrosion can be had to this fleet plough groove isolation structure, form groove; If when now the flow direction of corrosive liquid is the symmetry axis along vertical symmetry circuit, due to the existence of STI etch back trenches, compression can be applied for the formation of the wafer substrate of leaking to the wafer substrate for the formation of source of a transistor and another transistor, or compression is applied to the wafer substrate for the formation of source for the formation of the wafer substrate of leaking and another transistor of a transistor, after this causes two transistor to make, the source and drain unbalanced stress etc. of respective transistor.This programme utilizes above-mentioned rule, and in wet method removal process, the angular range between the flow direction of control corrosion rate liquid and the symmetry axis of described symmetric circuit is 0 degree to 30 degree.So, avoid the two transistor of symmetric circuit above-mentioned compression vector component on the symmetry axis direction of vertical symmetry circuit excessive, thus realize two transistor source, the drain region stress equalization of symmetric circuit, performance obtains impartial lifting.
4) in possibility, for 3) possibility, the angle between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree.So, the two transistor of symmetric circuit above-mentioned compression vector component on the symmetry axis direction of vertical symmetry circuit is made to be 0, make the two transistor source of symmetric circuit, drain region stress equalization further, thus the electric property realizing symmetric circuit obtains impartial lifting.
5) in possibility, above-mentioned symmetric circuit can be binary channels D/A converting circuit, also can be current mirror.
6) in possibility, for 5) current mirror in possibility, this current mirror is many times of amplifications.In other words, thermal anneal process or corrosive liquid process are carried out to three and above transistor simultaneously, be not limited to carry out above-mentioned process to two transistors simultaneously.In addition, arrange dummy argument between current source transistor and multiple current-copying transistor, make source transistor, current-copying transistor in thermal annealing process, impartial degree is by the impact of other transistor of surrounding.
7) above-mentioned 3) possibility is used alone, and also can play and make the electric property of symmetric circuit obtain the impartial effect promoted.
Accompanying drawing explanation
Fig. 1 is the apparatus structure schematic diagram in the acquisition methods of the symmetric circuit of the electrical coupling that one embodiment of the invention provides;
Fig. 2 is for the activation of the source of binary channels D/A converting circuit, drain region Doped ions, adopts the experiment results figure that Fig. 1 shown device carries out;
Fig. 3 is the structural representation of another kind of symmetric circuit;
Fig. 4 to Fig. 6 is the schematic diagram of the acquisition methods of the symmetric circuit of the electrical coupling that another embodiment of the present invention provides;
Fig. 7 is for binary channels D/A converting circuit, the experiment results figure that the acquisition methods of the symmetric circuit of the electrical coupling adopting another embodiment to provide carries out.
Embodiment
In transistor fabrication process, many places relate to thermal annealing, such as source, the activation of drain region Doped ions, release of metal interconnect structure thermal stress etc., research finds, the hot rate of heat transfer along the direction, crystal orientation of wafer (such as monocrystalline silicon or monocrystalline germanium) is greater than the rate of heat transfer along other direction, the present invention utilizes above-mentioned rule, when carrying out laser thermal anneal to the wafer with symmetric circuit, make laser beam parallel wafer surface, and the angular range controlling the direction of laser beam and the crystal orientation of described wafer is 60 degree to 90 degree, so, avoid above-mentioned heat diffusion vector component on wafer crystal orientation excessive, thus realize crystal column surface and be heated evenly, the each device of symmetric circuit is heated properly, performance obtains impartial lifting.
In addition, a certain chip will realize certain function, generally except the logic circuit area at symmetric circuit place, also need to coordinate input/output circuitry, the region at above-mentioned imput output circuit place is peripheral circuit region, in general, the transistor of peripheral circuit region is high voltage transistor, thus, the thickness of grid oxide layer of the transistor of peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area, and namely crystal column surface need form the grid oxic horizon (Dual gate oxide) of two kinds of thickness.The one formation method of the grid oxic horizon of above-mentioned two kinds of thickness is: the oxide layer first forming a layer thickness equalization at the crystal column surface of logic circuit area and peripheral circuit region, then the oxide layer of logic circuit area is removed, retain the oxide layer of peripheral circuit region, then, the oxide layer of a layer thickness equalization is formed again at the crystal column surface of logic circuit area and peripheral circuit region, so, oxide layer due to peripheral circuit region is the superposition of two-layer oxidated layer thickness, the thickness of the oxide layer that logic circuit area only has second time to be formed, thus, the above-mentioned grid oxic horizon defining logic circuit area and peripheral circuit region, wherein, the thickness of the grid oxic horizon of peripheral circuit region is larger.But, research finds, isolate owing to adopting fleet plough groove isolation structure (STI) between each transistor of logic circuit area, material in fleet plough groove isolation structure has been generally the oxide of insulating effect, thus when removing the oxide layer of logic circuit area, certain corrosion can be had to this fleet plough groove isolation structure, form groove; If when now corrosive liquid flows to along the symmetry axis of vertical symmetry circuit, due to the existence of STI etch back trenches, compression can be applied for the formation of the wafer substrate of leaking to the wafer substrate for the formation of source of a transistor and another transistor, or compression is applied to the wafer substrate for the formation of source for the formation of the wafer substrate of leaking and another transistor of a transistor, after this causes two transistor to make, the source and drain unbalanced stress etc. of respective transistor.This programme utilizes above-mentioned rule, and in wet method removal process, the angular range between the flow direction of control corrosion rate liquid and the symmetry axis of described symmetric circuit is 0 degree to 30 degree.So, avoid the two transistor of symmetric circuit above-mentioned compression vector component on the symmetry axis direction of vertical symmetry circuit excessive, thus realize two transistor source, the drain region stress equalization of symmetric circuit, performance obtains impartial lifting.
Above-mentioned two kinds of methods can be used alone, and also can use simultaneously, all can improve the electrical matching performance of symmetric circuit.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Figure 1 shows that the apparatus structure schematic diagram in the acquisition methods of the symmetric circuit of the electrical coupling that an embodiment provides.With reference to shown in Fig. 1, acquisition methods comprises: carry out laser thermal anneal to the wafer 1 with symmetric circuit, wherein, and laser beam 2 parallel wafer 1 surface, and the angle α scope in the crystal orientation 11 of the direction of laser beam 2 and described wafer 1 is 60 degree to 90 degree.
The electrical matching principle that above-mentioned laser thermal annealing method can improve symmetric circuit is as follows: heat is along wafer 1(such as monocrystalline silicon or monocrystalline germanium) the rate of heat transfer in direction, crystal orientation 11 be greater than rate of heat transfer along other direction, utilize above-mentioned rule, when carrying out laser thermal anneal to the wafer 1 with symmetric circuit, make laser beam 2 parallel wafer surface, and the angle α in the control direction of laser beam 2 and the crystal orientation 11 of described wafer 1 is more close to 90 degree, above-mentioned heat diffusion vector component on wafer crystal orientation more can be avoided excessive, heat major part or all along the direction of diffusion rate equalization, thus crystal column surface is heated substantially even, thus each device of symmetric circuit is heated properly, electric property can obtain impartial lifting.
Particularly, the symmetric circuit in above-mentioned wafer 1 is binary channels D/A converting circuit, and such as binary channels is respectively I passage and Q passage, and two passages have common area.
Above-mentioned laser thermal anneal can be the activation of source, drain region Doped ions, or the release of metal interconnect structure thermal stress etc.
Fig. 2 is for the activation of the source of binary channels D/A converting circuit, drain region Doped ions, the experiment results figure carried out.Wherein, the electrical matching test method of binary channels D/A converting circuit is: apply same voltage to I passage with Q passage, tests two passages output current separately.The computational methods of electrical matching rate are: 1-(I passage output current-Q passage output current)/Q passage output current.Can find out, along with the angle α in the direction of laser beam 2 and the crystal orientation 11 of described wafer 1 increases gradually, the electrical matching performance of binary channels D/A converting circuit gets a promotion gradually, reaches peak at 90 degree.Wherein, α scope is between 60 degree to 90 degree, and relative to other angle, two channel electrical Performance Match degree are higher, all can be used as the laser thermal anneal optimized angle improving symmetric circuit.
Except the binary channels D/A converting circuit shown in Fig. 1, symmetric circuit can also current mirror as shown in Figure 3.This current mirror is generally many times of amplifications, shows a current source transistor 31, four current-copying transistor 32 in Fig. 3, is thus 4 times of amplifications.In other words, three and above transistor are carried out to the laser thermal anneal process of such scheme simultaneously, be not limited to carry out above-mentioned process to two transistors simultaneously.In addition, between current source transistor 31 and multiple current-copying transistor 32, dummy argument 33(dummy can also be set), make source transistor 31, current-copying transistor 32 in thermal annealing process, impartial degree is by the impact of other transistor of surrounding.
The setting position of above-mentioned dummy argument 33 preferably makes the distance between adjacent source transistor 31, dummy argument 33, each current-copying transistor 32 equal.
In implementation process, the distance of the laser beam 2 preferred distance wafer on parallel wafer 1 surface is 1-1.4 rice.Above-mentioned distance, in conjunction with the Angle ambiguity of laser beam 2, can promote the electrical matching performance of symmetric circuit further.
Except above-mentioned laser heat treatment method, the present invention also provides another scheme, to improve the electrical matching performance of symmetric circuit.
Particularly, vertical view shown in sectional view as shown in Figure 4 and Fig. 5, described symmetric circuit is positioned at the logic circuit area I of wafer 1, described wafer 1 also has peripheral circuit region II, and the transistor gate oxidated layer thickness of described peripheral circuit region II is greater than the thickness of grid oxide layer of the transistor of logic circuit area I; Described acquisition methods comprises: when forming the grid oxic horizon of the grid oxic horizon of logic circuit area I and peripheral circuit region II, first form the oxide layer 4 of consistency of thickness in logic circuit area I and wafer 1 surface of peripheral circuit region II, then described peripheral circuit region II is hidden, wet method removes the described oxide layer 4 of logic circuit area I, in described wet method removal process, the angle β scope flowed between 5 and the symmetry axis 6 of described symmetric circuit of corrosive liquid is 0 degree to 30 degree.
Above-mentioned control corrosion rate liquid flows to 5, and to improve the electrical matching principle of symmetric circuit as follows: a certain chip will realize certain function, generally except the logic circuit area I at symmetric circuit place, also need to coordinate input/output circuitry, the region at above-mentioned imput output circuit place is peripheral circuit region II, in general, the transistor of peripheral circuit region II is high voltage transistor, thus, the thickness of grid oxide layer of the transistor of peripheral circuit region II is greater than the thickness of grid oxide layer of the transistor of logic circuit area I, and namely wafer 1 surface need form the grid oxic horizon of two kinds of thickness.The one formation method of the grid oxic horizon of above-mentioned two kinds of thickness is: first form the oxide layer 4 of a layer thickness equalization in logic circuit area I and the crystal column surface of peripheral circuit region II; Then the oxide layer 4 of logic circuit area I is removed, retain the oxide layer 4 of peripheral circuit region II, above-mentioned removal step is protected by hiding photoresist etc. in the oxide layer 4 of peripheral circuit region II, then sprays into corrosive liquid (such as HF acid) wet etching on wafer 1 surface and realizes; Afterwards, the oxide layer (not shown) of a layer thickness equalization is formed again in logic circuit area I and wafer 1 surface of peripheral circuit region II, so, oxide layer due to peripheral circuit region II is the superposition of two-layer oxidated layer thickness, the thickness of the oxide layer that logic circuit area I only has second time to be formed, thus, the above-mentioned grid oxic horizon defining logic circuit area I and peripheral circuit region II, wherein, the thickness of the grid oxic horizon of peripheral circuit region II is larger.But, the transistor of logic circuit area I is symmetrical set to form symmetric circuit, namely at least part of device in symmetry axis both sides of symmetric circuit is the identical transistor of structure, thus the source electrode of a transistor is adjacent with the source electrode of another transistor, or the drain electrode of a transistor is adjacent with the drain electrode of another transistor.
Research finds, owing to adopting fleet plough groove isolation structure 7(STI between each transistor of logic circuit area I) isolation, material in fleet plough groove isolation structure 7 has been generally the oxide of insulating effect, thus when removing the oxide layer 4 of logic circuit area I, certain corrosion can be had to this fleet plough groove isolation structure I, form groove 71, as shown in Figure 6; If now corrosive liquid flow to 5 for during along the symmetry axis 6 of vertical symmetry circuit, due to the existence of STI etch back trenches 71, also can be able to be drain electrode for the formation of source electrode 12(to a transistor) wafer 1 substrate and another transistor also can be source electrode for the formation of the 13(that drains) wafer 1 undercoat add compression; When flowing to 5 and being reverse, can to a transistor also can for source electrode for the formation of drain electrode 14() wafer 1 substrate and another transistor also can be drain for the formation of source electrode 15() wafer 1 undercoat add compression, after this causes two transistor to make, the source-drain electrode unbalanced stress etc. of respective transistor.This programme utilizes above-mentioned rule, in wet method removal process, the angle β flowed between 5 and the symmetry axis 6 of described symmetric circuit of control corrosion rate liquid is little as far as possible, with the two transistor source reducing symmetric circuit as far as possible, the compression vector component that drains on symmetry axis 6 direction of vertical symmetry circuit, thus realize two transistor source, the drain stress equalization of symmetric circuit, make its performance obtain impartial lifting.
For checking such scheme, take symmetric circuit as binary channels D/A converting circuit be example, inventor has made the parallel symmetric circuit in 1700 above-mentioned symmetry axis directions on a wafer, flowing to of control corrosion rate liquid 5 is respectively 45 degree with the symmetry axis 6 angle β of symmetric circuit, 90 degree, 0 degree, random four kinds of situations, electrical matching performance test experiments result be respectively along Fig. 7 from left to right order shown in.Wherein, by electrical matching performance degree from good to difference gray value step-down (white is 255, and black is 0) gradually, namely color deepens gradually.Wherein, the electrical matching test method of binary channels D/A converting circuit is: apply same voltage to I passage with Q passage, tests two passages output current separately.The computational methods of electrical matching rate are: 1-(I passage output current-Q passage output current)/Q passage output current.Electrical matching rate is higher, and electrical matching performance is better.Can find out, what adopt corrosive liquid flows to 5 when being 0 degree of process symmetric circuit with the symmetry axis 6 angle β of symmetric circuit, and the electrical matching performance of the result of adding up is best, and undesirable symmetric circuit is minimum.Experiment finds, in specific implementation process, the scope of above-mentioned angle β is 0 degree to 30 degree, substantially can meet the electrical matching performance requirement of symmetric circuit.
Be understandable that, the method that above-mentioned control corrosion rate liquid flows to also may be used for this symmetric circuit of current mirror, and when described current mirror is many times of amplifications, current source transistor and each current-copying transistor are symmetrically.Because current source transistor is parallel with the symmetry axis that each current-copying transistor is formed, thus can carry out corrosive liquid process to three and above transistor simultaneously, be not limited to carry out above-mentioned process to two transistors simultaneously.
In an embodiment, be combined the corner dimension between the grid oxic horizon of the scheme process symmetric circuit that above-mentioned control corrosion rate liquid flows to and the beam direction controlled in laser thermal anneal and wafer crystal orientation.Above-mentioned two kinds of methods, without sequencing, can need to select according to technique.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. the acquisition methods of the symmetric circuit electrically mated, it is characterized in that, comprising: laser thermal anneal is carried out to the wafer with symmetric circuit, wherein, laser beam parallel wafer surface, and the angular range in the crystal orientation of the direction of laser beam and described wafer is 60 degree to 90 degree.
2. the acquisition methods of the symmetric circuit of electrical coupling according to claim 1, is characterized in that, the angle in the direction of described laser beam and the crystal orientation of described wafer is 90 degree.
3. the acquisition methods of the symmetric circuit of electrical coupling according to claim 1, it is characterized in that, described symmetric circuit is positioned at the logic circuit area of wafer, described wafer also has peripheral circuit region, and the transistor gate oxidated layer thickness of described peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area; Described acquisition methods also comprises: when forming the grid oxic horizon of the grid oxic horizon of logic circuit area and peripheral circuit region, the oxide layer of consistency of thickness is first formed at the crystal column surface of logic circuit area and peripheral circuit region, then described peripheral circuit region is hidden, wet method removes the described oxide layer of logic circuit area, in described wet method removal process, the angular range between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree to 30 degree.
4. the acquisition methods of the symmetric circuit of electrical coupling according to claim 3, is characterized in that, in described wet method removal process, the angle between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree.
5. the acquisition methods of the symmetric circuit of electrical coupling according to claim 1, is characterized in that, described symmetric circuit is binary channels D/A converting circuit or current mirror.
6. the acquisition methods of the symmetric circuit of electrical coupling according to claim 5, is characterized in that, when described symmetric circuit is current mirror, described current mirror is many times of amplifications, arranges dummy argument between current source transistor and multiple current-copying transistor.
7. the acquisition methods of the symmetric circuit electrically mated, it is characterized in that, described symmetric circuit is positioned at the logic circuit area of wafer, described wafer also has peripheral circuit region, and the transistor gate oxidated layer thickness of described peripheral circuit region is greater than the thickness of grid oxide layer of the transistor of logic circuit area; Described acquisition methods comprises: when forming the grid oxic horizon of the grid oxic horizon of logic circuit area and peripheral circuit region, the oxide layer of consistency of thickness is first formed at the crystal column surface of logic circuit area and peripheral circuit region, then described peripheral circuit region is hidden, wet method removes the described oxide layer of logic circuit area, in described wet method removal process, the angular range between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree to 30 degree.
8. the acquisition methods of the symmetric circuit of electrical coupling according to claim 7, is characterized in that, in described wet method removal process, the angle between the flow direction of corrosive liquid and the symmetry axis of described symmetric circuit is 0 degree.
9. the acquisition methods of the symmetric circuit of the electrical coupling according to claim 7 or 8, is characterized in that, described symmetric circuit is binary channels D/A converting circuit or current mirror.
10. the acquisition methods of the symmetric circuit of electrical coupling according to claim 9, is characterized in that, when described symmetric circuit is current mirror, described current mirror is many times of amplifications.
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| CN1267917A (en) * | 1994-12-15 | 2000-09-27 | 株式会社半导体能源研究所 | Semi-conductor device and its producing method |
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