CN104679565A - Burning-writing system and burning-writing method for flash memory in optical communication equipment production - Google Patents
Burning-writing system and burning-writing method for flash memory in optical communication equipment production Download PDFInfo
- Publication number
- CN104679565A CN104679565A CN201510109917.XA CN201510109917A CN104679565A CN 104679565 A CN104679565 A CN 104679565A CN 201510109917 A CN201510109917 A CN 201510109917A CN 104679565 A CN104679565 A CN 104679565A
- Authority
- CN
- China
- Prior art keywords
- port
- debugging
- register
- flash memory
- string line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a burning-writing system and a burning-writing method for a flash memory in optical communication equipment production, and relates to the technical field of optical communication equipment production. The system comprises a plate management unit locking plate and ARM equipment, wherein the ARM equipment comprises a serial line debugging interface and an ARM chip; the plate management unit locking plate is connected with the serial line debugging interface through a serial line; the ARM chip comprises a high-performance bus access interface, an inner core, a high-performance internal interconnection bus and a memory, wherein the high-performance bus access interface is connected with the serial line debugging interface through a debugging access interface bus; the high-performance internal interconnection bus is connected with the high-performance bus access interface, the inner core and the memory respectively. According to the burning-writing system and the burning-writing system disclosed by the invention, the equipment is reduced, the production cost is reduced, the production efficiency is improved, and the problem that a loader is damaged under error operations or simulation is solved.
Description
Technical field
The present invention relates to optical communication equipment production technical field, is specifically the programming system and method for flash memory during a kind of optical communication equipment is produced.
Background technology
At present, all ARM (Advanced RISC Machines) chip application software program FLASH (flash memory) programming of optical communication manufacturing enterprise all adopts PC and emulation downloader (such as JLINK emulates downloader) to carry out, concrete mode is for insert JTAG (Joint Test Action Group by downloading wire, joint test working group) winding displacement mouth, carries out the program burn writing of flash memory in conjunction with Software tool (such as J-FLASH ARM Software tool).
But, due to traditional programming operation to PC and emulation downloader demand comparatively large, cause cost higher; And during ARM chip application program upgrade process, need the artificial emulation of plug repeatedly downloader, have a strong impact on work efficiency; In addition, when tester carries out the operation of flashburn tools by PC, man-machine interaction is more and without foolproof function, causes the problem easily occurring that maloperation and emulation downloader damage.
Summary of the invention
For the defect existed in prior art, in the object of the present invention is to provide a kind of optical communication equipment to produce, the programming system and method for flash memory, present invention saves equipment and reduces production cost; Improve production efficiency; Solve the problem of maloperation and the damage of emulation downloader.
For reaching above object, the technical scheme that the present invention takes is: the programming system of flash memory in a kind of optical communication equipment production, comprise board management unit buckle and ARM equipment, described ARM equipment comprises string line debugging interface and ARM chip, and described board management unit buckle is connected with string line debugging interface by string line; Described ARM chip comprises high performance bus access interface, kernel, high-performance interconnected bus and storer, wherein, described high performance bus access interface is connected with string line debugging interface by debugging access interface bus, and described high-performance interconnected bus is connected with high performance bus access interface, kernel and storer respectively.
On the basis of technique scheme, described string line debugging interface comprises string line clock port, string line data input output ports, reset pin; Described board management unit buckle comprises the first I/O port, the second I/O port, the 3rd I/O port; Described string line clock port is connected with the first I/O port, and string line data input output ports is connected with the second I/O port, and reset pin is connected with the 3rd I/O port.
On the basis of technique scheme, described board management unit buckle also comprises 3V3 pin and a GND pin, and ARM equipment also comprises VCC pin and the 2nd GND pin; Wherein, described 3V3 pin is connected with VCC pin, and a GND pin is connected with the 2nd GND pin.
On the basis of technique scheme, described high performance bus access interface comprises control and status word register, for control data direction of transfer, transmit size and transmission type; Transport address register, for the transfer address of director data; Data read/write register, for depositing or store by the data transmitted.
On the basis of technique scheme, described ARM chip also comprises authentication code register, for providing the identification information about string line debugging interface; Stop register, stop for forcing DAP and remove mistake and adhesive tape flag condition; Control/status register, for providing the control of string line debugging interface and the status information about string line debugging interface; Diagnosis debugging management status register, for providing security of system, Flash memory erase starts, acknowledgement state information; Diagnosis debugging management control register, for providing system debug request, controlling debugging and forbidding, controlling Flash memory erase; Debugging stops controlling and status register, and for providing the information about ARM chip status, enable kernel tailoring, realizes ARM chip and stop and single-step operation; Debugging is abnormal and monitor control register, controls for debugging monitoring.
A kind of programming method of flash memory during the present invention also provides optical communication equipment based on said system to produce, described ARM equipment comprises authentication code register, termination register, control/status register, diagnosis debugging management status register, diagnosis debugging management control register; The method comprises the following steps: each I/O port of step S1. initialization board management unit buckle; Step S2. carries out ARM chip reset, and ARM chip is become SWD pattern by JTAG patten transformation; Step S3. is by the authentication code of authentication code register read device; Step S4. arranges the clear error flag stopping register; Step S5. is by arranging control/status register, and enabled systems powers on and asks and the debugging request of powering on; According to diagnosis debugging management status register, step S6. judges whether ARM chip flash memory is encrypted, and if so, then goes to step S7; If not, then S8 is gone to step; Step S7. performs bulk erase operation by diagnosis debugging management control register, carries out the decryption processing of ARM chip; Step S8. passes through the DEBUG pattern that debugging stops control and the enable ARM chip of status register, then by debugging abnormal and monitoring control register calling ARM chip, makes it process halted state; Step S9. performs the flash memory initialization of ARM chip, carries out wiping and programming function, completes the ARM chip flash memory programming of specified application file.
On the basis of technique scheme, described string line debugging interface comprises string line clock port, string line data input output ports, reset pin; Described board management unit buckle comprises the first I/O port, the second I/O port, the 3rd I/O port; Described string line clock port is connected with the first I/O port, and string line data input output ports is connected with the second I/O port, and reset pin is connected with the 3rd I/O port.
On the basis of technique scheme, in step S1, each I/O port of initialization board management unit buckle is specially initialization first I/O port and exports, and the 3rd I/O port exports, and the second I/O port switches as data input and output.
On the basis of technique scheme, in step S2, carry out ARM chip reset by the 3rd I/O port; Send default value sequence by the first I/O port, the second I/O port, ARM chip is become SWD pattern by JTAG patten transformation.
Beneficial effect of the present invention is:
1, BMU (board management unit) buckle in the present invention is connected with the string line debugging interface of ARM equipment by string line, therefore emulator is downloaded without the need to using, namely by I/O port simulation SWD (the Serial Wire Debug of BMU buckle, string line debug protocol) agreement, realize programming ARM chip flash memory being carried out to application program, saved equipment and reduced production cost.
2, emulator is downloaded without the need to using in the present invention, therefore when ARM chip application program upgrade process, do not need the artificial emulation of plug repeatedly downloader, avoid the damage of emulation downloader, do not need the programming software of manual operation configure dedicated, namely saved production cost and turn improved production efficiency.
3, downloading emulator without the need to using in the present invention, when therefore tester carries out programming operation, there is not man-machine interaction, solve the problem of maloperation and the damage of emulation downloader.
Accompanying drawing explanation
Fig. 1 is the signal wiring figure of the programming system of flash memory during optical communication equipment of the present invention is produced;
Fig. 2 is the theory diagram of the programming system of flash memory during optical communication equipment of the present invention is produced;
Fig. 3 is the programming method flow diagram of flash memory during optical communication equipment of the present invention is produced.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Shown in Figure 1, the programming system of flash memory in a kind of optical communication equipment production, comprise BMU buckle and ARM equipment, described ARM equipment comprises SW-DP (string line debugging interface) and ARM chip, and described BMU buckle is connected with string line debugging interface by SW line (string line); Described string line debugging interface comprises SWD_TCK (string line clock port), SWD_DIO (string line data input output ports), NRST (reset pin); Described BMU buckle comprises the first I/O port, the second I/O port, the 3rd I/O port; Described string line clock port is connected with the first I/O port, and string line data input output ports is connected with the second I/O port, and reset pin is connected with the 3rd I/O port.Preferably, described BMU buckle also comprises 3V3 pin and a GND pin, and ARM equipment also comprises VCC pin and the 2nd GND pin; Wherein, described 3V3 pin is connected with VCC pin, and a GND pin is connected with the 2nd GND pin.
Shown in Fig. 1 and Fig. 2, described ARM chip comprises AHB-AP (high performance bus access interface), kernel, high-performance interconnected bus (AHB) and storer, wherein, described high performance bus access interface is connected with string line debugging interface by DAP bus (debugging access interface bus), and described high-performance interconnected bus is connected with high performance bus access interface, kernel and storer respectively.
Described high performance bus access interface comprises CSW register (control and status word register), for control data direction of transfer, transmit size and transmission type; TAR register (transport address register), for the transfer address of director data; DRW register (data read/write register), for depositing or store by the data transmitted.Because the storer of RAM chip is not within the scope of memory address, outside BMU buckle and the kernel of ARM chip directly can not access the storer of ARM chip, can only pass through high-performance interconnected bus accessing memory.And during the storer of BMU buckle access ARM chip, external signal is converted to DAP bus signals by string line, again through high performance bus access interface, by register transfer instruction address, transport address, the data that data read/write register transfer will be read and write, after the direction (read/write) that control and status word register transmission will need, size of data and data type, debugging access interface bus signals is converted to the data transmission in high-performance interconnected bus, visited the storer of ARM chip by high-performance interconnected bus.
Described ARM chip also comprises IDCODE register (authentication code register), for providing the identification information about string line debugging interface; ABORT register (termination register), stops for forcing DAP and removes mistake and adhesive tape flag condition; CTRL/STAT register (control/status register), for providing the control of string line debugging interface and the status information about string line debugging interface; MDM-AP Status register register (diagnosis debugging management status register), for providing security of system, Flash memory erase starts, acknowledgement state information; MDM-AP Control Register register (diagnosis debugging management control register), for providing system debug request, controlling debugging and forbidding, controlling Flash memory erase; DHCSR register (debugging stops controlling and status register), for providing the information about ARM chip status, enable kernel tailoring, realizes ARM chip and stops and single-step operation; DEMCR register (debugging is abnormal and monitor control register), controls for debugging monitoring.
Shown in Figure 3, based on the programming method of flash memory in the optical communication equipment production of said system, comprise the following steps:
Each I/O port of step S1. initialization BMU buckle; Concrete, each I/O port of initialization BMU buckle is specially initialization first I/O port and exports, and the 3rd I/O port exports, and the second I/O port switches as data input and output.
Step S2. carries out ARM chip reset, and ARM chip is become SWD pattern by JTAG patten transformation; Concrete, carry out ARM chip reset by the 3rd I/O port; Send default value sequence (0xE79E sequence) by the first I/O port, the second I/O port, ARM chip is become SWD pattern by JTAG patten transformation.
Step S3. is by the authentication code of authentication code register read device.
Step S4. arranges the clear error flag stopping register.
Step S5. is by arranging control/status register, and enabled systems powers on and asks and the debugging request of powering on.
According to diagnosis debugging management status register, step S6. judges whether ARM chip flash memory is encrypted, and if so, then goes to step S7; If not, then S8 is gone to step.
Step S7. performs bulk erase operation by diagnosis debugging management control register, carries out the decryption processing of ARM chip.
Step S8. passes through the DEBUG pattern that debugging stops control and the enable ARM chip of status register, then by debugging abnormal and monitoring control register calling ARM chip, makes it process halted state.
Step S9. performs the flash memory initialization of ARM chip, carries out wiping and programming function, completes the ARM chip flash memory programming of specified application file.
The present invention is not limited to above-mentioned embodiment, and for those skilled in the art, under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications are also considered as within protection scope of the present invention.The content be not described in detail in this instructions belongs to the known prior art of professional and technical personnel in the field.
Claims (9)
1. an optical communication equipment produce in the programming system of flash memory, comprise board management unit buckle and ARM equipment, it is characterized in that: described ARM equipment comprises string line debugging interface and ARM chip, described board management unit buckle is connected with string line debugging interface by string line;
Described ARM chip comprises high performance bus access interface, kernel, high-performance interconnected bus and storer, wherein, described high performance bus access interface is connected with string line debugging interface by debugging access interface bus, and described high-performance interconnected bus is connected with high performance bus access interface, kernel and storer respectively.
2. optical communication equipment as claimed in claim 1 produce in the programming system of flash memory, it is characterized in that: described string line debugging interface comprises string line clock port, string line data input output ports, reset pin; Described board management unit buckle comprises the first I/O port, the second I/O port, the 3rd I/O port; Described string line clock port is connected with the first I/O port, and string line data input output ports is connected with the second I/O port, and reset pin is connected with the 3rd I/O port.
3. optical communication equipment as claimed in claim 2 produce in the programming system of flash memory, it is characterized in that: described board management unit buckle also comprises 3V3 pin and a GND pin, ARM equipment also comprises VCC pin and the 2nd GND pin; Wherein, described 3V3 pin is connected with VCC pin, and a GND pin is connected with the 2nd GND pin.
4. optical communication equipment as claimed in claim 1 produce in the programming system of flash memory, it is characterized in that: described high performance bus access interface comprises
Control and status word register, for control data direction of transfer, transmit size and transmission type;
Transport address register, for the transfer address of director data;
Data read/write register, for depositing or store by the data transmitted.
5. optical communication equipment as claimed in claim 1 produce in the programming system of flash memory, it is characterized in that: described ARM chip also comprises
Authentication code register, for providing the identification information about string line debugging interface;
Stop register, stop for forcing DAP and remove mistake and adhesive tape flag condition;
Control/status register, for providing the control of string line debugging interface and the status information about string line debugging interface;
Diagnosis debugging management status register, for providing security of system, Flash memory erase starts, acknowledgement state information;
Diagnosis debugging management control register, for providing system debug request, controlling debugging and forbidding, controlling Flash memory erase;
Debugging stops controlling and status register, and for providing the information about ARM chip status, enable kernel tailoring, realizes ARM chip and stop and single-step operation;
Debugging is abnormal and monitor control register, controls for debugging monitoring.
6. based on the programming method of flash memory in the optical communication equipment production of system described in claim 1, it is characterized in that, described ARM equipment comprises authentication code register, termination register, control/status register, diagnosis debugging management status register, diagnosis debugging management control register; The method comprises the following steps:
Each I/O port of step S1. initialization board management unit buckle;
Step S2. carries out ARM chip reset, and ARM chip is become SWD pattern by JTAG patten transformation;
Step S3. is by the authentication code of authentication code register read device;
Step S4. arranges the clear error flag stopping register;
Step S5. is by arranging control/status register, and enabled systems powers on and asks and the debugging request of powering on;
According to diagnosis debugging management status register, step S6. judges whether ARM chip flash memory is encrypted, and if so, then goes to step S7; If not, then S8 is gone to step;
Step S7. performs bulk erase operation by diagnosis debugging management control register, carries out the decryption processing of ARM chip;
Step S8. passes through the DEBUG pattern that debugging stops control and the enable ARM chip of status register, then by debugging abnormal and monitoring control register calling ARM chip, makes it process halted state;
Step S9. performs the flash memory initialization of ARM chip, carries out wiping and programming function, completes the ARM chip flash memory programming of specified application file.
7. optical communication equipment as claimed in claim 6 produce in the programming method of flash memory, it is characterized in that: described string line debugging interface comprises string line clock port, string line data input output ports, reset pin; Described board management unit buckle comprises the first I/O port, the second I/O port, the 3rd I/O port; Described string line clock port is connected with the first I/O port, and string line data input output ports is connected with the second I/O port, and reset pin is connected with the 3rd I/O port.
8. optical communication equipment as claimed in claim 7 produce in the programming method of flash memory, it is characterized in that: in step S1, each I/O port of initialization board management unit buckle is specially initialization first I/O port and exports, and the 3rd I/O port exports, and the second I/O port switches as data input and output.
9. optical communication equipment as claimed in claim 7 produce in the programming method of flash memory, it is characterized in that: in step S2, carry out ARM chip reset by the 3rd I/O port; Send default value sequence by the first I/O port, the second I/O port, ARM chip is become SWD pattern by JTAG patten transformation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510109917.XA CN104679565B (en) | 2015-03-12 | 2015-03-12 | The programming system and method for flash memory in a kind of optical communication equipment production |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510109917.XA CN104679565B (en) | 2015-03-12 | 2015-03-12 | The programming system and method for flash memory in a kind of optical communication equipment production |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104679565A true CN104679565A (en) | 2015-06-03 |
| CN104679565B CN104679565B (en) | 2018-01-02 |
Family
ID=53314662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510109917.XA Active CN104679565B (en) | 2015-03-12 | 2015-03-12 | The programming system and method for flash memory in a kind of optical communication equipment production |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104679565B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040049617A1 (en) * | 2002-09-05 | 2004-03-11 | Integrated Circuit Solution Inc. | Method of firmware update by USB interface |
| TWM328039U (en) * | 2007-08-16 | 2008-03-01 | Inventec Appliances Corp | Flash memory burner |
| CN103677885A (en) * | 2012-09-21 | 2014-03-26 | 厦门雅迅网络股份有限公司 | ARM FLASH simple program programming method |
| CN103838585A (en) * | 2012-11-20 | 2014-06-04 | 广州市暨华医疗器械有限公司 | Method for achieving automatic recording of ARM9 embedded system based on SD card |
| CN203982359U (en) * | 2014-06-27 | 2014-12-03 | 国家电网公司 | Can connect the FLASH program burn writing device of multiple modules simultaneously |
-
2015
- 2015-03-12 CN CN201510109917.XA patent/CN104679565B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040049617A1 (en) * | 2002-09-05 | 2004-03-11 | Integrated Circuit Solution Inc. | Method of firmware update by USB interface |
| TWM328039U (en) * | 2007-08-16 | 2008-03-01 | Inventec Appliances Corp | Flash memory burner |
| CN103677885A (en) * | 2012-09-21 | 2014-03-26 | 厦门雅迅网络股份有限公司 | ARM FLASH simple program programming method |
| CN103838585A (en) * | 2012-11-20 | 2014-06-04 | 广州市暨华医疗器械有限公司 | Method for achieving automatic recording of ARM9 embedded system based on SD card |
| CN203982359U (en) * | 2014-06-27 | 2014-12-03 | 国家电网公司 | Can connect the FLASH program burn writing device of multiple modules simultaneously |
Non-Patent Citations (2)
| Title |
|---|
| 连赟等: "基于片外SPI FLASH的OTP烧录器的设计与实现", 《杭州电子科技大学学报》 * |
| 邓启辉: "用JTAG烧写Flash的方法", 《兵工自动化》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104679565B (en) | 2018-01-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103559053B (en) | Board system and FPGA (Field Programmable Logic Array) online update method of communication interface cards | |
| CN104809014B (en) | A kind of system remote radio upgrade method | |
| CN101454746B (en) | Method for communication with a multi-function memory card | |
| CN107704346B (en) | SOC chip debugging method and system | |
| US7225357B2 (en) | SDIO card development system | |
| CN105279127B (en) | A kind of FPGA program downloading systems and method based on PCI or PCIe buses | |
| CN107992390B (en) | Chip debugging method based on-chip bus | |
| CN105808396A (en) | Chip debugging device, debugging method and SOC (System of Chip) chip system | |
| CN105446657B (en) | A kind of method for monitoring RAID card | |
| CN107656882A (en) | A kind of USB controller verification method, system and equipment | |
| CN101211266A (en) | FPGA automatic downloading and on-line upgrading process | |
| CN103699112B (en) | Based on avionics Autonomous test Authentication devices and the verification method thereof of I/O signal fault simulation | |
| CN105095040B (en) | A kind of chip adjustment method and device | |
| CN104679559A (en) | Single chip microcomputer on-line programming method | |
| CN102520961B (en) | Off-chip online programmable SOC (system on a chip) and control method for same | |
| CN105159731A (en) | Field programmable gate array (FPGA) configuration file remote upgrading device | |
| CN107885517A (en) | Embedded system handles device program loaded circuit | |
| CN107124358A (en) | A kind of 4G PROFIBUS embedded system gateway devices based on FPGA | |
| CN109582341A (en) | A kind of host system and its programing change method of On-board System of Cab Signal equipment | |
| CN201374062Y (en) | FPGA on-line configuration circuit | |
| US20190271740A1 (en) | Non-intrusive on-chip debugger with remote protocol support | |
| CN102253875A (en) | Field programmable gate array (FPGA) logic module debugging and data acquisition method based on PicoBlaze embedded soft core processor | |
| CN101814054B (en) | Instruction tracing controller for debugging microcontroller | |
| CN103365815B (en) | The SD memory card interface that under support SD pattern, IP realizes | |
| CN104679565A (en) | Burning-writing system and burning-writing method for flash memory in optical communication equipment production |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |