CN104678669B - A kind of array base palte and preparation method thereof, display panel, display device - Google Patents
A kind of array base palte and preparation method thereof, display panel, display device Download PDFInfo
- Publication number
- CN104678669B CN104678669B CN201510113331.0A CN201510113331A CN104678669B CN 104678669 B CN104678669 B CN 104678669B CN 201510113331 A CN201510113331 A CN 201510113331A CN 104678669 B CN104678669 B CN 104678669B
- Authority
- CN
- China
- Prior art keywords
- electrode
- pixel
- layer
- array base
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides a kind of array base palte and preparation method thereof, display panel, display device, by between the first electrode line and second electrode line of array base palte, second pixel electrode is set, second pixel electrode electrically connects with belonging to the first pixel electrode of a pixel cell, by increasing pixel electrode area, to reduce the leaping voltage of display device, so as to can ensure that the display quality of display device.
Description
Technical field
, specifically can a kind of array base palte and preparation method thereof, display panel, display the present invention relates to display technology field
Device.
Background technology
Flat-panel monitor such as Thin Film Transistor-LCD (Thin Film Transistor Liquid
Crystal Display, abbreviation TFT-LCD), organic light emitting diode display (also known as Organic Electricity laser writer,
Organic Light-Emitting Diode, abbreviation OLED) etc. be current most main flow display device, mobile phone screen, monitoring
Device screen, the TV overwhelming majority are flat-panel monitors.
Due to the dot structure feature of flat-panel monitor in itself, all inevitably there is coupling in existing flat-panel monitor
Electric capacity, and leaping voltage of the grid voltage caused by high potential to low spot position, the presence of leaping voltage directly affect flat board
The display quality of display.
The content of the invention
The present invention provides a kind of array base palte and preparation method thereof, display panel, display device, it can be ensured that display device
Display quality.
Offer scheme of the present invention is as follows：
The embodiments of the invention provide the pixel cell region of a kind of array base palte, including multiple matrix arrangements, Yi Jiwei
The first electrode line and second electrode line set between adjacent two pixel cells region and with layer, wherein, each pixel list
The first pixel electrode belonging to the pixel cell is provided with first region, it is characterised in that：Also include：
The second pixel electrode being arranged between the first electrode line and second electrode line, second pixel electrode with
Belong to the first pixel electrode electrical connection of a pixel cell.
Preferably, the first electrode line and second electrode line are set with layer.
Preferably, the electrode wires are grid line and/or data wire.
Preferably, the array base palte also includes：
Belong between the first pixel electrode of same pixel cell and the second pixel electrode electrically connect for realizing
Three pixel electrodes.
Preferably, the array base palte also include underlay substrate, grid layer, gate insulation layer, active layer, common electrode layer,
At least one of source-drain electrode layer, passivation layer.
The embodiment of the present invention additionally provides a kind of array substrate manufacturing method, and the array base palte includes multiple matrix arrangements
Pixel cell region, and between adjacent two pixel cells region and with layer set first electrode line and second electrode
Line, it is characterised in that methods described includes：
It is synchronous to make the first pixel electrode and the second pixel electrode on the existing figure layer of array base palte, wherein, the first picture
Plain electrode is located in affiliated pixel cell region, second pixel electrode between first electrode line and second electrode line,
Belong to the first pixel electrode and the electrical connection of the second pixel electrode of same pixel cell.
Preferably, the first electrode line and second electrode line are set with layer.
Preferably, the electrode wires are grid line and/or data wire.
Preferably, synchronous first pixel electrode and the process of the second pixel electrode of making also includes：
Synchronous to make the 3rd pixel electrode, the 3rd pixel electrode, which is used to realize, belongs to the first of same pixel cell
Electrical connection between pixel electrode and the second pixel electrode.
Preferably, method also includes making underlay substrate, grid layer, gate insulation layer, active layer, common electrode layer, source and drain
The step of at least one of electrode layer, passivation layer figure layer.
The embodiment of the present invention additionally provides a kind of display panel, including the array base palte that the embodiments of the present invention provide.
The embodiment of the present invention additionally provides a kind of display device, including the display panel that the embodiments of the present invention provide.
From described above as can be seen that array base palte provided by the invention and preparation method thereof, display panel, display dress
Put, by between the first electrode line and second electrode line of array base palte, setting the second pixel electrode, the second pixel electricity
Pole electrically connects with belonging to the first pixel electrode of a pixel cell, by increasing pixel electrode area, to reduce display dress
The leaping voltage put, so as to can ensure that the display quality of display device.
Brief description of the drawings
Fig. 1 is array base-plate structure schematic diagram one provided in an embodiment of the present invention；
Fig. 2 is array base-plate structure schematic diagram two provided in an embodiment of the present invention；
Fig. 3 is array base-plate structure schematic diagram three provided in an embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme of the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is this hair
Bright part of the embodiment, rather than whole embodiments.Based on described embodiments of the invention, ordinary skill
The every other embodiment that personnel are obtained, belongs to the scope of protection of the invention.
Unless otherwise defined, technical term or scientific terminology used herein should be in art of the present invention and had
The ordinary meaning that the personage of general technical ability is understood.Used in present patent application specification and claims " the
One ", " second " and similar word are not offered as any order, quantity or importance, and are used only to distinguish different
Part.Equally, the similar word such as "one" or " one " does not indicate that quantity limits yet, but represents to exist at least one.
" connection " either the similar word such as " connected " is not limited to physics or mechanical connection, but can include electrically
Connection, it is either directly or indirect." on ", " under ", "left", "right" etc. are only used for representing relative position relation, work as quilt
After the absolute position of description object changes, then the relative position relation also correspondingly changes.
The embodiments of the invention provide a kind of array base palte, as shown in figure 1, specifically may include multiple squares in the array base palte
The region of pixel cell 100 of battle array arrangement, and the first electrode line 1 and second between the adjacent region of two pixel cell 100
Electrode wires 2, wherein, the first pixel electrode 3 belonging to the pixel cell 100 is provided with each region of pixel cell 100.
The array base palte also includes：
The second pixel electrode 4 being arranged between the first electrode line 1 and second electrode line 2, the second pixel electricity
Pole 4 electrically connects with belonging to the first pixel electrode 3 of a pixel cell 100.
The array base palte that the embodiment of the present invention is provided, by way of increasing pixel electrode area, increase pixel cell
Interior liquid crystal capacitance (CLc), to reduce the leaping voltage of display device, so as to can ensure that the display quality of display device.
The theoretical formula of leaping voltage (Δ Vp) specifically can be as follows：
Δ Vp=Cgs_on* (Vgh-Vgl)/(Cgs_on+Cst+Clc)
Wherein, Vgh is gate high-voltage, and Vgl is grid low-voltage, and Cst is storage capacitance, and Clc is liquid crystal capacitance.
It can be seen that when the numerical value increase of liquid crystal capacitance (CLc), the numerical value of leaping voltage (Δ Vp) can be reduced, so as to
It can ensure that the display quality of display device.
Due in the region of pixel cell 100, being already provided with pixel electrode i.e. the first pixel corresponding to the pixel cell 100
Electrode 3, then, it can increase in the array base palte region between the first adjacent pixel electrode 3 and set the in the embodiment of the present invention
Two pixel electrodes 4, and second pixel electrode 4 is electrically connected with corresponding first pixel electrode 3, that is, belong to a pixel list
Electrically connected between the first pixel electrode 3 and the second pixel electrode 4 of member 100, so as to which the purpose of pixel electrode increase can be realized.
Adjacent involved by the embodiment of the present invention, concretely vertical direction is neighbouring, or horizontal direction is left
It is right adjacent, can also be adjacent up and down.
In array base palte graphic layer structure, between the first adjacent pixel electrode 3 (two i.e. adjacent pixel cells 100),
It is generally set to be equipped with electrode wires, such as grid line, data wire etc..So in order to avoid the second pixel electrode 4 newly increased is being powered
The signal transmitted afterwards to electrode wires has an impact, and the set location of the second pixel electrode 4 can avoid electrode wires region, i.e.,
View field on underlay substrate of view field of second pixel electrode 4 on underlay substrate and electrode wires is simultaneously misaligned, with
Avoid interfering between multi-signal.
In one embodiment, as shown in Fig. 2 the array base palte that is provided of the embodiment of the present invention concretely double grid line
The array base palte of structure, and first electrode 1 and second electrode 2 involved by the embodiment of the present invention, concretely set with layer
First grid line 11 and the second grid line 21.So, the second pixel electrode 4 involved by the embodiment of the present invention, it specifically may be disposed at
In array base palte region between one grid line 11 and the second grid line 21.
In another specific embodiment, as shown in figure 3, the array base palte concretely even numbers that the embodiment of the present invention is provided
According to the array base palte of cable architecture, and first electrode 1 and second electrode 2 involved by the embodiment of the present invention, concretely set with layer
The first data wire 12 and the second data wire 22 put.So, the second pixel electrode 4 involved by the embodiment of the present invention, specifically may be used
It is arranged in the array base palte region between the first data wire 12 and the second data wire 22.
As can be seen from Figure 1, 2, 3, the second pixel electrode 4 involved in the embodiment of the present invention be arranged at two grid lines or
Between two data wires, therefore, in order that belonging between the first pixel electrode 3 and the second pixel electrode 4 of a pixel cell
Electrically connect, be also provided with the 3rd pixel electrode 5 in the embodiment of the present invention, the 3rd pixel electrode 5 is respectively with belonging to same picture
The first pixel electrode 3 and the second pixel electrode 4 of plain unit electrically connect.
The presence of 3rd pixel electrode 5, the area of pixel electrode can be further increased, pixel electrode (CLc) number can be made
Value further increase, to realize lower leaping voltage (Δ Vp).
The array base palte that the embodiment of the present invention is provided, can be based on actual use need, set underlay substrate, grid layer,
At least one of gate insulation layer, active layer, common electrode layer, source-drain electrode layer, passivation layer figure layer, to this embodiment of the present invention
It is not intended to limit.
The embodiment of the present invention additionally provides a kind of array substrate manufacturing method, is carried for making the embodiments of the present invention
The array base palte of confession.
So, the region of pixel cell 100 of multiple matrix arrangements can be specifically included in the array base palte, and positioned at phase
First electrode line 1 and second electrode line 2 between the adjacent region of two pixel cell 100.
This method can specifically include：
It is synchronous to make the first pixel electrode 3 and the second pixel electrode 4 on the existing figure layer of array base palte, wherein, first
Pixel electrode 3 is located in the affiliated region of pixel cell 100, and the second pixel electrode 4 is located at first electrode line 1 and second electrode line 2
Between, the first pixel electrode 3 and the second pixel electrode 4 that belong to same pixel cell 100 electrically connect.
In one embodiment, the first pixel electrode 3 and second of synchronous making involved by the embodiments of the present invention
The process of pixel electrode 4 can also include：
Synchronous to make the 3rd pixel electrode 5, the 3rd pixel electrode 5 belongs to same pixel cell 100 for realization
The first pixel electrode 3 and the second pixel electrode 4 between electrical connection.
In addition, the array substrate manufacturing method that the embodiment of the present invention is provided, can also be based on actual use needs, including system
Make at least one of underlay substrate, grid layer, gate insulation layer, active layer, common electrode layer, source-drain electrode layer, passivation layer figure layer
The step of.
In the array substrate manufacturing method that the embodiment of the present invention is provided, be not intended to limit the manufacture craft of above-mentioned each figure layer with
And Making programme, any ripe, reliable manufacture craft and Making programme can be used, makes embodiments of the present invention institute
The various figure layers being related to.
The embodiment of the present invention additionally provides a kind of display panel, and the display panel specifically may include the embodiments of the present invention
The array base palte of offer.
The embodiment of the present invention additionally provides a kind of display device, and the display device specifically may include the embodiments of the present invention
The display panel of offer.
From described above as can be seen that array base palte provided by the invention and preparation method thereof, display panel, display dress
Put, by between the first electrode line and second electrode line of array base palte, setting the second pixel electrode, the second pixel electricity
Pole electrically connects with belonging to the first pixel electrode of a pixel cell, so that by way of increasing pixel electrode area, with
Reduce the leaping voltage of display device, it can be ensured that the display quality of display device.
Described above is only embodiments of the present invention, it is noted that is come for those skilled in the art
Say, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (12)
1. a kind of array base palte, include the pixel cell region of multiple matrix arrangements, and positioned at adjacent two pixel cells region
Between first electrode line and second electrode line, wherein, belonging to the pixel cell is provided with each pixel cell region
One pixel electrode, it is characterised in that also include：
The second pixel electrode being arranged between the first electrode line and second electrode line, second pixel electrode is with belonging to together
In the first pixel electrode electrical connection of a pixel cell.
2. array base palte as claimed in claim 1, it is characterised in that the first electrode line and second electrode line are set with layer
Put.
3. array base palte as claimed in claim 1, it is characterised in that the electrode wires are grid line and/or data wire.
4. array base palte as claimed in claim 1, it is characterised in that the array base palte also includes：
Belong between the first pixel electrode of same pixel cell and the second pixel electrode the 3rd picture electrically connected for realizing
Plain electrode.
5. array base palte as claimed in claim 1, it is characterised in that the array base palte also include underlay substrate, grid layer,
At least one of gate insulation layer, active layer, common electrode layer, source-drain electrode layer, passivation layer.
6. a kind of array substrate manufacturing method, the array base palte includes the pixel cell region of multiple matrix arrangements, Yi Jiwei
First electrode line and second electrode line between adjacent two pixel cells region, it is characterised in that methods described includes：
It is synchronous to make the first pixel electrode and the second pixel electrode on the existing figure layer of array base palte, wherein, the first pixel electricity
Pole is located in affiliated pixel cell region, and second pixel electrode belongs between first electrode line and second electrode line
First pixel electrode of same pixel cell and the electrical connection of the second pixel electrode.
7. method as claimed in claim 6, it is characterised in that the first electrode line and second electrode line are set with layer.
8. method as claimed in claim 6, it is characterised in that the electrode wires are grid line and/or data wire.
9. method as claimed in claim 6, it is characterised in that the first pixel electrode of the synchronous making and the second pixel electrode
Process also include：
Synchronous to make the 3rd pixel electrode, the 3rd pixel electrode is used to realize the first pixel for belonging to same pixel cell
Electrical connection between electrode and the second pixel electrode.
10. method as claimed in claim 6, it is characterised in that method also includes making underlay substrate, grid layer, gate insulation
The step of at least one of layer, active layer, common electrode layer, source-drain electrode layer, passivation layer figure layer.
11. a kind of display panel, it is characterised in that including the array base palte described in any one of 1-5.
12. a kind of display device, it is characterised in that including the display panel described in claim 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510113331.0A CN104678669B (en) | 2015-03-16 | 2015-03-16 | A kind of array base palte and preparation method thereof, display panel, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510113331.0A CN104678669B (en) | 2015-03-16 | 2015-03-16 | A kind of array base palte and preparation method thereof, display panel, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104678669A CN104678669A (en) | 2015-06-03 |
| CN104678669B true CN104678669B (en) | 2017-12-08 |
Family
ID=53313947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510113331.0A Active CN104678669B (en) | 2015-03-16 | 2015-03-16 | A kind of array base palte and preparation method thereof, display panel, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104678669B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11305248A (en) * | 1998-04-24 | 1999-11-05 | Sharp Corp | Liquid crystal display device |
| CN101706637A (en) * | 2009-04-03 | 2010-05-12 | 深超光电（深圳）有限公司 | Pixel electrode structure with high display quality |
| TW201409140A (en) * | 2012-08-17 | 2014-03-01 | Au Optronics Corp | Stereoscopic display panel, display panel and driving method thereof |
| CN102937764B (en) * | 2012-10-17 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and driving method of array substrate, and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060110167A (en) * | 2005-04-19 | 2006-10-24 | 삼성전자주식회사 | Array substrate and method for manufacturing thereof and liquid crystal display having the same |
-
2015
- 2015-03-16 CN CN201510113331.0A patent/CN104678669B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11305248A (en) * | 1998-04-24 | 1999-11-05 | Sharp Corp | Liquid crystal display device |
| CN101706637A (en) * | 2009-04-03 | 2010-05-12 | 深超光电（深圳）有限公司 | Pixel electrode structure with high display quality |
| TW201409140A (en) * | 2012-08-17 | 2014-03-01 | Au Optronics Corp | Stereoscopic display panel, display panel and driving method thereof |
| CN102937764B (en) * | 2012-10-17 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and driving method of array substrate, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104678669A (en) | 2015-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107293570B (en) | Display panel and display device | |
| US10777141B2 (en) | Display device | |
| US10236335B2 (en) | Display device | |
| CN110335564A (en) | A kind of array substrate, display panel and display device | |
| CN104699316B (en) | array substrate, display panel and display device | |
| CN104850268A (en) | Touch control display panel, touch control display device and production method | |
| CN204178340U (en) | Embedded display touch structure with narrow frame and high correctness | |
| CN103472647A (en) | Array substrate, liquid crystal display panel and display device | |
| CN104483792A (en) | Array substrate and display device | |
| CN104570515A (en) | Array substrate and manufacture method thereof, display panel and display device | |
| CN103777423B (en) | Liquid crystal panel and dot structure thereof | |
| CN103268878A (en) | TFT (thin film transistor) array substrate, and production method thereof and display device | |
| CN106206670B (en) | AMOLED display device and its array substrate | |
| CN104319354B (en) | Pin binding structure and display panel | |
| CN104360556A (en) | Liquid crystal display panel and array substrate | |
| CN102437113B (en) | Repairing method of signal disconnection of active matrix organic light-emitting display array substrate | |
| CN103077944A (en) | Display device, array substrate and manufacture method of array substrate | |
| JP2022013773A (en) | Display device | |
| CN110137228B (en) | Display panel and display device | |
| CN102790051A (en) | Array substrate and preparation method and display device thereof | |
| CN106527005A (en) | Manufacturing method of pixel structure | |
| CN103185997A (en) | Pixel structure and thin film transistor array substrate | |
| CN204315573U (en) | A kind of array base palte, display floater and display unit | |
| CN202421684U (en) | Array substrate and display device | |
| US20190012975A1 (en) | Pixel circuit structure and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |