CN104662520B - 用于管理具有不同高速缓存能力的跨页指令的方法和设备 - Google Patents

用于管理具有不同高速缓存能力的跨页指令的方法和设备 Download PDF

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Publication number
CN104662520B
CN104662520B CN201380047990.8A CN201380047990A CN104662520B CN 104662520 B CN104662520 B CN 104662520B CN 201380047990 A CN201380047990 A CN 201380047990A CN 104662520 B CN104662520 B CN 104662520B
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China
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instruction
cacheable
cache
instructions
page
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Expired - Fee Related
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CN201380047990.8A
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English (en)
Chinese (zh)
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CN104662520A (zh
Inventor
莱斯利·马克·德布鲁因
詹姆斯·诺里斯·迪芬德尔费尔
迈克尔·斯科特·麦基尔文
布莱恩·迈克尔·斯坦普尔
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CN201380047990.8A 2012-09-26 2013-09-26 用于管理具有不同高速缓存能力的跨页指令的方法和设备 Expired - Fee Related CN104662520B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/626,916 2012-09-26
US13/626,916 US8819342B2 (en) 2012-09-26 2012-09-26 Methods and apparatus for managing page crossing instructions with different cacheability
PCT/US2013/061876 WO2014052561A1 (en) 2012-09-26 2013-09-26 Methods and apparatus for managing page crossing instructions with different cacheability

Publications (2)

Publication Number Publication Date
CN104662520A CN104662520A (zh) 2015-05-27
CN104662520B true CN104662520B (zh) 2018-05-29

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CN201380047990.8A Expired - Fee Related CN104662520B (zh) 2012-09-26 2013-09-26 用于管理具有不同高速缓存能力的跨页指令的方法和设备

Country Status (5)

Country Link
US (1) US8819342B2 (https=)
EP (1) EP2901288B1 (https=)
JP (1) JP6196310B2 (https=)
CN (1) CN104662520B (https=)
WO (1) WO2014052561A1 (https=)

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US9460018B2 (en) 2012-05-09 2016-10-04 Qualcomm Incorporated Method and apparatus for tracking extra data permissions in an instruction cache
US9348598B2 (en) * 2013-04-23 2016-05-24 Arm Limited Data processing apparatus and method for pre-decoding instructions to be executed by processing circuitry
US10318427B2 (en) * 2014-12-18 2019-06-11 Intel Corporation Resolving memory accesses crossing cache line boundaries
US9356602B1 (en) * 2015-05-14 2016-05-31 Xilinx, Inc. Management of memory resources in a programmable integrated circuit
US10176096B2 (en) * 2016-02-22 2019-01-08 Qualcomm Incorporated Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
US20170255569A1 (en) * 2016-03-01 2017-09-07 Qualcomm Incorporated Write-allocation for a cache based on execute permissions
CN105786717B (zh) * 2016-03-22 2018-11-16 华中科技大学 软硬件协同管理的dram-nvm层次化异构内存访问方法及系统
US10204053B2 (en) * 2016-09-30 2019-02-12 Oracle International Corporation Modeling processor shared memory using a cacheability status
US11726783B2 (en) * 2020-04-23 2023-08-15 Advanced Micro Devices, Inc. Filtering micro-operations for a micro-operation cache in a processor
US11740973B2 (en) * 2020-11-23 2023-08-29 Cadence Design Systems, Inc. Instruction error handling
CN112631490A (zh) * 2020-12-30 2021-04-09 北京飞讯数码科技有限公司 显示界面控制方法、装置、计算机设备及存储介质
US11995010B2 (en) * 2021-04-16 2024-05-28 Avago Technologies International Sales Pte. Limited Adaptor storage system of and method
CN118796278B (zh) * 2024-09-14 2024-11-29 北京微核芯科技有限公司 处理器取指令方法、装置、设备和存储介质

Citations (2)

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CN1820257A (zh) * 2002-11-26 2006-08-16 先进微装置公司 包括具有不同缓存线大小的第一级高速缓存及第二级高速缓存的微处理器
CN101493762A (zh) * 2008-01-23 2009-07-29 Arm有限公司 多指令集的指令预解码

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JPS6020255A (ja) * 1983-07-15 1985-02-01 Fujitsu Ltd バツフア記憶制御方式
JPH0254351A (ja) * 1988-08-18 1990-02-23 Mitsubishi Electric Corp データ処理システム
EP1224539A1 (en) 1999-10-14 2002-07-24 Advanced Micro Devices, Inc. Apparatus and method for caching alignment information
US7330959B1 (en) 2004-04-23 2008-02-12 Transmeta Corporation Use of MTRR and page attribute table to support multiple byte order formats in a computer system
US7406613B2 (en) 2004-12-02 2008-07-29 Qualcomm Incorporated Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions
JP4837305B2 (ja) * 2005-05-10 2011-12-14 ルネサスエレクトロニクス株式会社 マイクロプロセッサ及びマイクロプロセッサの制御方法
US7404042B2 (en) 2005-05-18 2008-07-22 Qualcomm Incorporated Handling cache miss in an instruction crossing a cache line boundary
US8117404B2 (en) 2005-08-10 2012-02-14 Apple Inc. Misalignment predictor
US7337272B2 (en) * 2006-05-01 2008-02-26 Qualcomm Incorporated Method and apparatus for caching variable length instructions
US20080120468A1 (en) * 2006-11-21 2008-05-22 Davis Gordon T Instruction Cache Trace Formation
US8239657B2 (en) 2007-02-07 2012-08-07 Qualcomm Incorporated Address translation method and apparatus
US8898437B2 (en) 2007-11-02 2014-11-25 Qualcomm Incorporated Predecode repair cache for instructions that cross an instruction cache line
US8140768B2 (en) 2008-02-01 2012-03-20 International Business Machines Corporation Jump starting prefetch streams across page boundaries
US8639943B2 (en) 2008-06-16 2014-01-28 Qualcomm Incorporated Methods and systems for checking run-time integrity of secure code cross-reference to related applications
US8560811B2 (en) 2010-08-05 2013-10-15 Advanced Micro Devices, Inc. Lane crossing instruction selecting operand data bits conveyed from register via direct path and lane crossing path for execution
US9460018B2 (en) 2012-05-09 2016-10-04 Qualcomm Incorporated Method and apparatus for tracking extra data permissions in an instruction cache

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
CN1820257A (zh) * 2002-11-26 2006-08-16 先进微装置公司 包括具有不同缓存线大小的第一级高速缓存及第二级高速缓存的微处理器
CN101493762A (zh) * 2008-01-23 2009-07-29 Arm有限公司 多指令集的指令预解码

Also Published As

Publication number Publication date
CN104662520A (zh) 2015-05-27
US8819342B2 (en) 2014-08-26
JP6196310B2 (ja) 2017-09-13
JP2015534687A (ja) 2015-12-03
EP2901288A1 (en) 2015-08-05
WO2014052561A1 (en) 2014-04-03
EP2901288B1 (en) 2018-08-08
US20140089598A1 (en) 2014-03-27

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