CN104658950B - For keeping the storing apparatus of chip and for by the apparatus and method of wafer alignment - Google Patents
For keeping the storing apparatus of chip and for by the apparatus and method of wafer alignment Download PDFInfo
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- CN104658950B CN104658950B CN201510048231.4A CN201510048231A CN104658950B CN 104658950 B CN104658950 B CN 104658950B CN 201510048231 A CN201510048231 A CN 201510048231A CN 104658950 B CN104658950 B CN 104658950B
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- retaining surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The present invention relates to the storing apparatus for accommodating and keeping chip, has following feature：Retaining surface（1o）, for chip to be maintained at into retaining surface（1o）On holding meanss and compensation device（3,4,5,6）, active, especially local controllable, at least part of compensation is carried out for the global deformation to chip.The invention further relates to for using foregoing storing apparatus by the first chip and the apparatus and method of the second wafer alignment.
Description
Technical field
The present invention relates to for accommodating and keeping the storing apparatus of chip and in the feelings using the storing apparatus
By the first chip and the apparatus and method of the second wafer alignment under condition.
Background technology
This storing apparatus or sample retainer or chuck exist with many embodiments, and for storing apparatus,
Flat receiving face or retaining surface is conclusive, thus becomes less and less structure in increasing wafer face
It can be properly aligned and contact in whole wafer face.If so-called pre- bonding steps（The pre- bonding steps are by chip
It is connected with each other by separable connection）If being performed before the bonding process of reality, this is especially important.As long as
All structures set on one or two chip should realize 2 μm of ＜ alignment precision or especially deformation values, chip
Height alignment accuracy each other is exactly especially important.In known storing apparatus and device for alignment（It is i.e. so-called
Aligner, especially bond aligner）In, this can very well reach near alignment mark.With from alignment mark
The increase of distance, there is the alignment accuracy or especially for being better than 2 μm, preferably better than 1 μm and being further preferably better than 0.25 μm
The on inspection and perfectly alignment of deformation values is not achievable.
The content of the invention
The task of the present invention is so to improve the storing apparatus according to type so that can be realized using it more accurate
Alignment.
The task utilize it is a kind of be used for accommodate and keep the storing apparatus of chip to solve, the storing apparatus has following
Feature：
- retaining surface,
- be used to chip being maintained at holding meanss at retaining surface, and
- compensation device, active, local controllable, at least part of compensation is carried out for the global deformation to chip.
The task also utilize it is a kind of be used for by the first chip and the device of the second wafer alignment solution, the device has following
Feature：
- be used to determine the device of local alignment error, the local alignment in the form of the vector field with deformation vector
Error is due to that the first chip occurs relative to the elongation and/or deformation of the second chip,
- at least one storing apparatus for being used to accommodate at least one chip according to one of the claims, and
- be used for consider vector field and simultaneously by the compensation of compensation device in the case of aligning wafer alignment dress
Put.
The task also utilize it is a kind of be used for by the method for the first chip and the second wafer alignment solution, this method has following
The step of, especially in the following order：
The vector field with deformation vector of the first chip of-detection and/or the vector with deformation vector of the second chip
And vector field is analyzed by analytical equipment and tries to achieve local alignment error,
- at least one chip is received into foregoing storing apparatus, and
- consider vector field and simultaneously by the compensation of compensation device in the case of aligning wafer.
In illustrated value scope, the value in the boundary should also be as being disclosed as boundary value and can with appoint
The requested protection of meaning combination.
The present invention based on the understanding according to european patent application EP 09012023 and EP10 015 569 applicant, its
It is middle utilize above-mentioned understanding, the detection of whole surface, especially using the position of the structure in each wafer surface as
Wafer position figure is possible.The invention being subsequently noted be related to for try to achieve when the first chip is connected with the second chip due to
The device for the local alignment error that first chip occurs relative to the elongation and/or deformation of the second chip, has：
- along the first chip the first contact surface stretch value the first stretch scheme and/or
- along the second contact surface stretch value the second stretch scheme and
- the analytical equipment for the first and/or second stretch scheme of analysis, can be in the hope of the alignment error of part by it.
Here, the basic thought of the present invention is, the receiving being made up of multiple, separate Active control element is set
Device, it can be especially affected in terms of shape and/or temperature using the retaining surface of these control element storing apparatus.
This, these Active control elements are used by manipulating accordingly so that the known part by the location drawing and/or stretch scheme
Either local deformation is compensated or farthest minimizes or reduce alignment error.Here, not only overcome part
Deformation, and minimize or correct simultaneously by local deformation is caused on the whole, chip is grand in its external dimensions
See deformation or elongation.
Therefore, according to the present invention, by the invention described above for being related to the location drawing, stretch scheme and/or stress diagram and
In the case that correction is combined on the spot of the disclosed alignment error in contact and bonding wafer there, it is in particular possible to
Be：The alignment result further improved is realized by active, the especially local effect to wafer distortion.
Provided according to the advantageous embodiment of the present invention, can be by compensation device come local influence retaining surface
Temperature.The local temperature rise of retaining surface causes to be maintained at part expansion of the chip in retaining surface in the opening position.Temperature ladder
Degree is higher, and chip is more in the expansion of the opening position.So as to which the data based on the location drawing and/or expansion plans, especially alignment miss
The vector analysis of difference, in particular for each position of the location drawing and/or expansion plans, can targetedly act on chip
Local deformation or the confrontation local deformation.
In this context, vector analysis is understood to the vector field with deformation vector, and the vector field is particular by two
One of modification of the present invention described below is tried to achieve.
First modification is related to wherein only application scenarios of one of two chips of structuring.In this case, according to this hair
Bright regulation, detect the deviation of structure, the especially deviation of geometry and desired geometry.In this case, especially
It is interested, exposure region, be especially repeated several times exposure exposure sources exposure region shape and nominal intended shape
Deviation, the nominal intended shape is typically rectangle.These deviations, the vector field for especially describing these deviations can be by
Completed according to EP 09012023 based on the detection of the location drawing to each alignment mark corresponding with exposure region.Instead, should
Vector field can also be tried to achieve based on the stress diagram and/or stretch scheme that are detected by EP 10 015 569.6.But according to
The vector field of the invention advantageously can also be tried to achieve and read in by any other suitable measurement apparatus.Exposure is repeated several times
Etching system is especially applicable this measurement, these etching systems in order to detect the data and with specific test mask and/
Or fc-specific test FC routine operation.
Second modification is related to the application scenarios that two chips are structured wherein.In this case, advised according to the present invention
It is fixed, calculate alignment in particular for the location drawing, especially according to all positions of EP 09,012,023 first and second locations drawing
The vector field of deviation.The vector field should be according to the embodiment in EP 10 015 569.6 in particular for according to technology
And/or economic criterion is counted as preferable aligned position to try to achieve.
Provided in another advantageous embodiment of the present invention, retaining surface can partly be influenceed by compensation device
Elongation, especially by the preferably independent controllable piezoelectric element of arrangement at the back side of retaining surface.Pass through the elongation of retaining surface
Or shrink namely bear elongation, also correspondingly cause the chip especially by the confining force acted on by retaining surface on chip
Deformation, especially extend or shrink so that can be based upon by this way the stretch scheme that the chip is tried to achieve value pass through it is corresponding
Control device targetedly influence the chip.As long as by the compensation device, preferred especially by z-direction
Mechanism can partly influence the shape of retaining surface, there is chip of the other confrontation in retaining surface deformation can
Can property.Here it is also suitable, the control to compensation device is completed by control device, and the control device is based on the location drawing
And/or the value of stretch scheme is carried out correspondingly targetedly, to the Partial controll of compensation device.
Control device especially includes being used for the software for implementing/calculating corresponding routine.
According to the present invention another Advantageous embodiments provide, from the back side of retaining surface by compensation device partly, especially
It is to surge and/or pneumatically apply pressure to retaining surface.Thus, the shape of retaining surface can equally be had an impact, so as to
Obtain above-mentioned effect.The control is equally carried out further through control described above device.
Advantageously, compensation device is arranged to integrate, multiple having of being preferably embedded in storing apparatus, especially retaining surface
Source control element.Thus, it is possible to the receiving portion of storing apparatus is monolithically constructed, such as its same feelings in known storing apparatus
Condition is the same.
Particularly advantageous here is can individually manipulate each control element or control element group.Local manipulation phase
Answer ground to refer to, small section, especially less than chip half, preferably smaller than chip 1/4, be preferably smaller than chip 1/8, be further excellent
Choosing can partly be manipulated less than the section of chip 1/16 by compensation device.Particularly advantageously, compensation device can profit
Each region occupied by the structure of oneself of chip is acted on at least one control element.
The device of the present invention advantageously comprises previously described control in the central control unit for being responsible for all control process
Device processed.But according to the present invention it is contemplated that control device is set in storing apparatus, especially as single unit system
Module.
Method according to the present invention can be further improved in the following way, that is, be provided after the alignment to first
And/or second chip the location drawing and/or stretch scheme carry out detection especially again.It can specify that thus in accordance with the present invention
Complete and alignment completion is tested after aliging.Correspondingly it is contemplated that carrying out the chip pair with excessive alignment error
Exclusion, so as to for example it is carried out again according to the present invention alignment or cleaning.Meanwhile the data of detection can be used for outstanding
It is to carry out self calibration to the device by control device.
In the disclosed hairs of european patent application EP 09012023.9 and/or european patent application EP 10 015 569.6
In bright, the present invention is suitable to while together disclosure as embodiment.
Brief description of the drawings
Further advantage, feature and the details of the present invention obtains from the following description of preferred embodiment and by accompanying drawing,
Wherein：
Fig. 1 a show the top view of storing apparatus of the invention in the first embodiment,
Fig. 1 b show the section view according to Fig. 1 a Vertical Centre Lines A-A of storing apparatus,
Fig. 2 a show the top view of storing apparatus of the invention in this second embodiment,
Fig. 2 b show the section view according to Fig. 2 a Vertical Centre Lines B-B of storing apparatus,
Fig. 3 a show the top view of storing apparatus of the invention in the third embodiment,
Fig. 3 b show the section view according to Fig. 3 a Vertical Centre Lines C-C of storing apparatus,
Fig. 4 a show the top view of storing apparatus of the invention in the 4th embodiment,
Fig. 4 b show the section view according to Fig. 4 a Vertical Centre Lines D-D of storing apparatus.
In the accompanying drawings, identical and effect identical components/features are denoted with the same reference numerals.
Embodiment
All 4 embodiments show the receiving portion 1 of monolithic, and they are arranged to plane, circular disc,
The disc carries the smooth flat retaining surface 1o for being used for accommodating and keep chip.On the outer periphery, receiving portion has collar flange 1a.
Retaining surface 1o forms the receiving plane for accommodating chip, and the receiving plane extends in x and y direction.Z-direction with
It vertically extends, and the confining force orientation acted on chip is in z-direction.The holding of chip is carried out by perforate 2, described to open
Hole is distributed in same shape the Shangdi of retaining surface 10 arrangement in large quantities, so as to under-voltage be protected chip by applying to perforate 2
Hold on retaining surface 1o.The quantity of perforate 2 is bigger and the diameter of perforate 2 is smaller, be applied at perforate 2 be used for keep chip
The under-voltage deformation for causing chip fewlyer at perforate 2.
Under-voltage at perforate 2 is applied by unshowned vacuum plant, and the vacuum plant is to being arranged in retaining surface 1o's
The inner space 1i at the back side applies under-voltage.Inner space 1i is defined and relative to ring by the peripheral wall 1w of receiving portion 1 in addition
Border is sealed.Perforate 2 extends to interior space 1i from retaining surface 1o and therefore can be equally applied in be accounted in space 1i internally
Leading is under-voltage.
Inner space 1i passes through vis-a-vis retaining surface the 1o back side 1r arranged and the inner space 1i having been not shown in addition
Bottom portion defining, wherein back side 1r passed through by perforate 2.
Multiple heating/cooling elements are overleaf provided with 1r as Active control element, heating is especially only set
Element 3.Heating element heater 3 is manipulated individually or in groups respectively, wherein the control by unshowned control device come complete
Into.In heating heating element heater 3 for the moment, the material of the very well heat conduction of receiving portion is passed through（Especially metal）Kept to heat
Face 1o partial section.This causes the local expansion of chip in this region on retaining surface 1o.Therefore in storing apparatus
The chip of upper receiving by correspondingly align and possible deformation/elongation position known in the case of targetedly pass through switch
Single or multiple heating element heaters 3 cause the deformation of chip, to compensate local deformation.Thus, especially in a large amount of local repairs
In the case of repaying, the global compensation of change of to overall situation deformation, especially chip the diameter in X and/or Y-direction is also obtained.
The special benefits influenceed by heating and/or cooling element on the deformation at chip are following possibility：
Can be with minimal deformation, especially without keeping shifting ground in vertical direction or Z-direction of facial disfigurement and/or especially non-wafer
Realize the influence.Minimum deformation is can be regarded as in this context, and retaining surface and especially chip are in vertical direction（Namely
Vertical direction or Z-direction）Relative to 5 μm of the deformation ＜ of mounting surface, advantageously 2 μm of ＜, preferably 1 μm of ＜ and further preferably
0.5 μm of ＜.This is connected especially for the pre- bonding of manufacture, is for example to have for the pre- bonding connected based on Van-der-Waals
Profit.Due to here, retaining surface and especially chip can be kept for the fact that flat, common in such pre- bonding steps
Bonding ripple will not in its diffusion by unevenness influence.Therefore, retain and be not bonded position（So-called space）Risk
It is greatly diminished.In order to manufacture this pre- bonding connection, make every effort to make the flat of retaining surface in whole wafer face according to the present invention
Spend 5 μm of ＜, further preferably advantageously 2 μm of ＜, preferably 1 μm of ＜ and 0.5 μm of ＜.These values of flatness refer to
Distance of each partial interior of the demifacet of contact wafers between highest and minimum point.
Heating element heater 3 is advantageously evenly distributed below retaining surface 1o.Advantageously, set in storing apparatus and be more than 10
Individual heating element heater 3, particular more than 50 heating element heaters 3, preferably more than 100 heating element heaters 3 are preferred to be more than 500
Heating element heater 3.These heating element heaters form the region that can be individually manipulated in retaining surface, and these regions can be realized to chip
Local action.Advantageously, the regional of retaining surface is mutually thermally isolated using suitable device.Especially, these region quilts
Shape is constructed in, the shape can realize the uniform of each section and the arrangement closed.Advantageously, by these section structures
Make and be suitable for this for triangle, quadrangle or hexagon.
As heating element heater 3 it is particularly suitable that Peltier's element.
Heating element heater 3 is not shown in the second form of implementation shown in Fig. 2 a and 2b, it is instead or in combination
Ground is provided with piezoelectric element 4 at retaining surface 1o, is preferably more than to back side 1r distance to retaining surface 1o distance.By this
Mode realizes the targetedly effect to retaining surface 1o.Piezoelectric element 4 can cause in nanometer to micrometer range in activation
In elongation.
The quantity of piezoelectric element 4 can be equal to heating element heater 3 above-mentioned quantity, wherein according to the present invention it is contemplated that this two
The combination of individual embodiment.
In the 3rd embodiment shown in Fig. 3 a and 3b of the present invention, instead of heating element heater 3 and/or piezoelectric element
4 or it is in combination be provided with pin 5, these pins are terminated at retaining surface 1o with especially sharp dowel ends 5e.
In the output end position of pin 5, dowel ends 5e is concordant with retaining surface 1o.As long as chip it is determined that pin 5 region in
Local deformation exists as the information of deformation pattern or stretch scheme, and control device can is by manipulating single or multiple pins 5 innings
Chip is acted on to portion, its mode is that pin 5 or dowel ends 5e move towards the direction of chip in z-direction.Pin end
Thus portion 5e partly applies pressure to chip, the pressure causes chip in the position local crowning or deflection.Pin 5 can
With or be integrally slidably directed in the guiding perforate 7 for extending to back side 1r from retaining surface 1o.To this instead, only
Dowel ends 5e is movable in pin 5 and the compresses lower section of pin 5 or pin is consolidated relative to perforate 7 is oriented to
It is fixed.In this way, it is ensured that the pin 5 or these pins 5 relative interior space 1r special sealing.
The quantity of pin 5 is equal to the quantity of piezoelectric element 4 or heating element heater 3, wherein can also combine one or more here
Individual foregoing embodiment.
In figs 4 a and 4b in shown embodiment, receiving portion 1 has multiple balancing gate pits 6, these balancing gate pits with its
The upper wall 6o shown in Fig. 4 b forms retaining surface 1o.Balancing gate pit 6 extends through inner space 1i and relative to inner space li
Sealed.Each 6 groups of balancing gate pit 6 or balancing gate pit can be individually pressurized, and the wherein control can be by described
Control device carry out.In the case where applying pressure, balancing gate pit 6 is at least configured at its upper wall 6o so that its
Deform, namely be configured to thinner and/or more soft than other interface walls of balancing gate pit 6 in the case of applying pressure.Perforate 2 with it is interior
The 1i connections of portion space.
According to the present invention, 3 μm of the maximum to retaining surface 1o is only only completed by foregoing compensation device 3,4,5,6, especially
It is maximum 1 μm, the preferably at most 100nm local deflection of minimum.
In order to resist local deformation using the one or more in foregoing embodiment, need as described above
Will：Control device knows that the deformation in chip is present in where and with which kind of degree or on what direction.Then could
The deformation targetedly act on or resist and compensate.The stretch scheme of each chip, which produces, to be distributed on chip
Elongation vector form explanation, these elongation vectors are utilized according to EP 10 015 569.6 corresponding measurement apparatus to try to achieve.
Corresponding control data can be tried to achieve especially by experience, stored in a control unit, so as to being capable of root for each chip
Individually controlled according to the chip stretch scheme in the previously given opening position of the location drawing by chip.In this way can be with
Automatically compensated during aligning wafer.
Active control element 3,4,5,6 be not in these figures perspec-tive be depicted, and also can have difference
Size or shape.
Reference table
1 receiving portion
1a collar flanges
1i inner spaces
1o retaining surfaces
1w peripheral walls
2 perforates
3 heating/cooling element
4 piezoelectric elements
5 pins
5e dowel ends
6 balancing gate pits
6o upper walls
7 are oriented to perforate
Claims (16)
1. for accommodating and keeping the storing apparatus of chip, there is following feature：
- smooth flat retaining surface（1o）,
- be used to the chip being maintained at the retaining surface（1o）The holding meanss at place, and
- compensation device（3,4,5,6）, active, local controllable, at least portion is carried out for the global deformation to the chip
The compensation divided,
Characterized in that, the retaining surface（1o）It is configured to extend or shrinks so that the wafer distortion.
2. storing apparatus according to claim 1, wherein passing through the compensation device（3,4,5,6）Can partly it influence
The retaining surface（1o）Temperature.
3. storing apparatus according to claim 1, wherein passing through the compensation device（3,4,5,6）Can partly it influence
The retaining surface（1o）Elongation.
4. storing apparatus according to claim 3, wherein by the retaining surface（1o）The back side（1r）Place's arrangement pressure
Electric device（4）The retaining surface can partly be influenceed（1o）Elongation.
5. storing apparatus according to claim 4, wherein the piezoelectric element（4）Can individually it be manipulated.
6. storing apparatus according to claim 1, it is characterised in that pass through the compensation device（3,4,5,6）Being capable of office
Influence to portion the retaining surface（1o）Shape.
7. storing apparatus according to claim 6, wherein can partly influence the guarantor by effect in z-direction
Hold face（1o）Shape.
8. storing apparatus according to claim 7, wherein the shape is mechanically influenceed.
9. storing apparatus according to claim 1, wherein can be from the retaining surface（1o）The back side（1r）By described
Compensation device（3,4,5,6）Partly to the retaining surface（1o）Apply pressure.
10. storing apparatus according to claim 9, wherein can surge and/or pneumatically to the retaining surface（1o）Apply
Plus-pressure.
11. storing apparatus according to claim 1, wherein by the compensation device（3,4,5,6）It is arranged in the appearance
The multiple Active control elements received in device（3,4,5,6）.
12. storing apparatus according to claim 11, wherein the compensation device（3,4,5,6）It is integrated in the retaining surface
（1o）In.
13. storing apparatus according to claim 11, wherein each control element can be manipulated individually（3,4,5,6）Or
Control element（3,4,5,6）Group.
14. it is used for, by the device of the first chip and the second wafer alignment, there is following feature：
- be used to determine the device of local alignment error, the local alignment error in the form of the vector field with deformation vector
It is due to the first chip stretching relative to second chip described in when first chip is connected with second chip
Long and/or deformation and occur,
- it is at least one it is according to claim 1 or 2 be used to accommodate the storing apparatus of at least one chip, and
- be used for consider the vector field and simultaneously by the compensation of the compensation device in the case of aligning wafer pair
Neat device.
15. it is used for, by the method for the first chip and the second wafer alignment, there is following step：
The vector field with deformation vector of-detection first chip and/or second chip with deformation vector
Vector field and vector field is analyzed by analytical equipment and tries to achieve local alignment error,
- at least one chip is received into storing apparatus according to claim 1 or 2, and
- consider vector field and simultaneously by the compensation of compensation device in the case of aligning wafer.
16. according to the method for claim 15, wherein setting after the alignment to first chip and/or described second
The detection of the vector field of chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510048231.4A CN104658950B (en) | 2010-12-20 | 2010-12-20 | For keeping the storing apparatus of chip and for by the apparatus and method of wafer alignment |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510048231.4A CN104658950B (en) | 2010-12-20 | 2010-12-20 | For keeping the storing apparatus of chip and for by the apparatus and method of wafer alignment |
| CN201080070797.2A CN103283000B (en) | 2010-12-20 | 2010-12-20 | For keeping the storing apparatus of wafer |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201080070797.2A Division CN103283000B (en) | 2010-12-20 | 2010-12-20 | For keeping the storing apparatus of wafer |
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| Publication Number | Publication Date |
|---|---|
| CN104658950A CN104658950A (en) | 2015-05-27 |
| CN104658950B true CN104658950B (en) | 2018-01-19 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11782411B2 (en) | 2021-07-28 | 2023-10-10 | Kla Corporation | System and method for mitigating overlay distortion patterns caused by a wafer bonding tool |
| US11829077B2 (en) | 2020-12-11 | 2023-11-28 | Kla Corporation | System and method for determining post bonding overlay |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI782169B (en) * | 2018-01-23 | 2022-11-01 | 日商東京威力科創股份有限公司 | Joining system and joining method |
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| US4475223A (en) * | 1981-06-12 | 1984-10-02 | Hitachi, Ltd. | Exposure process and system |
| US5094536A (en) * | 1990-11-05 | 1992-03-10 | Litel Instruments | Deformable wafer chuck |
| CN101286430A (en) * | 2008-06-03 | 2008-10-15 | 浙江大学 | An electronic emitter on silicon-based surface and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060107048A (en) * | 2005-04-07 | 2006-10-13 | 삼성전자주식회사 | Heating apparatus and driving method thereof |
| JP2009200247A (en) * | 2008-02-21 | 2009-09-03 | Dap Technology Kk | Packing method and packing apparatus |
| JP5440495B2 (en) * | 2008-04-30 | 2014-03-12 | 株式会社ニコン | Evaluation method, evaluation apparatus, substrate overlay method, and substrate overlay apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4475223A (en) * | 1981-06-12 | 1984-10-02 | Hitachi, Ltd. | Exposure process and system |
| US5094536A (en) * | 1990-11-05 | 1992-03-10 | Litel Instruments | Deformable wafer chuck |
| CN101286430A (en) * | 2008-06-03 | 2008-10-15 | 浙江大学 | An electronic emitter on silicon-based surface and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11829077B2 (en) | 2020-12-11 | 2023-11-28 | Kla Corporation | System and method for determining post bonding overlay |
| US11782411B2 (en) | 2021-07-28 | 2023-10-10 | Kla Corporation | System and method for mitigating overlay distortion patterns caused by a wafer bonding tool |
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| Publication number | Publication date |
|---|---|
| CN104658950A (en) | 2015-05-27 |
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