CN104658902A - Trench gate etching method - Google Patents
Trench gate etching method Download PDFInfo
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- CN104658902A CN104658902A CN201510043716.4A CN201510043716A CN104658902A CN 104658902 A CN104658902 A CN 104658902A CN 201510043716 A CN201510043716 A CN 201510043716A CN 104658902 A CN104658902 A CN 104658902A
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- mask
- etching
- groove
- protective layer
- preset distance
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 title claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000011241 protective layer Substances 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 239000007789 gas Substances 0.000 claims description 16
- 239000010410 layer Substances 0.000 claims description 16
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 239000001301 oxygen Substances 0.000 claims description 14
- 229910052760 oxygen Inorganic materials 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 11
- 239000007788 liquid Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 239000002360 explosive Substances 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- VUZPPFZMUPKLLV-UHFFFAOYSA-N methane;hydrate Chemical compound C.O VUZPPFZMUPKLLV-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention relates to a trench gate etching method. The trench gate etching method comprises the following steps: step one, forming a mask on the surface of a silicon substrate, etching a trench through the mask to the interior of the silicon substrate, and forming a surrounding region by the region, adjacent to the side wall of the trench, of the mask; step two, etching the surrounding region perpendicular to the side wall of the trench, and forming a step at a first preset distance between the edge of the surrounding region after etching and the top angle of the trench; step three, coating the surface of the silicon substrate with a protective layer after treatment in the second step; step four, removing the protective layer on the surrounding region and the step, and removing the protective layer on the internal part of the trench until a second preset distance is formed between the surface of the protective layer inside the trench and the top angle of the trench; step five, under the protection of the protective layer and the surrounding region after etching, etching the step into a smooth edge. According to the method disclosed by the invention, the trench is filled with the protective layer after the trench is formed. When smooth treatment is carried out on the top corner, the trench can be prevented from being damaged.
Description
Technical field
The present invention relates to semiconductor applications, particularly trench gate engraving method.
Background technology
Generally include three poles at the field-effect transistor of prior art, i.e. source electrode, drain and gate, wherein grid is for controlling conducting and the disconnection of source electrode and drain electrode.That is, grid is actually the control pole of field-effect transistor.For the field-effect transistor taking semiconductor silicon as substrate, by grid applied voltage, can by silicon substrate body charge carrier (electronics or hole) be attracted to surface, make the substrate surface charge accumulated below grid form conducting channel.In order to shorten current path, reduce loss, usually the planar gate structure on surface can be improved to trench gate structure.
When constructing trench gate, puncturing grid oxic horizon to prevent the sharp-pointed drift angle of groove from producing point discharge phenomenon and grid was lost efficacy, need after formation of the groove, then vertical angles carrying out sphering process.But when vertical angles carry out corners, often damage the sidewall of groove and affect the quality of trench gate, this will inevitably cause the later stage to the mending course of trenched side-wall, makes the construction process of trench gate complicated.
Summary of the invention
For the problems referred to above, the present invention proposes a kind of trench gate engraving method.According to method of the present invention, after formation of the groove, in groove, protective layer is filled with.When vertical angles carry out sphering process, trench wall can be prevented to be destroyed.
According to trench gate engraving method of the present invention, comprise step one: on the surface of silicon substrate, form mask, groove is become towards the etched inside of silicon substrate through mask, the region adjacent with the sidewall of groove of mask is formed around district, step 2: etch perpendicular to the sidewall of groove around district, the step of the first preset distance is formed between the edge around district after the etching and the drift angle of groove, step 3: armor coated on the surface after step 2 process of silicon substrate, step 4: remove around the protective layer in district and step, and remove the protective layer of the part in groove, until be the second preset distance between the surface of protective layer in groove and the drift angle of groove, step 5: protective layer and etching after around under the protection in district, step is etched to round and smooth edge.
According to method of the present invention, armor coated in groove be etched into groove in silicon substrate after, like this when carrying out groove drift angle corners, the sidewall of groove can be protected not to be damaged, to simplify the manufacture process of trench gate.
In one embodiment, in step one, be also provided with the first photoresist around in district.In another embodiment, in step 2, corrosion etches around district in a wet process; After formation step, remove the first photoresist.Owing to can select corrosive liquid mask to very strong selectivity, and the material of mask is different from the material of silicon substrate, therefore only mask by fast erosion, silicon substrate is not corroded substantially.Under the protection of photoresist, corrosive liquid only outwards etches around district (or mask) to form step from the sidewall of groove.In a preferred embodiment, mask is silicon nitride layer or silicon dioxide layer; When being mask for silicon nitride layer, the corrosive liquid that wet etching uses is phosphoric acid; When being mask for silicon dioxide layer, the aqueous solution that the corrosive liquid that wet etching uses is hydrofluoric acid.
In one embodiment, in step 3, the protective layer used is the second photoresist.In one embodiment, the mode removing the second photoresist is plasma etching, and the etching gas used is oxygen.By controlling speed and the etching end point of plasma etching, can guarantee the second photoresists (or protective layer) all in groove all can not to be removed, but predetermined amount can be retained.Second photoresist can be oxidized to carbon dioxide and water by oxygen, thus can etch products be discharged easily.In addition, when using oxygen etch the second photoresist, mask can stop oxygen to penetrate in silicon substrate, and the exposed silicon of stepped area can react with oxygen and generates silica coating and can deeply infiltrate to the inside of silicon substrate by anti-block, thus, use oxygen not only can etch away the second photoresist easily, and silicon substrate can be made not to be damaged on the whole.
In a preferred embodiment, etching gas also comprises nitrogen and the hydrogen outside explosive range.In the process of removing second photoresist, oxygen and hydrogen reaction generate a large amount of heat, and this contributes to the removing speed of raising second photoresist.Remove for the second photoresist for plasma etching, nitrogen is inert gas, therefore by regulating the content of nitrogen, can control the etching speed to the second photoresist easily.
In one embodiment, the first preset distance is equal with the second preset distance.Like this, the round and smooth edge formed can be quarter circular arc, makes the sidewall of round and smooth edge and groove form level and smooth transition.
In one embodiment, in step 5, with plasma etching, step is etched into round and smooth edge, the etching gas that plasma etching uses is CHF
3, CF
4with the admixture of gas of Ar, wherein CHF
3amount of substance and CF
4the ratio of amount of substance be (3-7): 3, CHF
3amount of substance be 5:(12-24 with the ratio of the amount of substance of Ar).Preferably, when mask is mask, the thickness of mask is greater than the first preset distance or the second preset distance.Like this, during step is etched into round and smooth edge, earth silicon mask can protect silicon substrate not to be damaged.
Compared with prior art; the invention has the advantages that: (1) is according to method of the present invention; armor coated in groove be etched into groove in silicon substrate after; during carrying out groove drift angle corners; the sidewall of groove can be protected not to be damaged, to this also simplifies the construction process of trench gate.(2) process cycle of method of the present invention is short, and cost is lower.
Accompanying drawing explanation
Also will be described in more detail the present invention with reference to accompanying drawing based on embodiment hereinafter.Wherein:
Fig. 1 show schematically show by way of illustration to 7 and implements method step of the present invention.
In the accompanying drawings, identical parts use identical Reference numeral.Accompanying drawing is not according to the ratio of reality.
Embodiment
Below in conjunction with accompanying drawing, method of the present invention is described further.
Step one, the surface of silicon substrate 1 forms mask 2.Become groove 3 through mask 2 towards the etched inside of silicon substrate 1, the region adjacent with the sidewall 4 of groove 3 of mask 2 is formed around district 5.As shown in Figure 1.
In one embodiment, by heat growth mode, silicon substrate 1 superficial growth silicon dioxide layer and form mask 2.Also mask 2 can be formed at the deposited on silicon silicon nitride layer of silicon substrate 1.
In a preferred embodiment, groove 3 is formed by following manner: on mask 2, arrange the first photoresist 6.Then by step removing pre-position first photoresists such as exposure, developments.Then, under the protection of the first photoresist 6, form groove 3 in the mode of plasma etching in the inside of silicon substrate 1.Like this, around district 5 having retained the first photoresist 6, as shown in Figure 1.
Step 2, perpendicular to the sidewall 4 of groove 3, etching is around district 5.The step 8 of the first preset distance L1 is formed between the edge around district 5 after the etching and the drift angle 7 of groove 3.As shown in Figure 2.After formation step 8, then remove the first photoresist 6.As shown in Figure 3.
As shown in Figure 1, after formation groove 3, only expose in the side-walls with groove 3 around district 5, and its upper part is covered by the first photoresist 6.In this case, the mode of wet etching can be used etch this around district 5, even if laterally advance away from groove 3 around district 5, material is thus formed step 8, as shown in Figure 2.The speed of wet etching is isotropic, therefore can ensure that step 8 is all equal apart from the distance of groove 3 in all directions.When around district 5 (that is, mask 2) for silicon nitride layer time, wet etching use corrosive liquid be phosphoric acid.When around district 5 (that is, mask 2) for silicon dioxide layer time, the corrosive liquid that wet etching uses be hydrofluoric acid the aqueous solution or BOE solution.These corrosive liquids are all, known by those skilled in the art, repeat no more here.The selectivity of these corrosive liquids is also very good, only can corrode around district 5, and can not the sidewall of erosion grooves 3 and diapire, thus avoids the destruction to groove 3.
After formation step 8, the first photoresist 6 is removed, as shown in Figure 3.Usually, suitable Exposure mode can be selected to be removed completely by the first photoresist 6, and this is known by those skilled in the art, repeats no more here.
Step 3: on the surface after step 2 process of silicon substrate 1 armor coated 10.As shown in Figure 4, groove 3 not only all fills up by protective layer 10, and completely covers around district 5.In one embodiment, protective layer 10 is second photoresists.
Step 4: by around the protective layer removing in district 5 and step 8, and remove the protective layer of the part in groove 3, until be the second preset distance L2 between the surface 11 of protective layer 10 in groove 3 and the drift angle 7 of groove 3.As shown in Figure 5.
In one embodiment, protective layer 10 is removed in the mode of the plasma etching of oxygen effect etching gas.Like this, in the process of removing protective layer 10, can stop etching at any time according to the surplus of groove 3 inner protective layer 10, avoiding problems the risk all removed by the protective layer 10 in groove 3, and the length of the second preset distance L2 can be controlled.In a preferred embodiment, the first preset distance L1 is equal with the second preset distance L2.
In addition; use oxygen etch second photoresist (namely; protective layer 10) time; mask 2 (or around district 5) can stop oxygen to penetrate in silicon substrate 1; and the exposed silicon in step 8 place can react with oxygen and generates silica coating and can deeply infiltrate to the inside of silicon substrate 1 by anti-block, and silicon substrate 1 can be made like this not to be damaged on the whole.
In a preferred embodiment, also including content in oxygen (that is, etching gas) is hydrogen outside explosive range.More preferably, also nitrogen is included.In etching process, hydrogen can with oxygen reaction and heat release, and this helps raising etching speed.For etching, nitrogen is inert gas, by the content of nitrogen in etching gas, can control etching speed easily.Thus, by the content of hydrogen and nitrogen in Collaborative Control etching gas, can be conveniently implemented in the different moment has different etching speeds, to adapt to different needs.
Step 5: under the protection around district 5 after protective layer 10 and etching, step 8 is etched to round and smooth edge 13.As shown in Figure 6.
In one embodiment, by plasma etching, step 8 can be etched into round and smooth edge 13, the etching gas used is CHF
3, CF
4with the admixture of gas of Ar, wherein CHF
3amount of substance and CF
4the ratio of amount of substance be (3-7): 3, CHF
3amount of substance be 5:(12-24 with the ratio of the amount of substance of Ar).Preferably, when being mask 2 for silicon dioxide layer, the thickness of mask 2 is greater than the first preset distance L1 or the second preset distance L2.In one embodiment, the thickness of mask 2 is 0.03 μm-0.02 μm, and the first preset distance L1 is 0.003 μm-0.015 μm.Like this; even if etching gas can etching mask 2; but the thickness due to mask 2 is greater than the first preset distance L1; therefore when step 8 is etched into round and smooth edge; mask 2 still exists; thus all silicon substrate 1 is played a protective role in the whole process of etch step 8, even if after even step 8 is etched into round and smooth edge, mask 2 still exists.When being mask 2 for silicon nitride layer, due to CHF
3, CF
4with the admixture of gas of Ar to the etching speed of silicon nitride much smaller than the etching speed to silicon, therefore silicon nitride layer can more effectively protect silicon substrate 1.
Preferably, finally the protective layer 10 in groove 3 is removed completely, carry out subsequent technique to facilitate, as shown in Figure 7.
Although invention has been described with reference to preferred embodiment, without departing from the scope of the invention, various improvement can be carried out to each step, or the every technical characteristic mentioned in each embodiment all can be combined in any way.The present invention is not limited to specific embodiment disclosed in literary composition, but comprises all technical schemes fallen in the scope of claim.
Claims (10)
1. a trench gate engraving method, comprising:
Step one: form mask on the surface of silicon substrate, become groove through described mask towards the etched inside of silicon substrate, the region adjacent with the sidewall of described groove of described mask is formed around district,
Step 2: perpendicular to described groove sidewall etch described in around district, form the step of the first preset distance between the drift angle of the edge around district after the etching and described groove,
Step 3: armor coated on the surface after step 2 process of described silicon substrate,
Step 4: removing is described around the protective layer in district and step, and removes the protective layer of the part in described groove, until be the second preset distance between the surface of protective layer in groove and the drift angle of described groove,
Step 5: after described protective layer and described etching around under the protection in district, described step is etched to round and smooth edge.
2. method according to claim 1, is characterized in that, in described step one, is also provided with the first photoresist described around in district.
3. method according to claim 2, is characterized in that, in described step 2, corrosion etches described around district in a wet process; After the described step of formation, remove described first photoresist.
4. method according to claim 3, is characterized in that, described mask is silicon nitride layer or silicon dioxide layer; When being mask for silicon nitride layer, the corrosive liquid that described wet etching uses is phosphoric acid; When being mask for silicon dioxide layer, the aqueous solution that the corrosive liquid that described wet etching uses is hydrofluoric acid.
5. the method according to any one of claim 1 to 4, is characterized in that, in described step 3, the protective layer used is the second photoresist.
6. method according to claim 5, is characterized in that, the mode removing described second photoresist is plasma etching, and the etching gas used is oxygen.
7. method according to claim 6, is characterized in that, described etching gas also includes nitrogen and the hydrogen outside explosive range.
8. method according to claim 4, is characterized in that, in described step 5, with plasma etching, described step is etched into round and smooth edge, and the etching gas that described plasma etching uses is CHF
3, CF
4with the admixture of gas of Ar, wherein CHF
3amount of substance and CF
4the ratio of amount of substance be (3-7): 3, CHF
3amount of substance be 5:(12-24 with the ratio of the amount of substance of Ar).
9. method according to claim 8, is characterized in that, described first preset distance is equal with described second preset distance.
10. method according to claim 9, is characterized in that, when described mask is silicon dioxide layer, the thickness of described mask is greater than described first preset distance or the second preset distance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510043716.4A CN104658902B (en) | 2015-01-28 | 2015-01-28 | Trench gate engraving method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510043716.4A CN104658902B (en) | 2015-01-28 | 2015-01-28 | Trench gate engraving method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104658902A true CN104658902A (en) | 2015-05-27 |
| CN104658902B CN104658902B (en) | 2018-05-08 |
Family
ID=53249883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510043716.4A Active CN104658902B (en) | 2015-01-28 | 2015-01-28 | Trench gate engraving method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104658902B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986992A (en) * | 2019-05-23 | 2020-11-24 | 芯恩（青岛）集成电路有限公司 | Groove etching method |
| CN114121905A (en) * | 2022-01-26 | 2022-03-01 | 晶芯成(北京)科技有限公司 | MIM capacitor and forming method thereof |
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| CN104282543A (en) * | 2013-07-11 | 2015-01-14 | 上海华虹宏力半导体制造有限公司 | Groove gate applied to groove-type MOS device and manufacturing method thereof |
-
2015
- 2015-01-28 CN CN201510043716.4A patent/CN104658902B/en active Active
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| US5956598A (en) * | 1998-07-02 | 1999-09-21 | United Microelectronics Corp. | Method for fabricating a shallow-trench isolation structure with a rounded corner in integrated circuit |
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| CN103035561A (en) * | 2012-08-31 | 2013-04-10 | 上海华虹Nec电子有限公司 | Process method for forming inclined angle at top of deep groove |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986992A (en) * | 2019-05-23 | 2020-11-24 | 芯恩（青岛）集成电路有限公司 | Groove etching method |
| CN114121905A (en) * | 2022-01-26 | 2022-03-01 | 晶芯成(北京)科技有限公司 | MIM capacitor and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104658902B (en) | 2018-05-08 |
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