CN104655930A - Alternating current phase recognition instrument and alternating current phase recognition method - Google Patents
Alternating current phase recognition instrument and alternating current phase recognition method Download PDFInfo
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- CN104655930A CN104655930A CN201510088315.0A CN201510088315A CN104655930A CN 104655930 A CN104655930 A CN 104655930A CN 201510088315 A CN201510088315 A CN 201510088315A CN 104655930 A CN104655930 A CN 104655930A
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Abstract
The invention discloses an alternating current phase recognition instrument and an alternating current phase recognition method, and belongs to the field of power detection instruments. The alternating current phase recognition instrument comprises a phase recognition instrument main unit (2) connected with alternating current and a phase recognition instrument auxiliary unit (5) which is in wireless communication with the phase recognition instrument main unit. The alternating current phase recognition method comprises the following steps: (1), the phase recognition instrument auxiliary unit (5) sends a request instruction to the phase recognition instrument main unit (2); step 2, the phase recognition instrument main unit (2) receives the request instruction sent by the phase recognition instrument auxiliary unit (5), acquires the phase data of phase lines connected to the phase recognition instrument auxiliary unit (5), and returns the phase data to the phase recognition instrument auxiliary unit (5); step 3, the phase recognition instrument auxiliary unit (5) executes a phase judging method for phase judgment and display after receiving the phase data returned by the phase recognition instrument main unit (2). By means of the alternating current phase recognition instrument and the alternating current phase recognition method, the phases can be judged quickly and accurately, three-phase load distribution is performed according to the load, and load of the alternating current three-phase lines is balanced.
Description
Technical field
Alternating current phases identifier and alternating current phases recognition methods, belong to electric power detecting instrument field.
Background technology
In the prior art, low-voltage network triple-phase line when user class wiring, has been hard to tell the A phase of alternating current, B phase and C phase after picking out enter terminal block case from platform district transformer, can only arbitrarily wiring.Due to three-phase can not be balanced electricity consumption, causes a certain phase or two-phase overload, cause three-phase current unbalance, so that line loss increases, and even burns transformer, causes fire etc., cause heavy losses to the country and people.
Summary of the invention
The technical problem to be solved in the present invention is: overcome the deficiencies in the prior art, there is provided a kind of automatically to identify and show the phase line information of three-phase alternating current, user side is facilitated to carry out three-phase load distribution by payload, make the load balancing of alternating current triple-phase line, avoid three characteristics of the middle term current imbalance and cause dangerous alternating current phases identifier, and swift with judgement, the alternating current phases recognition methods that accuracy is high.
The technical solution adopted for the present invention to solve the technical problems is: this alternating current phases identifier, comprise transformer and export ground three-phase and four-line alternating current, it is characterized in that: the phase identification instrument extension set being provided with phase identification instrument main frame and wireless telecommunications with it, in the operation circuit of the three-phase firewire of described three-phase and four-line alternating current and zero line access phase identification instrument extension set, in the control circuit of at least one phase firewire of three-phase and four-line alternating current and zero line access phase identification instrument main frame.
Preferably, the control circuit of described phase identification instrument extension set comprises the first CPU (central processing unit), the first clock synchronization module, first phase generation module, the first short-term transceiver module, charactron module and button; First clock synchronization module is connected with the input end of the first CPU (central processing unit), first communication module and the first CPU (central processing unit) interconnected, first phase generation module is connected with the input end of the first CPU (central processing unit), described alternating current access first phase generation module, the output terminal of the first CPU (central processing unit) connects charactron module and can the button of input control order simultaneously.
Preferably, the control circuit of described phase identification instrument main frame comprises the second CPU (central processing unit), second clock synchronization module, second phase generation module and the second short-term transceiver module, second clock synchronization module is connected with the input end of the second CPU (central processing unit), second communication module and the second CPU (central processing unit) interconnected, second phase generation module is connected with the input end of the second CPU (central processing unit).
Preferably, in the control circuit of described phase identification instrument main frame and phase identification instrument extension set, be also provided with the indicating lamp module for indicating duty.
A kind of alternating current phases recognition methods, is characterized in that: comprise the steps:
Step 1, the control circuit of phase identification instrument extension set performs extension set workflow and sends request instruction to phase identification instrument main frame;
Step 2, the control circuit of phase identification instrument main frame performs the phase data that host work flow process obtains the phase line accessed in it, and returns phase identification instrument extension set after receiving the request instruction that phase identification instrument extension set sends;
Step 3, after phase identification instrument extension set receives the phase data that phase identification instrument main frame returns, the phase data obtained in conjunction with himself, excute phase determination methods judges each phase place and shows;
Described phase data comprises: time scale information when each phase line is carried out to count value that acquisition counter method obtains and carried out acquisition counter method.
Preferably, described extension set workflow, comprises the steps:
Step 1001, pushes button;
When needs carry out phase identification, press the button be connected with the first CPU (central processing unit) in phase identification instrument extension set control circuit;
Step 1002, determines real-time time;
After the first CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by the first clock synchronization module;
Step 1003, sends request instruction;
First CPU (central processing unit) sends request instruction by the first communication module in phase identification instrument extension set control circuit to phase identification instrument main frame;
Step 1004, acquisition phase information;
After request instruction sends by the first CPU (central processing unit), wait the phase data that pending phase identification instrument main frame returns according to host work flow processing; First CPU (central processing unit) is simultaneously starting point with real-time time, carries out acquisition counter in the whole branch of the continuous print of two after this according to acquisition counter method to three-phase phase;
Step 1005, whether main frame returns phase data;
First CPU (central processing unit) judges whether to receive in the presetting time phase data that phase identification instrument main frame returns, if have received the phase data that phase identification instrument main frame returns, perform step 1006, if do not receive the phase data that phase identification instrument main frame returns, return and perform step 1002;
Step 1006, whether time scale information conforms to;
First CPU (central processing unit) judges whether the time scale information in the phase data that phase identification instrument main frame returns matches with the time scale information in the image data collected with himself, if coupling, performs step 1007, if do not mated, returns step 1002;
Step 1007, carries out phase place judgement;
Count value in the phase information that first CPU (central processing unit) reading phase identification instrument main frame returns, and the count value in the phase data of the three-phase phase himself obtained by acquisition counter method, according to phase place determination methods, each phase phase place is judged;
Step 1008, carries out phase place display;
First CPU (central processing unit), according to the three-phase phase judged, is shown by charactron module.
Preferably, described host work flow process, comprises the steps:
Step 2001, receives extension set request;
The second CPU (central processing unit) in phase identification instrument host computer control circuit receives by the second communication module the request instruction that phase identification instrument extension set sends;
Step 2002, determines real-time time;
After the second CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by second clock synchronization module;
Step 2003, record A phase phase place;
Second CPU (central processing unit) is carried out acquisition counter by acquisition counter method to access phase line wherein when starting for next whole point and is obtained phase data;
Step 2004, sends phase data;
The phase data obtained is back to phase identification instrument extension set by the second processing unit.
Preferably, described acquisition counter method is: carry out counting with fixed frequency and gather the rising edge of corresponding phase line or negative edge, stops counting, obtain described count value after rising edge or negative edge arrive.
Preferably, described fixed frequency is 100 μ s.
Preferably, described phase place determination methods is:
Step a, the count value that phase identification instrument extension set is sent into according to phase identification instrument main frame determines A phase phase line;
Step b, judges according to one of following criterion:
Criterion 1:A phase count value is greater than the count value of other two phase line, then other two phase lines fall into a trap numerical value minimum for B phase, another is C phase;
Criterion 2:A phase count value is greater than the enumeration data of a phase wherein and is less than the enumeration data of another phase, then what count value was minimum is C phase, and another is B phase;
Criterion 3:A phase count value is less than other two-phase enumeration data, then other two phase line fall into a trap numerical value little for B phase, what count large numerical value is C phase;
Criterion 4: when A phase count value is 0, with criterion 3, when count value is 195 ~ 205, with criterion 1.
Compared with prior art, the beneficial effect that the present invention has is:
1, by this alternating current phases identifier and alternating current phases recognition methods, can judge the phase place of the alternating current three-phase firewire of terminal block end fast and accurately, facilitate user side wiring, make the load balancing of alternating current triple-phase line, avoid three characteristics of the middle term current imbalance and cause danger.
2, carrying out wireless telecommunications with the form of note between phase identification instrument main frame and phase identification instrument extension set, communication fast and stable, eliminating because blocking or distance and the Communications failure caused.
3, when phase identification instrument main frame and phase identification instrument extension set to be undertaken pair by GPS simultaneously, ensure that the accuracy to looking.
Phase identification instrument carry out phase place judge time, by the mode record phase information of counting, involved packet is less, convenient sends.
4, by phase generating module, the sine wave of alternating current is converted to square wave, facilitates CPU (central processing unit) collection.
5, directly phase place is indicated by charactron module, observe more directly perceived, by indicating lamp module, duty is indicated, work more reliable.
6, the pps pulse per second signal sent into by GPS and rs 232 serial interface signal were accurately judged the time, and timing is more accurate.
Accompanying drawing explanation
Fig. 1 is alternating current phases identifier connection diagram.
Fig. 2 is alternating current phases identifier extension set control circuit functional-block diagram.
Fig. 3 is alternating current phases identifier host computer control circuit block diagram.
Fig. 4 is alternating current phases identifier CPU (central processing unit) circuit theory diagrams.
Fig. 5 ~ 6 are alternating current phases identifier communication module circuit theory diagrams.
Fig. 7 is alternating current phases identifier indicating lamp module circuit theory diagrams.
Fig. 8 is alternating current phases identifier phase generating module circuit theory diagrams.
Fig. 9 ~ 10 are alternating current phases identifier charactron modular circuit schematic diagram.
Figure 11 ~ 12 are alternating current phases identifier supply module circuit theory diagrams.
Figure 13 is alternating current phases identifier clock synchronization module circuit theory diagrams.
Figure 14 is alternating current phases recognition methods extension set workflow diagram.
Figure 15 is alternating current phases recognition methods host work process flow diagram.
Figure 16 is alternating current phases recognition methods phase place decision flow chart.
Figure 17 is alternating current phases recognition methods alternating current phases schematic diagram.
Figure 18 is alternating current phases recognition methods embodiment 2 phase identification instrument extension set workflow diagram.
Figure 19 is alternating current phases recognition methods embodiment 2 phase identification instrument host work process flow diagram.
Wherein: 1, transformer 2, phase identification instrument main frame 3, power transmission cable 4, terminal block case 5, phase identification instrument extension set.
Embodiment
Fig. 1 ~ 17 are most preferred embodiments of the present invention, and below in conjunction with accompanying drawing 1 ~ 19, the present invention will be further described.
Embodiment 1:
As shown in Figure 1, in transmission line of electricity, the power transmission cable 3 of three-phase four-wire system picks out in transformer 1, is connected in terminal block case 4.In the alternating current access phase identification instrument main frame 2 of drawing in the transformer 1 of power distribution network end, in the alternating current access phase identification instrument extension set 5 of drawing in user junction box 4.Because phase identification instrument main frame 2 is connected to power distribution network one end, therefore phase identification instrument main frame 2 can judge A, B, C three-phase phase line of alternating current, and in terminal block case 4 side, cannot distinguish A, B, C three-phase phase line of alternating current, but at synchronization, the phase information on phase identification instrument main frame 2 and phase identification instrument extension set 5 is identical.In transformer 1 side, can A, B, C three-phase phase line of alternating current all be accessed in phase identification instrument main frame 2, also can select wherein a phase or two-phase access, in this alternating current phases identifier, preferably only access A phase firewire and zero line.Wirelessly communication is carried out between phase identification instrument main frame 2 and phase identification instrument extension set 5.
As shown in Figure 2, phase identification instrument extension set 5 control circuit comprises the first CPU (central processing unit), the first clock synchronization module, first phase generation module, the first short-term transceiver module, the first indicating lamp module, charactron module and button.First clock synchronization module is connected with the input end of the first CPU (central processing unit), and the first CPU (central processing unit) obtains real-time precise time by the first clock synchronization module.First communication module and the first CPU (central processing unit) interconnected, the first CPU (central processing unit) carries out communication by the first communication module.First phase generation module is connected with the input end of the first CPU (central processing unit), and alternating current access first phase generation module, the first central processing module gathers the phase information of alternating current three-phase phase line by first phase generation module.The output terminal of the first CPU (central processing unit) connects the first indicating lamp module and charactron module simultaneously, is indicated, shown by charactron module to phase information by the duty of the first indicating lamp module to phase identification instrument extension set 5.The input end of the first central processing module is connected with simultaneously can the button of input control order.
As shown in Figure 3, phase identification instrument main frame 2 control circuit and phase identification instrument extension set 5 circuit form and connected mode similar, comprise the second CPU (central processing unit), second clock synchronization module, second phase generation module, the second short-term transceiver module and the second indicating lamp module.Second clock synchronization module is connected with the input end of the second CPU (central processing unit), and the second CPU (central processing unit) obtains real-time precise time by second clock synchronization module.Second communication module and the second CPU (central processing unit) interconnected, the second CPU (central processing unit) carries out communication by the second communication module.Second phase generation module is connected with the input end of the second CPU (central processing unit), and alternating current access second phase generation module, the second central processing module gathers the phase information of alternating current A phase phase line by second phase generation module.The output terminal of the second CPU (central processing unit) is connected with the second indicating lamp module indicated the duty of phase identification instrument main frame 2 simultaneously.In this alternating current phases identifier, the form by note between phase identification instrument main frame 2 and phase identification instrument extension set 5 carries out communication, also by other forms, as: the mode such as short-distance wireless, power line carrier.
First clock synchronization module and second clock synchronization module adopt GPS module to realize, and the pps pulse per second signal sent into by GPS and rs 232 serial interface signal were accurately judged the time.Identical supply module is also provided with the control circuit of phase identification instrument extension set 5 at phase identification instrument main frame 2.
As shown in Figure 4, the single-chip microcomputer U1 of to be model be STM32F103C8T6 that adopts of CPU (central processing unit).The 17 pin series connection button KEY1 ground connection of single-chip microcomputer U1,5 pin and 6 pin series capacitance C5 and electric capacity C6 ground connection is respectively simultaneously in parallel by crystal oscillator Y1 between 5 pin and 6 pin.The 7 pin series capacitance C17 ground connection of single-chip microcomputer U1,44 pin resistance in series R2 ground connection, 20 pin resistance in series R1 ground connection.24 pin of single-chip microcomputer U1,36 pin, 48 pin are connected 3.3V direct supply with 9 pin, 23 pin, 35 pin, 47 pin and 8 pin ground connection.In this alternating current phases identifier, the first CPU (central processing unit) and the second CPU (central processing unit) adopt identical circuit form.
As shown in Fig. 5 ~ 6, in communication module, adopt model to be the GSM communication chip U4 of M35, and in the SIM card module U3 is connected with GSM communication chip U4, SIM card module U3, loading SIM card is connected with GSM communication chip U4 and realize communication.10 pin of GSM communication chip U4 simultaneously and connect one end of electric capacity C18 and the collector of triode Q1, the emitter of triode Q1 and the other end ground connection of electric capacity C18.One end of the base stage of triode Q1 parallel resistance R6, resistance R9 simultaneously, the other end ground connection of resistance R9, the other end of resistance R6 connects 29 pin of single-chip microcomputer U1.The 19 pin series capacitance C19 ground connection of GSM communication chip U4.The 21 pin resistance in series R18 of GSM communication chip U4 connect 22 pin of single-chip microcomputer U1, one end of 22 pin of GSM communication chip U4 simultaneously parallel resistance R19 ~ R20, the other end ground connection of resistance R20, the other end of resistance R19 connects 21 pin of single-chip microcomputer U1,24 pin resistance in series R4 ground connection.27 pin of GSM communication chip U4 connect 1 pin of SIM card module U3, connect 2 pin, 7 pin, 3 pin of SIM card module U3 after 28 pin ~ 30 pin difference resistance in series R14 ~ R12.The 1 pin resistance in series R3 of antenna U2 connects 39 pin of GSM communication chip U4,3 ~ 4 pin ground connection.31 pin of integrated chip, 35 ~ 38 pin, 40 pin ground connection together, 33 ~ 34 pin connect power vd D.
1 pin ~ 3 pin of SIM card module U3,7 pin series capacitance C10 ~ C7 ground connection respectively, 6 pin pass through electric capacity C10 ground connection simultaneously, the direct ground connection of 5 pin.In this alternating current phases identifier, the first communication module and the second communication module adopt identical circuit form.
As shown in Figure 7, in indicating lamp module, power supply 3.3V positive pole simultaneously and the anode of running fire optical diode LD1 ~ LD5, one end of the negative electrode of light emitting diode LD1 ~ LD5 contact resistance R21, resistance R40 ~ 43 simultaneously, the collector of resistance R21 connecting triode Q2, the grounded emitter of triode Q2,13 pin of parallel resistance R10 between base stage and emitter, the GSM communication chip U4 that base stage is connected by resistance R7 simultaneously.The other end ground connection of resistance R40, the other end of resistance R41 ~ 43 connects 33,32,10 pin of single-chip microcomputer U1 respectively.In this alternating current phases identifier, the first indicating lamp module, the second indicating lamp module adopt same circuit to arrange.Light emitting diode LD1 ~ LD5 is respectively: the running LED of GSM communication chip U4, supply module working station indicator, communications status pilot lamp, running LED and clock synchronization module pilot lamp.
As shown in Figure 8, phase generating module comprises transformer PT1 ~ PT3, and model is the integrated chip U6 ~ U7 of MCP607.1 ~ 4 pin of connection terminal J3 is respectively used to C, B, A three-phase firewire and the zero line N that access three-phase four-wire system alternating current.With the first siding ring of zero line N difference connection transformer PT1 after live wire C resistance in series R25, the second siding ring of transformer PT1 is while connect 2 pin of integrated chip U6, ground connection after another side resistance in series R34 ~ 35, electric capacity C26, after the 1 pin resistance in series R31 of integrated chip U6 simultaneously and connect single-chip microcomputer U1 15 pin and between resistance R35, electric capacity C26.Between the second siding ring of transformer PT1 simultaneously and be connected with resistance R28, electric capacity C25.
With the first siding ring of zero line N difference connection transformer PT2 after live wire B resistance in series R26, the second siding ring of transformer PT2 is while connect 7 pin of integrated chip U6, ground connection after another side resistance in series R36 ~ 37, electric capacity C29, after the 8 pin resistance in series R32 of integrated chip U6 simultaneously and connect single-chip microcomputer U1 14 pin and between resistance R37, electric capacity C29.Between the second siding ring of transformer PT2 simultaneously and be connected with resistance R29, electric capacity C27.
With the first siding ring of zero line N difference connection transformer PT3 after live wire A resistance in series R27, the second siding ring of transformer PT3 is while connect 2 pin of integrated chip U7, ground connection after another side resistance in series R38 ~ 39, electric capacity C30, after the 1 pin resistance in series R33 of integrated chip U6 simultaneously and connect single-chip microcomputer U1 11 pin and between resistance R39, electric capacity C30.Between the second siding ring of transformer PT3 simultaneously and be connected with resistance R30, electric capacity C28.
In this alternating current phases identifier, first phase generation module, second phase generation module can adopt same circuit to arrange, second phase generation module is owing to preferably accessing A phase phase place, therefore also only can arrange as the transformer PT3 in Fig. 7, integrated chip U7 and associated peripheral circuits realize, by phase generating module, the sine wave signal of alternating current is adjusted to square-wave signal.
As shown in Fig. 9 ~ 10, display module comprises charactron SEG1 and in order to drive the integrated chip U8 of charactron SEG1.11 pin of integrated chip U8,12 pin and 14 pin are connected with 42 pin of single-chip microcomputer U1,43 pin and 41 pin respectively.10 pin of integrated chip U8 connect 5V direct supply, and 13 pin ground connection, are parallel with electric capacity C33 between 10 pin and 13 pin simultaneously.The d terminals of charactron SEG1 are connected after the 1 pin resistance in series R47 of integrated chip U8; The a terminals of charactron SEG1 are connected after the 2 pin resistance in series R44 of integrated chip U8; The f terminals of charactron SEG1 are connected after the 3 pin resistance in series R49 of integrated chip U8; The dp terminals of charactron SEG1 are connected after the 4 pin resistance in series R51 of integrated chip U8; The c terminals of charactron SEG1 are connected after the 5 pin resistance in series R46 of integrated chip U8; The g terminals of charactron SEG1 are connected after the 6 pin resistance in series R50 of integrated chip U8; The b terminals of charactron SEG1 are connected after the 7 pin resistance in series R45 of integrated chip U8; The e terminals of charactron SEG1 are connected after the 15 pin resistance in series R48 of integrated chip U6.
Charactron SEG1 employing model is four common cathode charactrons of SR420361N, and integrated chip U8 employing model is the charactron driving chip of 74HC595.
As shown in figure 11, the galvanic positive pole of the 5V introduced by connection terminal J1 is connected with 2 pin of integrated chip U5, the 3 pin ground connection of integrated chip U5, simultaneously in parallel by electric capacity C20, electric capacity C14 between 2 pin with 3 pin, is parallel with resistance R11 between 2 pin and 1 pin.The collector of 1 pin of integrated chip U5 simultaneously triode Q3 in parallel, the grounded emitter of triode Q3, between the base stage that resistance R24 and resistance R8 is connected in parallel on triode Q7 after connecting and emitter, 45 pin of single-chip microcomputer U1 are connected in parallel between resistance R24 and resistance R8.One end of 5 pin of integrated chip U5 simultaneously parallel resistance R22 ~ 23, the other end of resistance R22 is connected in parallel to 4 pin of integrated chip U5.Electric capacity C22, electric capacity C11 ~ C12, electric capacity 15, electric capacity C35 ~ C38 is parallel with between 4 pin of integrated chip U5 and the other end of resistance R23.The other end ground connection simultaneously of resistance R23,4 pin of self integrated chip U5 draw direct supply VDD.The model of integrated chip U8 is SPX29152T5.
As shown in figure 12,5V DC power anode connects between 1 pin of the 1 pin integrated chip U9 of integrated chip U9,3 pin and is parallel with electric capacity C23, electric capacity C16.The 3 pin ground connection of integrated chip U7,2 pin and 4 pin are the positive pole of 3.3V direct supply, 2 pin of integrated chip U7, are parallel with electrochemical capacitor C34, electric capacity C24 and electric capacity C1 ~ C4 between 4 pin and earth terminal simultaneously.Integrated chip U7 model is SPX1117-3.3V, for 5V direct supply is converted to 3.3V direct supply.
In this alternating current phases identifier, the first clock synchronization module, second clock synchronization module adopt GPS to carry out time synchronized simultaneously.As shown in figure 13, connection terminal J2 is for accessing the GPS module that model is VK16U6, and 1 ~ 6 pin of connection terminal J2 respectively corresponding model is A ~ F pin of the GPS module of VK16U6.The 1 pin resistance in series R5 of connection terminal J2 connects 10 pin, the 2 pin connection power supply 3.3V of single-chip microcomputer U1, and 3 pin of connection terminal J2,4 pin connect 13 pin, 12 pin of single-chip microcomputer U1 respectively, and the 5 pin ground connection of connection terminal J2,6 pin are unsettled.
The pps pulse per second signal that CPU (central processing unit) is sent into by clock synchronization module and rs 232 serial interface signal accurately judged the time.Its ultimate principle is: when pulse per second (PPS) rising edge arrives, and add the clock data that one, GPS serial ports brings second and only do calibration use, can ensure that system clock accuracy reaches hundreds of nanosecond like this, timing is very accurate.
The recognition methods of this alternating current phases, the identification realizing alternating current phases is coordinated by phase identification instrument main frame 2 and phase identification instrument extension set 5, its theoretical foundation and principle are: be 50Hz in the frequency of China's alternating current, namely the time in each cycle is 20ms, phase differential due to A, B, C three-phase firewire is 120 °, therefore adjacent two phase firewire time phase difference 20/3 ≈ 6.7ms.In the recognition methods of this alternating current phases, owing to the sine wave of alternating current being nursed one's health as square wave by phase generating module, therefore CPU (central processing unit) counts for frequency with 100 μ s, preferably gathers the rising edge of each phase line, also can gather the negative edge of each phase line.As from the foregoing, in one-period, each phase phase line count value is: 20ms/100 μ s=200, and due to adjacent two phase firewire time phase difference 6.7ms, therefore the count value of adjacent two phase line rising time differences is: 6.7ms/100 μ s=67.Namely, when carrying out acquisition counter to the rising edge of three-phase phase line, the count value of A, B, C three-phase phase line rising edge difference is followed successively by 67.As mentioned above, the phase information on synchronization phase identification instrument main frame 2 and phase identification instrument extension set 5 is identical.And preferably only gather A phase phase place (namely only acquisition counter being carried out to A phase rising edge) at phase identification instrument main frame 2, therefore when phase identification instrument extension set 5 collect the three-phase rising edge of synchronization count value and get phase identification instrument main frame 2 gather A phase phase count after, A phase phase place can be judged immediately, and the phase count of the other two-phase that can gather according to phase identification instrument extension set 5 self, the phase place of other two-phase can be judged.
As shown in figure 14, the workflow of phase identification instrument extension set 5, comprises the steps:
Step 1001, pushes button;
When needs carry out phase identification, staff presses the button be connected with the first CPU (central processing unit);
Step 1002, determines real-time time;
After the first CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by the first clock synchronization module;
The pps pulse per second signal that first CPU (central processing unit) is sent into by the first clock synchronization module and rs 232 serial interface signal accurately judged the time.Its ultimate principle is: when pulse per second (PPS) rising edge arrives, and add the clock data that one, GPS serial ports brings second and only do calibration use, can ensure that system clock accuracy reaches hundreds of nanosecond like this, timing is very accurate.
Step 1003, sends request instruction;
First CPU (central processing unit) is crossed the first communication module and is sent request instruction to phase identification instrument main frame 2;
Step 1004, acquisition phase information;
After request instruction sends by the first CPU (central processing unit), wait the phase data that pending phase identification instrument main frame 2 returns according to its workflow; First CPU (central processing unit) is simultaneously starting point with real-time time, carries out acquisition counter in the whole branch of the continuous print of two after this to the rising edge of the three-phase phase time that arrives;
Citing: the first CPU (central processing unit) is 1h:01m:40s being collected the enforcement time by the first clock synchronization module, first CPU (central processing unit) starts at 1h:02m:00s and 1h:03m:00s, carries out acquisition counter respectively to the arrival time of the rising edge of three-phase phase.
Step 1005, whether main frame returns phase data;
First CPU (central processing unit) judges whether to receive in the presetting time phase data that phase identification instrument main frame 2 returns, if have received the phase data that phase identification instrument main frame 2 returns, perform step 1006, if do not receive the phase data that phase identification instrument main frame 2 returns, return and perform step 1002;
Step 1006, whether time scale information conforms to;
Time scale information in the phase data that first CPU (central processing unit) reading phase identification instrument main frame 2 returns, judge whether time corresponding to this time scale information and the time himself gathered match, if the acquisition time of phase identification instrument main frame 2 and the time self gathered match, perform step 1007, if do not mated, return step 1002;
Step 1007, carries out phase place judgement;
First CPU (central processing unit) reads the rising edge count value of the A phase phase place that phase identification instrument main frame 2 returns, and the three-phase phase rising edge count value that himself acquisition counter arrives, and judges flow process, judge each phase phase place according to phase place;
Step 1008, carries out phase place display;
First CPU (central processing unit), according to the three-phase phase judged, is shown by charactron module.
As shown in figure 15, the workflow of phase identification instrument main frame 2, comprises the steps:
Step 2001, receives extension set request;
Second CPU (central processing unit) receives by the second communication module the request instruction that phase identification instrument extension set 5 sends;
Step 2002, determines real-time time;
After the second CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by second clock synchronization module;
The pps pulse per second signal that second CPU (central processing unit) is sent into by second clock synchronization module equally and rs 232 serial interface signal accurately judged the time, and its ultimate principle is identical.
Step 2003, record A phase phase place;
After second CPU (central processing unit), take real-time time as starting point, between next the whole point arrival starting the rising edge of A phase firewire, carry out acquisition counter;
Step 2004, sends phase data;
Time scale information corresponding to the count value of A phase firewire rising edge arrival time and acquisition time is together back to phase identification instrument extension set 5 as phase data by the second processing unit.
As shown in figure 16, in phase identification instrument extension set 5, carry out phase place when judging, it judges that flow process is as follows:
Step 3001, Receiving Host data;
Phase identification instrument extension set 5 receives the A phase phase data that phase identification instrument main frame 2 returns;
Step 3002, carries out comparing;
The count value of the A phase rising edge that phase identification instrument main frame 2 acquisition counter obtains by phase identification instrument extension set 5 and the count value himself putting the three-phase alternating current that acquisition technique obtains at one time are compared;
Step 3003, determines A phase firewire;
Phase identification instrument extension set 5 acquisition technique to three groups of live wire rising edges count value in, identical with the A phase rising edge count value that phase identification instrument main frame 2 sends is A phase firewire;
Step 3004, whether A phase count value is greater than other two-phases;
First CPU (central processing unit) judges whether the count value of A phase firewire is greater than the count value of other two-phases, if be greater than other two-phase count value, then judge criterion as: in addition in two-phase phase line, what count value was less is B phase firewire, other one is C phase firewire mutually, i.e. situation shown in dotted line 1 in Figure 17.Otherwise perform step 3005;
Step 3005, whether A phase numerical value is between other two-phases;
First CPU (central processing unit) judges that the count value of A phase firewire is whether between the count value of other two-phases, if between other two-phase count value, then judge criterion as: in other two-phases, count value the greater is as B phase firewire, other one is C phase firewire mutually, i.e. situation shown in dotted line 2 in Figure 17, otherwise perform step 3006;
Step 3006, whether A phase numerical value is less than other two-phases;
First CPU (central processing unit) judges whether the count value of A phase firewire is less than the count value of other two-phases, if be less than other two-phase count value, then judge criterion as: in addition in two-phase phase line, what count value was less is B phase firewire, other one is C phase firewire mutually, i.e. situation shown in dotted line 3 in Figure 17.Otherwise perform step 3007;
Step 3007, whether A phase counts is 0;
Situation as shown in dotted line in Figure 17 4, now phase identification instrument extension set 2 gathers the moment and is on the rising edge of A phase phase line, then now the second CPU (central processing unit) is 0 or about 200 (as 195 ~ 205) to the acquisition counter of A phase, if be 0, then phase criterion is with step 3004, if A phase acquisition counting position 0, be then about 200 (as 195 ~ 205), now phase criterion is with step 3006.
Specific works process and principle of work as follows:
When staff needs terminal block case 4 at user side, first push button, after first CPU (central processing unit) judges that button is pressed, current time is obtained by the first clock synchronization module, and phase identification instrument main frame 2 sends request instruction, includes the time scale information corresponding to current time in this request instruction.
Phase identification instrument main frame 2 is after the request instruction receiving phase identification instrument 5 transmission, current time is obtained by second clock synchronization module, and when starting for next whole point of current time, acquisition counter is carried out to the rising edge of A phase firewire, after acquisition counter success, the count value of the A phase phase place collected and the time scale information in collection moment are together back to phase identification instrument extension set 5 as phase data.
After phase identification instrument extension set 5 receives the phase data that phase identification instrument main frame 2 beams back, first the time scale information of this phase data is read, and whether one of the whole branch judging phase identification instrument main frame 2 acquisition counter and two whole branches himself gathering coincide, if misfitted, represent that postponing appears in note in two-way process, phase identification failure, phase identification instrument extension set 5 resends request instruction.If one of the whole branch of phase identification instrument main frame 2 acquisition counter and two whole branches himself gathering are coincide, then read the rising edge data of the A phase firewire that phase identification instrument main frame 2 acquisition counter obtains, the count value of the three-phase phase line that whole branch identical with himself collects is compared, first A phase is judged, then other two-phases are judged according to above-mentioned judgement flow process, and shown by charactron module, phase identification process terminates.
Embodiment 2:
Embodiment 2 is from the difference of embodiment 1: the workflow of phase identification instrument extension set 5 and phase identification instrument main frame 2 is different, and its hardware configuration and circuit arrange identical.
As shown in figure 18, in embodiment 2, the workflow of phase identification instrument extension set 5, comprises the steps:
Step 4001, pushes button;
When needs carry out phase identification, staff presses the button be connected with the first CPU (central processing unit);
Step 4002, determines real-time time;
After the first CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by the first clock synchronization module;
Step 4003, before whether the time be the 50s of current minute;
First CPU (central processing unit) judge the number of seconds of current time whether be in current in front 50s within, if be in when minute front 50s within, perform step 4004, if be in when minute 50 ~ 59s, perform step 4005;
Step 4004, sends request instruction immediately;
First CPU (central processing unit) sends request instruction by the first communication unit to phase identification instrument extension set 5, includes the time scale information of corresponding current time in request instruction;
Step 4005, time delay sends request instruction;
First CPU (central processing unit), when next whole time arrives, sends request instruction by the first communication unit to phase identification instrument main frame 2, includes the time scale information of corresponding instruction delivery time in this instruction;
Step 4006, next whole member record phase information;
After request instruction sends by the first CPU (central processing unit), wait the phase data that pending phase identification instrument main frame 2 returns according to its workflow; First CPU (central processing unit) simultaneously with the time representated by time scale information for starting point, when next whole branch arrives, acquisition counter is carried out to the rising edge of the three-phase phase time that arrives;
Step 4007, whether main frame is by return message;
First CPU (central processing unit) judges whether to receive in the presetting time information that phase identification instrument main frame 2 returns, if have received the information that phase identification instrument main frame 2 returns, perform step 4008, if do not receive the information that phase identification instrument main frame 2 returns, return and perform step 4002;
Step 4008, whether what main frame returned is reissue commands;
First CPU (central processing unit) judges whether the information that phase identification instrument main frame 2 returns is the instruction resend, if what receive is resend instruction, returns step 4002, if what receive is not the instruction resend, performs step 4009;
Step 4009, carries out phase place judgement;
First CPU (central processing unit) reads the rising edge count value of the A phase phase place that phase identification instrument main frame 2 returns, and the three-phase phase rising edge count value that himself acquisition counter arrives, and judges flow process, judge each phase phase place according to phase place;
Step 4010, carries out phase place display;
First CPU (central processing unit), according to the three-phase phase judged, is shown by charactron module.
As shown in figure 19, the workflow of phase identification instrument main frame 2, comprises the steps:
Step 5001, accepts extension set request;
Phase identification instrument main frame 2 receives the request instruction that phase identification instrument extension set 5 sends;
Step 5002, determines real-time time;
After the second CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by second clock synchronization module;
Step 5003, receive time-out;
Second CPU (central processing unit) judges whether time corresponding to time scale information in the request instruction that phase identification instrument extension set 5 is delivered to and current time are in same minute, if be in same minute, perform step 5005, if be not in same minute, then represent receive time-out, perform step 5004;
Step 5004, sends reissue commands;
Phase identification instrument main frame 2 sends reissue commands to phase identification instrument extension set 5, requires that phase identification instrument main frame 2 resends request instruction;
Step 5005, next whole member record A phase information;
Second CPU (central processing unit) at next whole point, by second waveform generating module send into waveform acquisition record A phase rising edge count value;
Step 5006, sends phase data;
The time scale information of the rising edge count value of A phase phase line and the whole branch in collection moment is sent to phase identification instrument extension set 5 as phase data by the second communication module by the second CPU (central processing unit).
The above is only preferred embodiment of the present invention, and be not restriction the present invention being made to other form, any those skilled in the art may utilize the technology contents of above-mentioned announcement to be changed or be modified as the Equivalent embodiments of equivalent variations.But everyly do not depart from technical solution of the present invention content, any simple modification, equivalent variations and the remodeling done above embodiment according to technical spirit of the present invention, still belong to the protection domain of technical solution of the present invention.
Claims (10)
1. alternating current phases identifier, comprise transformer (1) and export ground three-phase and four-line alternating current, it is characterized in that: the phase identification instrument extension set (5) being provided with phase identification instrument main frame (2) and wireless telecommunications with it, in the operation circuit of the three-phase firewire of described three-phase and four-line alternating current and zero line access phase identification instrument extension set (5), in the control circuit of at least one phase firewire of three-phase and four-line alternating current and zero line access phase identification instrument main frame (2).
2. alternating current phases identifier according to claim 1, is characterized in that: the control circuit of described phase identification instrument extension set (5) comprises the first CPU (central processing unit), the first clock synchronization module, first phase generation module, the first short-term transceiver module, charactron module and button; First clock synchronization module is connected with the input end of the first CPU (central processing unit), first communication module and the first CPU (central processing unit) interconnected, first phase generation module is connected with the input end of the first CPU (central processing unit), described alternating current access first phase generation module, the output terminal of the first CPU (central processing unit) connects charactron module and can the button of input control order simultaneously.
3. alternating current phases identifier according to claim 1, it is characterized in that: the control circuit of described phase identification instrument main frame (2) comprises the second CPU (central processing unit), second clock synchronization module, second phase generation module and the second short-term transceiver module, second clock synchronization module is connected with the input end of the second CPU (central processing unit), second communication module and the second CPU (central processing unit) interconnected, second phase generation module is connected with the input end of the second CPU (central processing unit).
4. alternating current phases identifier according to claim 1, is characterized in that: in the control circuit of described phase identification instrument main frame (2) and phase identification instrument extension set (5), be also provided with the indicating lamp module for indicating duty.
5. the alternating current phases recognition methods utilizing the alternating current phases identifier described in any one of claim 1 ~ 4 to realize, is characterized in that: comprise the steps:
Step 1, the control circuit of phase identification instrument extension set (5) performs extension set workflow and sends request instruction to phase identification instrument main frame (2);
Step 2, the control circuit of phase identification instrument main frame (2) performs the phase data that host work flow process obtains the phase line accessed in it, and returns phase identification instrument extension set (5) after receiving the request instruction that phase identification instrument extension set (5) sends;
Step 3, after phase identification instrument extension set (5) receives the phase data that phase identification instrument main frame (2) returns, the phase data obtained in conjunction with himself, excute phase determination methods judges each phase place and shows;
Described phase data comprises: time scale information when each phase line is carried out to count value that acquisition counter method obtains and carried out acquisition counter method.
6. alternating current phases recognition methods according to claim 5, is characterized in that: described extension set workflow, comprises the steps:
Step 1001, pushes button;
When needs carry out phase identification, press the button be connected with the first CPU (central processing unit) in phase identification instrument extension set (5) control circuit;
Step 1002, determines real-time time;
After the first CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by the first clock synchronization module;
Step 1003, sends request instruction;
First CPU (central processing unit) sends request instruction by the first communication module in phase identification instrument extension set (5) control circuit to phase identification instrument main frame (2);
Step 1004, acquisition phase information;
After request instruction sends by the first CPU (central processing unit), wait the phase data that pending phase identification instrument main frame (2) returns according to host work flow processing; First CPU (central processing unit) is simultaneously starting point with real-time time, carries out acquisition counter in the whole branch of the continuous print of two after this according to acquisition counter method to three-phase phase;
Step 1005, whether main frame returns phase data;
First CPU (central processing unit) judges whether to receive in the presetting time phase data that phase identification instrument main frame (2) returns, if have received the phase data that phase identification instrument main frame (2) returns, perform step 1006, if do not receive the phase data that phase identification instrument main frame (2) returns, return and perform step 1002;
Step 1006, whether time scale information conforms to;
First CPU (central processing unit) judges whether the time scale information in the phase data that phase identification instrument main frame (2) returns matches with the time scale information in the image data collected with himself, if coupling, perform step 1007, if do not mated, return step 1002;
Step 1007, carries out phase place judgement;
Count value in the phase information that first CPU (central processing unit) reading phase identification instrument main frame (2) returns, and the count value in the phase data of the three-phase phase himself obtained by acquisition counter method, according to phase place determination methods, each phase phase place is judged;
Step 1008, carries out phase place display;
First CPU (central processing unit), according to the three-phase phase judged, is shown by charactron module.
7. alternating current phases recognition methods according to claim 5, is characterized in that: described host work flow process, comprises the steps:
Step 2001, receives extension set request;
The second CPU (central processing unit) in phase identification instrument main frame (2) control circuit receives by the second communication module the request instruction that phase identification instrument extension set (5) sends;
Step 2002, determines real-time time;
After the second CPU (central processing unit) detects that button is pressed, the data determination real-time time sent into by second clock synchronization module;
Step 2003, record A phase phase place;
Second CPU (central processing unit) is carried out acquisition counter by acquisition counter method to access phase line wherein when starting for next whole point and is obtained phase data;
Step 2004, sends phase data;
The phase data obtained is back to phase identification instrument extension set (5) by the second processing unit.
8. the alternating current phases recognition methods according to claim 5 or 6, it is characterized in that: described acquisition counter method is: carry out counting with fixed frequency and the rising edge of corresponding phase line or negative edge are gathered, stop counting after rising edge or negative edge arrive, obtain described count value.
9. alternating current phases recognition methods according to claim 8, is characterized in that: described fixed frequency is 100 μ s.
10. the alternating current phases recognition methods according to claim 5 or 6, is characterized in that: described phase place determination methods is:
Step a, phase identification instrument extension set (5) determines A phase phase line according to the count value that phase identification instrument main frame (2) is sent into;
Step b, judges according to one of following criterion:
Criterion 1:A phase count value is greater than the count value of other two phase line, then other two phase lines fall into a trap numerical value minimum for B phase, another is C phase;
Criterion 2:A phase count value is greater than the enumeration data of a phase wherein and is less than the enumeration data of another phase, then what count value was minimum is C phase, and another is B phase;
Criterion 3:A phase count value is less than other two-phase enumeration data, then other two phase line fall into a trap numerical value little for B phase, what count large numerical value is C phase;
Criterion 4: when A phase count value is 0, with criterion 3, when count value is 195 ~ 205, with criterion 1.
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