CN104639125A - Clock signal generator and electronic equipment - Google Patents
Clock signal generator and electronic equipment Download PDFInfo
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- CN104639125A CN104639125A CN201310566975.6A CN201310566975A CN104639125A CN 104639125 A CN104639125 A CN 104639125A CN 201310566975 A CN201310566975 A CN 201310566975A CN 104639125 A CN104639125 A CN 104639125A
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- clock signal
- adjustable resistor
- inverter
- generating apparatus
- signal generating
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Abstract
Disclosed are a clock signal generator and electronic equipment. The clock signal generator comprises a controller and at least three phase inverters in sequential head-tail connection. Any two adjacent phase inverters form a phase inverter pair. An adjustable resistor is arranged between two phase inverters in at least one phase inverter pair. One end of any adjustable resistor is connected with the output end of one phase inverter in the corresponding phase inverter pair, and the other end of the adjustable resistor is connected with the input end of the other phase inverter in the phase inverter pair. The controller controls resistance values of the adjustable resistors when the adjustable resistors are connected to a circuit. The number of the phase inverters is an odd number. By the clock signal generator, both influences of clock signals on other surrounding signals and the area of a chip can be reduced effectively.
Description
Technical field
The present invention relates to electronic circuit technology field, be specifically related to a kind of generating means and electronic equipment of clock signal.
Background technology
Existing clock signal generating apparatus, when clocking, can only produce the clock signal of fixed frequency.When needing the signal producing other frequencies, then by increasing or reduce the described current source of clock signal generating apparatus inside or the mode of electric capacity, the frequency of clock signal can only be changed, increases the area of chip.Further, each adjustment operation can only change the frequency of clock signal in limited frequency domain, the frequency Relatively centralized of namely produced clock signal, still can produce interference to the signal of other frequencies of surrounding.
Summary of the invention
The embodiment of the present invention solve problem be how to reduce clock signal to other signals interference.
For solving the problem, the embodiment of the present invention provides a kind of clock signal generating apparatus, described device comprises: the inverter that the head and the tail of controller and more than three connect successively, any two adjacent reversers form an inverter pair, adjustable resistor is provided with between two inverters of at least one inverter centering, one end of adjustable resistor described in any one is connected with the output of an inverter of described inverter centering, the other end is connected with the input of another inverter of described inverter centering, described controller controls the resistance size in described adjustable resistor place in circuit, the quantity of described inverter is odd number.
Alternatively, described device also comprises: the detector be connected with the input of controller, whether produces interference to other signals for detecting produced clock signal.
Alternatively, described inverter is Schmidt trigger.
Alternatively, described adjustable resistor is adjustable resistor.
Alternatively, described adjustable resistor is slide rheostat.
Alternatively, described adjustable resistor comprises: the plural resistance be connected in parallel, and each described resistance is all connected with a switch, and described switch is closed or disconnection under the control of described controller.
Alternatively, described adjustable resistor is metal-oxide-semiconductor.
Alternatively, described adjustable resistor is at least two, and all be arranged on any inverter between adjustable resistor resistance identical.
Embodiments of the invention additionally provide a kind of electronic equipment, and described electronic equipment comprises above-mentioned clock signal generating apparatus.
Compared with prior art, the technical scheme of the embodiment of the present invention has the following advantages:
By the inverter of more than three head and the tail are connected successively, and adopt controller to control to be arranged on the resistance size in the adjustable resistor place in circuit between two inverters, the size of the electric current of clock signal generating apparatus can be regulated more easily according to actual needs, and need not increase or reduce current source or the electric capacity of described clock signal generating apparatus inside, effectively reduce clock signal to the impact of other signals of surrounding and the area reducing chip.
Accompanying drawing explanation
Fig. 1 is a kind of clock signal generating apparatus in the embodiment of the present invention;
Fig. 2 is another kind of clock signal generating apparatus in the embodiment of the present invention;
Fig. 3 is another clock signal generating apparatus in the embodiment of the present invention.
Embodiment
Existing clock signal generating apparatus, when needing the clock signal producing different frequency, by changing the described current source of clock signal generating apparatus inside or the mode of electric capacity, can only change the frequency of clock signal.Such as, can current source be increased, and then increase the electric current for generation of clock signal, thus increase the frequency of the clock signal produced.But the frequency changing clock signal by the way not only increases the area of chip, and each operation changed can only change the frequency of clock signal in limited frequency domain, is difficult to the demand meeting user.
For the problems referred to above, The embodiment provides a kind of clock signal generating apparatus, the inverter looping oscillating circuit that described device connects successively by adopting head and the tail, and between two inverters the adjustable resistor of equipment, the resistance size in described adjustable resistor place in circuit is controlled by controller, regulate the electric current for generation of clock signal, and then regulate the frequency of the clock signal produced.When applying the frequency of described device adjustment clock signal, the frequency of clock signal can be regulated arbitrarily according to actual needs, not by the restriction of frequency domain, the not only use of convenient user, and effectively reduce the area of chip.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
See Fig. 1, The embodiment provides a kind of clock signal generating apparatus, described device can comprise: the inverter that the head and the tail of controller 110 and more than three connect successively, any two adjacent inverters form an inverter pair, between two inverters of at least one inverter centering, arrange adjustable resistor, controller 110 controls the resistance size in described adjustable resistor place in circuit.
The inverter head and the tail of more than three connect successively, looping oscillating circuit.Such as, inverter 1202, inverter 1204 and inverter 1206 head and the tail connect successively.Wherein the output of any one inverter all can clocking, the clock signal produced can input in other parts of electronic equipment, such as, the clock signal that the output of inverter 1204 produces can be inputed in other parts of electronic equipment.The quantity of described inverter can be three, five or seven, can also be other numbers, as long as the quantity of described inverter keeps odd number.
In concrete enforcement, in all inverters of described clock signal generating apparatus, as long as can partial inversion device Schmidt trigger, also all can be Schmidt trigger by inverter.Such as, only having inverter 1204 and inverter 1206 to be Schmidt trigger, also can be that inverter 1202 to inverter 1206 is Schmidt trigger.Described Schmidt trigger and inverter include two stable states, and difference is, the state of described Schmidt trigger is subject to the control of Electric potentials of input signal.Such as, when the current potential of input signal rises to the positive threshold voltage of Schmidt trigger from low level, the output signal generation state turnover that Schmidt trigger is corresponding.When the current potential of input signal drops to the negative sense threshold voltage of Schmidt trigger from high level, the output signal that Schmidt trigger is corresponding overturns.
It should be noted that, in actual application, those skilled in the art can set forward threshold voltage or the negative sense threshold voltage of Schmidt trigger according to actual conditions, thus regulate the signal output waveform of described Schmidt trigger.
In concrete enforcement, any two adjacent inverters can form an inverter pair, then when described clock signal generating apparatus comprises the inverter that three head and the tail connect successively, as shown in Figure 1, described clock signal generating apparatus can comprise three inverters pair altogether, be respectively inverter 1202 and inverter 1204, inverter 1204 and inverter 1206, and inverter 1206 and inverter 1202.In like manner, when described clock signal generating apparatus comprises the inverter that five head and the tail connect successively, described clock signal generating apparatus comprises five inverters pair altogether, repeats no more herein.
Any one inverter all can arrange adjustable resistor between included two inverters wherein, now, one end of described adjustable resistor is connected with the output of an inverter of described inverter centering, and the other end is connected with the input of another inverter of described inverter centering.Such as, arrange adjustable resistor 1302 between inverter 1202 and inverter 1204, one end of adjustable resistor 1302 is connected with the output of inverter 1202, and the other end is connected with the input of inverter 1204.Also adjustable resistor can be set between all inverters are to included two inverters, such as, also can adjustable resistor 1304 be set between inverter 1204 and inverter 1206, and adjustable resistor 1306 is set between inverter 1206 and inverter 1202.
It should be noted that, different inverters between the resistance of adjustable resistor that arranges can be equal, also can be unequal, set according to actual needs by those skilled in the art.
In concrete enforcement, described clock signal generating apparatus can also comprise: the detector (not shown) be connected with the input of controller 110, and whether described detector produces interference to other signals of surrounding for the clock signal detecting described clock signal generating apparatus and produce.When produced clock signal produces interference to other signals, detected result is sent to described controller 110 by described detector, controls described adjustable resistor carry out relevant subsequent and operate by described controller 110.
It should be noted that, described clock signal generating apparatus both can when detector have detected that produced clock signal produced interference to other signals, under control of the controller 110, regulate the frequency of the clock signal produced, can when not having detector whether to detect other signals generation interference produced clock signal yet, under the control of described controller 110, produce the clock signal of multiple different frequency, ambient signals is produced to the probability disturbed to reduce produced clock signal.
No matter whether described clock signal generating apparatus comprises detector, and described controller 110 all can regulate the frequency of produced clock signal by the resistance size controlled in adjustable resistor place in circuit.Such as: controller 110 can control the resistance size in adjustable resistor 1302, adjustable resistor 1304 and adjustable resistor 1306 place in circuit.Such as, controller 110 can send corresponding control signal respectively to adjustable resistor 1302, adjustable resistor 1304 and adjustable resistor 1306, and then the resistance size controlled in adjustable resistor 1302, adjustable resistor 1304 and adjustable resistor 1306 place in circuit, the same control signal that also can be sent by controller controls adjustable resistor 1302, adjustable resistor 1304 and adjustable resistor 1306 simultaneously.
Wherein, described control signal can be analog signal, such as, be concrete voltage signal or current signal, also can be digital signal, distinguish different control signals by low and high level, can also be control command, as long as can by adjustable resistor identification.
It should be noted that, controller 110 both can send described control signal by wired mode, also can wirelessly send described control signal.
In concrete enforcement, described adjustable resistor can be adjustable resistor, described adjustable resistor is specifically as follows slide rheostat, and described controller 110 can control described slide rheostat by transmitting control signal and slide, and then controls the electric current in described clock signal generating apparatus.The resistance that described adjustable resistor also can be connected in parallel for two or more, each resistance is all connected with a switch, described controller 110 can control by transmitting control signal and the disconnection of the switch of described resistant series or closed, and then the size of the resistance of resistance in control place in circuit, thus control the electric current in described clock signal generating apparatus.Described adjustable resistor can also be metal-oxide-semiconductor, and described metal-oxide-semiconductor can be PMOS or NMOS tube, and described controller can transmit control signal and control being turned on or off of metal-oxide-semiconductor, and then controls the electric current of described clock signal generating apparatus.
Below for described adjustable resistor for slide resistor or multiple resistance of being connected in parallel, be described in detail by reference to the accompanying drawings:
It should be noted that, described adjustable resistor is not limited to device cited by following examples or circuit, those skilled in the art, based on the understanding to following examples, can convert described adjustable resistor, to realize the adjustment to electric current in described clock signal generating apparatus.
As shown in Figure 2, the clock signal generating apparatus in the present embodiment comprises: controller 210; And inverter 2202, inverter 2204 and inverter 2206 that three head and the tail connect successively; And the adjustable resistor 2302 be arranged between inverter 2202 and inverter 2204, be arranged on the adjustable resistor 2304 between inverter 2204 and inverter 2206, be arranged on the adjustable resistor 2306 between inverter 2206 and inverter 2202.Described controller 210 controls the resistance size in described adjustable resistor 2302, adjustable resistor 2304 and adjustable resistor 2306 place in circuit.
Described adjustable resistor 2302, adjustable resistor 2304 and adjustable resistor 2306 can be partly slide rheostat, can be also all slide rheostat.Be all that slide rheostat is described for the adjustable resistor of described adjustable resistor 2,302 2304 and adjustable resistor 2306 in the present embodiment.
When detector detects that the frequency of produced clock signal produces interference to other signals of surrounding, controller 210 transmits control signal at least one in adjustable resistor 2302, adjustable resistor 2304 and adjustable resistor 2306 according to detected result, such as control described adjustable resistor 2302 to transmit control signal, the slidably end controlling adjustable resistor 2302 slides to a direction, resistance now in described adjustable resistor 2302 place in circuit reduces, the electric current of described clock signal generating apparatus increases, and causes the frequency of produced clock signal to increase.Described controller 210 also can transmit control signal to adjustable resistor 2302 and adjustable resistor 2304 simultaneously, and the slidably end controlling adjustable resistor 2302 and adjustable resistor 2304 all slides to a direction, can change the frequency of produced clock signal rapidly.
It should be noted that, in actual applications, when transmitting control signal to multiple adjustable resistor, both can control multiple adjustable resistor and having slided in the same way, also can control described multiple adjustable resistor to slide along different directions, as long as the frequency of described clock signal can be changed.
As the above analysis, control the resistance size in adjustable resistor place in circuit by controller 210, effectively can control the electric current in described clock signal generating apparatus, thus control the frequency of the clock signal produced.
As shown in Figure 3, the clock signal generating apparatus in the present embodiment comprises: controller 310; Inverter 3202, inverter 3204 and inverter 3206 that three head and the tail connect successively; And the adjustable resistor 3302 be arranged between inverter 3202 and inverter 3204, be arranged on the adjustable resistor 3304 between inverter 3204 and inverter 3206, be arranged on the adjustable resistor 3306 between inverter 3206 and inverter 3202.Described controller 310 controls the resistance size in described adjustable resistor 3302, adjustable resistor 3304 and adjustable resistor 3306 place in circuit.
Adjustable resistor described in the present embodiment comprises multiple resistance be connected in parallel.Such as, adjustable resistor 3302 comprises resistance R
1with resistance R
2, resistance R
1with resistance R
2parallel connection, resistance R
1with switch S
1series connection, resistance R
2with switch S
2series connection.Adjustable resistor 3304 comprises resistance R
3with resistance R
4, resistance R
3with resistance R
4parallel connection, resistance R
3with switch S
3series connection, resistance R
4with switch S
4series connection.Adjustable resistor 3306 comprises resistance R
5with resistance R
6, resistance R
5with resistance R
6parallel connection, resistance R
5with switch S
5series connection, resistance R
6with switch S
6series connection.Wherein, resistance R
1to R
6resistance all equal.
It should be noted that, described adjustable resistor can comprise multiple resistance be connected in parallel, and each resistance can be connected a switch, also can not tandem tap, is not construed as limiting herein.
When described detector detects that produced clock signal produces interference to other signals of surrounding, if now the switch of all adjustment resistors is all closed, the resistance namely in place in circuit comprises R
1to R
6, then controller 310 transmits control signal to adjustable resistor according to detected result, is disconnected by partial switch wherein.Such as, controller 310 can transmit control signal to adjustable resistor 3302, adjustable resistor 3304 and adjustable resistor 3306, control switch S
1, switch S
3and switch S
5disconnect, now, the resistance in place in circuit comprises resistance R
2, resistance R
4and resistance R
6, the resistance of the resistance namely in place in circuit increases to one times before adjustment, and then the electric current of described clock generating device is decreased to one times before adjustment, causes the frequency of produced clock signal to change.
In concrete enforcement, described adjustable resistor can also comprise the metal-oxide-semiconductor that two or more is connected in parallel, such as, described MOS can be NMOS tube, the drain electrode of described NMOS tube is connected with the output of an inverter of inverter centering, source electrode is connected with the input of described another inverter of inverter centering, and grid is connected with described controller.When described in one of them, the grid voltage of metal-oxide-semiconductor is greater than the cut-in voltage of described NMOS, and when being less than the cut-in voltage of another NMOS tube in parallel with described NMOS, in described NMOS tube place in circuit, and another NMOS tube in parallel with described NMOS does not have in place in circuit.Because described metal-oxide-semiconductor self exists resistance, therefore, metal-oxide-semiconductor can be played equally the effect of the electric current regulating described clock signal generating apparatus as adjustable resistor, those skilled in the art can implement the present embodiment with reference to above-described embodiment, repeat no more herein.
Embodiments of the invention additionally provide a kind of electronic equipment, and described electronic equipment comprises above-mentioned clock signal generating apparatus.The frequency-adjustable joint of the clock signal produced due to described clock signal generating apparatus, therefore described electronic equipment in working order time, can not disturb other signals of surrounding, can be user-friendly.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (9)
1. a clock signal generating apparatus, it is characterized in that, comprise: the inverter that the head and the tail of controller and more than three connect successively, any two adjacent reversers form an inverter pair, adjustable resistor is provided with between two inverters of at least one inverter centering, one end of adjustable resistor described in any one is connected with the output of an inverter of described inverter centering, the other end is connected with the input of another inverter of described inverter centering, described controller controls the resistance size in described adjustable resistor place in circuit, the quantity of described inverter is odd number.
2. clock signal generating apparatus as claimed in claim 1, is characterized in that, also comprise: the detector be connected with the input of controller, whether produces interference to other signals for detecting produced clock signal.
3. clock signal generating apparatus as claimed in claim 1, it is characterized in that, described inverter is Schmidt trigger.
4. clock signal generating apparatus as claimed in claim 1, it is characterized in that, described adjustable resistor is adjustable resistor.
5. clock signal generating apparatus as claimed in claim 4, it is characterized in that, described adjustable resistor is slide rheostat.
6. clock signal generating apparatus as claimed in claim 1, it is characterized in that, described adjustable resistor comprises: the plural resistance be connected in parallel, and each described resistance is all connected with a switch, and described switch is closed or disconnection under the control of described controller.
7. clock signal generating apparatus as claimed in claim 1, it is characterized in that, described adjustable resistor comprises: the plural metal-oxide-semiconductor be connected in parallel.
8. the clock signal generating apparatus as described in any one of claim 1 to 7, is characterized in that, described adjustable resistor is at least two, and all be arranged on any inverter between adjustable resistor resistance identical.
9. an electronic equipment, is characterized in that, comprises the clock signal generating apparatus as described in any one of claim 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310566975.6A CN104639125B (en) | 2013-11-14 | 2013-11-14 | Clock signal generating apparatus and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310566975.6A CN104639125B (en) | 2013-11-14 | 2013-11-14 | Clock signal generating apparatus and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104639125A true CN104639125A (en) | 2015-05-20 |
| CN104639125B CN104639125B (en) | 2018-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310566975.6A Active CN104639125B (en) | 2013-11-14 | 2013-11-14 | Clock signal generating apparatus and electronic equipment |
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| Country | Link |
|---|---|
| CN (1) | CN104639125B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091272A (en) * | 1997-12-18 | 2000-07-18 | Vlsi Technologies, Inc. | Low power clock squarer with tight duty cycle control |
| CN2569454Y (en) * | 2002-06-13 | 2003-08-27 | 振玮科技股份有限公司 | Current image circuit |
| CN102412811A (en) * | 2012-01-06 | 2012-04-11 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
-
2013
- 2013-11-14 CN CN201310566975.6A patent/CN104639125B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091272A (en) * | 1997-12-18 | 2000-07-18 | Vlsi Technologies, Inc. | Low power clock squarer with tight duty cycle control |
| CN2569454Y (en) * | 2002-06-13 | 2003-08-27 | 振玮科技股份有限公司 | Current image circuit |
| CN102412811A (en) * | 2012-01-06 | 2012-04-11 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
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| Publication number | Publication date |
|---|---|
| CN104639125B (en) | 2018-04-27 |
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