CN104638012A - Trench isolation type semiconductor structure and manufacturing method thereof - Google Patents
Trench isolation type semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN104638012A CN104638012A CN201510047503.9A CN201510047503A CN104638012A CN 104638012 A CN104638012 A CN 104638012A CN 201510047503 A CN201510047503 A CN 201510047503A CN 104638012 A CN104638012 A CN 104638012A
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Abstract
The invention provides a trench isolation type semiconductor structure and a manufacturing method thereof. The manufacturing method for forming the semiconductor structure comprises the following steps: firstly manufacturing an active device in an active region of a semiconductor layer; then forming a trench in the isolation region of the semiconductor layer; finally filling the trench with an interlayer dielectric layer to form a trench isolation region with the trench together while the interlayer dielectric layer for protecting the active device is formed; thus a trench filling process is not required to be additionally increased, the manufacturing flow of the semiconductor structure is simplified, the manufacturing cost is reduced, and the frequency of a photolithographic process can also be reduced.
Description
Technical field
The present invention relates to ground semiconductor technology, more specifically, relate to a kind of semiconductor structure and manufacture method thereof of trench isolations formula.
Background technology
The manufacturing process of semiconductor integrated circuit is mainly included in the active area on the surface of Semiconductor substrate and forms the devices such as such as transistor, and these devices need by isolation structure mutually isolated.Groove isolation construction is often used as the active area of isolation of semiconductor substrate.Therefore groove is common Structure and energy step during semiconductor device manufactures every structure.
Fig. 1 is the structure chart of a kind of trench isolations formula semiconductor structure of existing techniques in realizing, and this structure mainly comprises Semiconductor substrate, ditch Cao isolated area, interlayer dielectric layer, the active area limited by groove and metal plug and metal interconnecting layer.Form the processing step of this structure for comprising: step a, on semiconductor substrate 1 formation groove 2, to be limited with source region; Step b, in groove 2, fill isolated material 3, to form channel separating zone; Unnecessary isolated material on step c, removal Semiconductor substrate 1 and groove, to make active device in the active area between groove, such as, first forms tagma 4, then form source region 5 on tagma 4; Steps d, surface coverage interlayer dielectric layer 6 at active area and groove; Step e, formation run through interlayer dielectric layer and the metal plug 7 contacted with the active device of active area; Step f, the metal interconnecting layer 8 that formation contacts with metal plug 7 on interlayer dielectric layer 6, to form the electrode of active device.
Therefore, the trench isolations formula semiconductor structure of existing techniques in realizing, when forming channel separating zone, need the processing step that a filling groove is set specially, add the complexity of manufacturing process flow, and semiconductor device is formed after trench fill again, be unfavorable for the number of times reducing the photoetching process that needs are used when forming semiconductor device, the manufacturing cost of device can not be reduced.
Summary of the invention
In view of this, a kind of semiconductor structure of trench isolations formula and manufacture method thereof is the object of the present invention is to provide to cause to solve in prior art the problem that technological process is complicated and manufacturing cost is high owing to needing to arrange trench fill process specially.
A semiconductor structure for trench isolations formula, comprising:
The semiconductor layer of the first doping type, has the source region and isolated area that are alternately arranged;
Active device, is positioned at described active area;
Groove, is positioned at described isolated area;
Interlayer dielectric layer, to be at least covered on described active device and to be filled in described groove.
Preferably, described semiconductor structure also comprises the metal interconnecting layer be positioned on described interlayer dielectric layer, and described metal interconnecting layer is contacted with described active device by the metal plug through described interlayer dielectric layer.
Preferably, the thickness of described interlayer dielectric layer is not less than 1/2nd of the width of described groove.
Preferably, described active device comprises the tagma of the second doping type being arranged in described active area and is arranged in the source region of the first doping type in described tagma.
Preferably, described metal plug contacts with described source region.
Preferably, the semiconductor layer of the described first doping type epitaxial loayer that is Semiconductor substrate or is positioned in Semiconductor substrate.
A manufacture method for the semiconductor structure of trench isolations formula, comprising:
There is provided the semiconductor layer of the first doping type, described semiconductor layer has the active area and isolated area that are alternately arranged;
Active device is made in described active area;
Groove is formed in described semiconductor layer;
On described active area and groove, form interlayer dielectric layer, described interlayer dielectric layer is covered on described active device and is filled in described groove.
Preferably, described manufacture method also comprises and being formed through described interlayer dielectric layer and the metal plug extended in described active device, and on described interlayer dielectric layer, form the metal interconnecting layer contacted with described metal plug.
Preferably, the thickness stating interlayer dielectric layer is made to be not less than 1/2nd of the width of described groove.
Preferably, in described active area, make active device to comprise:
At surface imp lantation second dopant of described active area, to form the tagma of the second doping type in described active area;
At surface imp lantation one dopant of described second doping type, to form the source region of the first doping type in described tagma.
Preferably, described metal plug is contacted with described source region.
Preferably, described manufacture method, is also included in semiconductor substrate surface and injects the first dopant, and to form described semiconductor layer, or the epitaxial loayer growing the first doping type is on a semiconductor substrate as described semiconductor layer.
Therefore; in the method for the semiconductor structure of manufacture trench isolations formula provided by the invention; before making the groove for isolating; first in the active area of semiconductor layer, form active device; and then form groove in the isolated area of semiconductor layer; finally when forming the interlayer dielectric layer of protection active device; make interlayer dielectric layer filling groove; to form groove every structure with groove one piece; thus without the need to additionally increasing trench fill process; simplify the manufacturing process of described semiconductor structure, reduce manufacturing cost.In addition, active making active device, before groove is formed, also can reduce the photoetching process number of times making active device.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the embodiment of the present invention, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 is the structure chart of a kind of trench isolations formula semiconductor structure of existing techniques in realizing;
Fig. 2 a-2d is the sectional view in each stage of the method for the semiconductor structure of manufacture trench isolations formula according to the embodiment of the present invention.
Embodiment
In more detail the present invention is described hereinafter with reference to accompanying drawing.In various figures, identical element adopts similar Reference numeral to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.In addition, may some known part not shown.For brevity, in a width figure, the structure obtained after several step can be described.Describe hereinafter many specific details of the present invention, the structure of such as device, material, size, treatment process and technology, more clearly to understand the present invention.But just as the skilled person will understand like that, the present invention can be realized not in accordance with these specific details.
Fig. 2 a-2d is the sectional view in each stage of the method for the semiconductor structure of manufacture trench isolations formula according to the embodiment of the present invention.
Please refer to shown in Fig. 2 d (semiconductor structure provided by the invention is along the sectional view in channel alignment direction), the semiconductor structure of trench isolations formula provided by the invention comprises: the semiconductor layer 1 of the first doping type, and it has the active area A and isolated area B that are alternately arranged; Be arranged in the active device of active area A, it can comprise the tagma 2 being arranged in active area A and the source region 3 being arranged in tagma; Be arranged in the groove 4 of isolated area B, be namely limited with source region A by groove 2; Interlayer dielectric layer 5, to be at least covered on described active device and to fill described groove 4.
Semiconductor structure provided by the invention also can comprise the metal interconnecting layer 7 be positioned on described interlayer dielectric layer 5 further, and metal interconnecting layer 7 is connected with the active device of active area by the metal plug 6 running through interlayer dielectric layer.The active device such as mos field effect transistor (MOSFET), insulated gate bipolar transistor (IGBT) etc. of active area.In the embodiment of the present application, the active device of active area is MOSFET, it can comprise the tagma 2 of the second doping type being arranged in active area A (as being arranged in the surface of active area) and be positioned at the source region 3 of the first doping type in tagma 2 (as being positioned at the surface in tagma), then metal plug 6 contacts with source region 3, and the metal interconnecting layer contacted with metal plug 6 is as the source electrode of MOSFET.Described active area A and isolated area B is alternately arranged in semiconductor layer 1, and groove 4 is formed in isolated area B, then the position at the B place, active area limited by groove 4, the region namely between groove is an active area A.The MOSFET being positioned at active area A also comprises drain region and grid region (not shown in FIG.), and grid region generally includes gate dielectric layer and is positioned at the grid on gate dielectric layer.If MOSFET is lateral MOS, then in tagma 2, (surface as tagma) also comprises the drain region of the first doping type, is grid region between drain region and source region; If this MOSFET is vertical MOS, below the semiconductor layer of then described first doping type, (groove 4 is extended downwards by the top of semiconductor layer 1, then below refers to the direction that groove extends) also comprise the drain region of the first doping type, grid region is then between the source region 3 of described first doping type.The semiconductor layer 1 of the first doping type is Semiconductor substrate (silicon substrate as the first doping type) or for being positioned at the epitaxial loayer in Semiconductor substrate.If when the semiconductor layer of the first doping type 1 is Semiconductor substrate, also comprise the well region of the first doping type in this Semiconductor substrate, this well region includes source region and isolated area, and groove 4 and active device can all be positioned among this well region.
In semiconductor structure provided by the invention; interlayer dielectric layer 5 is generally the good material of insulating properties and is formed, its be positioned at comprise active device active area on, and filling groove 4; protecting active device not contaminated while, can also form groove isolation construction with groove 4 one pieces.Full in order to make groove 4 be filled by interlayer dielectric layer 5 completely, to ensure isolation effect, the thickness of interlayer dielectric layer 5 will be not less than 1/2nd of groove width usually.
Therefore; in the isolated semiconductor structure of plough groove type provided by the invention; interlayer dielectric layer is while being coated with on the active device in source region; also be filled among the groove for isolating; active device can be protected not contaminated, isolated area can be formed with groove one piece again, therefore without the need to and outer add other packing material more in the trench to form channel separating zone; the processing step that described semiconductor structure is formed can be simplified, reduce production cost.
Method according to the semiconductor structure of the manufacture trench isolations formula of the embodiment of the present invention mainly comprises following technical process.
With reference to figure 2a, first, the semiconductor layer 1 of first doping type with active area A and the isolated area B be alternately arranged is provided, then in the A of active area, makes active device.。
The source device made in the A of active area is mos field effect transistor (MOSFET), insulated gate bipolar transistor (IGBT) etc. such as.In the embodiment of the present application, the active device made in active area is MOSFET, its manufacturing process can be included in surface imp lantation second dopant of active area A, to form the tagma 2 of the second doping type in described active area, namely tagma 2 is formed at the surface of semiconductor layer 1, again at surface imp lantation first dopant in tagma 2, to form the source region 3 of the first doping type in tagma 2.Because active device was formed before groove 4 is formed, area of isolation B can protect without using mask when forming active device, even if because made active device in isolated area, and also can by follow-up trench process to getting rid of.Therefore, the present invention can not use mask process, and at surface imp lantation second dopant of whole semiconductor layer 1 to form tagma 2, and then on tagma 2, form source region 3, as shown in Figure 2 a, then tagma 2 and source region 3 may extend in isolated area B.Form tagma 2 without using mask process, the number of times of photoetching process can be reduced, reduce cost of manufacture.Certainly also can utilize mask process only at the surface imp lantation dopant of active area A to form tagma 2.
The making of MOSFET also can comprise its drain region of formation and grid region further, and the formation in grid region generally includes the grid forming gate oxide and be positioned on gate oxide.If made MOSFET is lateral MOS, then its manufacture method is also included in (surface as tagma) in tagma 2 and forms the drain region of the first doping type, wherein, drain region can be formed with source region one step, between source region 3 and drain region, then forms the lamination of gate oxide and grid as grid region; If made MOSFET is vertical MOS, then form the drain region of the first doping type (as when semiconductor layer 1 is the epitaxial loayer on Semiconductor substrate upper surface in the below (below of the one side relative with making active device) of the semiconductor layer 1 of described first doping type, drain region is positioned at the lower surface of described Semiconductor substrate), and then the lamination forming gate oxide and grid between source region 3 is as grid region.
The semiconductor layer 1 of the first doping type can be Semiconductor substrate (silicon substrate as the first doping type), also can be the epitaxial loayer in Semiconductor substrate.If semiconductor layer 1 is Semiconductor substrate, then before formation active device, also first can inject the first dopant at semiconductor substrate surface, formed and have the Semiconductor substrate of the trap of the first doping type, using as described semiconductor layer 1, then active area A and isolated area B can all be arranged in this trap; If semiconductor layer 1 is Semiconductor substrate, then also can first at the epitaxial loayer of Semiconductor substrate (silicon substrate as the first doping type) superficial growth first doping type before formation active device, using as described semiconductor layer 1.
With reference to figure 2b, after having made active device, then form groove 4 having in isolated area B, groove 4 is extended in semiconductor layer by the surface of semiconductor layer 1.
The method forming groove 4 in the isolated area B of described semiconductor layer 1 does not limit in this application, a kind of optional method is: first form hard mask layer on the surface of described semiconductor layer 1, again opening process is carried out in place corresponding with isolated area B for hard mask layer, to expose the surface of isolated area B, then etch by the isolated area B that exposes to form groove 4.The number of groove 4 does not limit to one, and can decide according to needing in semiconductor layer 1 active device made, the region between groove 4 is described semiconductor structure active area A.
With reference to figure 2c, after formation groove 4, then on described active area A and groove 4, form interlayer dielectric layer 5 again, described interlayer dielectric layer 5 is covered on described active device and fills described groove.Such as in the present embodiment, interlayer dielectric layer 5 is covered on tagma 2 and source region 3, and is filled among groove 4.Interlayer dielectric layer 5 is generally the good material of insulating properties and is formed, and among its filling groove 4, can form channel separating zone with groove 4 one pieces.Therefore interlayer dielectric layer 5 protecting active device not contaminated while, can also serve as the filler of groove 4, have the effect of isolation.Full in order to make groove 4 be filled by interlayer dielectric layer completely, to ensure isolation effect, the thickness of interlayer dielectric layer will be not less than 1/2nd of groove width usually.
With reference to figure 2d, the method of the semiconductor structure of the manufacture trench isolations formula of the embodiment of the present invention also comprises, after formation interlayer dielectric layer 5, again in formation through interlayer dielectric layer 5 and the metal plug 6 extended in the active device in active area, and on interlayer dielectric layer 5, form the metal interconnecting layer 7 contacted with metal plug.
Form metal plug 6 not limit in invention with the method for metal interconnecting layer 7, such as its formation method can be: form the hard mask layer with opening on the surface of interlayer dielectric layer 5, opening is exposed be positioned at least part of interlayer dielectric layer 5 at active region place, then etch and etch by by exposed interlayer dielectric layer 5 place, and in the active device of etch stop in active area, then in etched region, described metal plug 6 is formed, make metal plug 6 be run through interlayer dielectric layer 5 by the surface of interlayer dielectric layer 5 and be extended in described active device to contact with active device, mask is finally utilized to form metal interconnecting layer 7 on interlayer dielectric layer 5, it is made to contact with metal plug 6, then metal interconnecting layer 7 is contacted with the active device in active area by metal plug 6.
In the present embodiment, the active device formed in active area is MOSFET, when metal forms metal plug 6, metal plug 6 is extended in source region 3 by the surface of interlayer dielectric layer 5, to contact with source region 3, then metal interconnecting layer 7 is the source electrode of MOSFET, and metal plug 6 also can be made further to extend in tagma 2, to contact with tagma 2, then the source electrode of MOSFET is made to be connected with underlayer electrode.
The manufacture method of semiconductor structure provided by the invention also can comprise the metal interconnecting layer 7 being formed and be positioned on described interlayer dielectric layer 5 further, and metal interconnecting layer 7 is connected with the active device of active area by the metal plug 6 running through interlayer dielectric layer.The active device such as mos field effect transistor (MOSFET), insulated gate bipolar transistor (IGBT) etc. of active area.In the embodiment of the present application, the active device of active area is MOSFET, it can comprise the tagma 2 of the second doping type being arranged in active area (as being arranged in the surface of active area) and be positioned at the source region 3 of the first doping type in tagma 2 (as being positioned at the surface in tagma), then metal plug 6 contacts with source region 3, and the metal interconnecting layer contacted with metal plug 6 is as the source electrode of MOSFET.Certainly, the manufacture method of semiconductor structure provided by the invention also can be included in and form other structure such as drain electrode and gate electrode, and it specifically forms method and does not limit.
In each embodiment of application, first doping type refers to the one in N-type doping type and P type doping type, second doping type then refers to the another kind in N-type doping type and P type doping type, first dopant refers to the one in N-type dopant and P-type dopant, and the first dopant refers to the another kind in N-type dopant and P-type dopant.
Therefore; in the method for the semiconductor structure of manufacture trench isolations formula provided by the invention; before making the groove for isolating; first in the active area of semiconductor layer, form active device; and then form groove in the isolated area of semiconductor layer; finally when forming the interlayer dielectric layer of protection active device; make interlayer dielectric layer filling groove; to form groove every structure with groove one piece; thus without the need to additionally increasing trench fill process; simplify the manufacturing process of described semiconductor structure, reduce manufacturing cost.In addition, active making active device, before groove is formed, also can reduce the photoetching process number of times making active device.
In the above description, the details for each step and structure is not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.
Above embodiments of the invention are described.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the invention.Scope of the present invention is by claims and equivalents thereof.Do not depart from the scope of the present invention, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should fall within the scope of the present invention.
Claims (12)
1. a semiconductor structure for trench isolations formula, comprising:
The semiconductor layer of the first doping type, has the source region and isolated area that are alternately arranged;
Active device, is positioned at described active area;
Groove, is positioned at described isolated area;
Interlayer dielectric layer, to be at least covered on described active device and to be filled in described groove.
2. semiconductor structure according to claim 1, characterized by further comprising the metal interconnecting layer be positioned on described interlayer dielectric layer, and described metal interconnecting layer is contacted with described active device by the metal plug through described interlayer dielectric layer.
3. semiconductor structure according to claim 1, is characterized in that, the thickness of described interlayer dielectric layer is not less than 1/2nd of the width of described groove.
4. semiconductor structure according to claim 2, is characterized in that, described active device comprises the tagma of the second doping type being arranged in described active area and is arranged in the source region of the first doping type in described tagma.
5. semiconductor structure according to claim 4, is characterized in that, described metal plug contacts with described source region.
6. semiconductor structure as claimed in any of claims 1 to 5, is characterized in that, the epitaxial loayer that the semiconductor layer of described first doping type is Semiconductor substrate or is positioned in Semiconductor substrate.
7. a manufacture method for the semiconductor structure of trench isolations formula, comprising:
There is provided the semiconductor layer of the first doping type, described semiconductor layer has the active area and isolated area that are alternately arranged;
Active device is made in described active area;
Groove is formed in described semiconductor layer;
On described active area and groove, form interlayer dielectric layer, described interlayer dielectric layer is covered on described active device and is filled in described groove.
8. manufacture method according to claim 7, it is characterized in that, also comprise and being formed through described interlayer dielectric layer and the metal plug extended in described active device, and on described interlayer dielectric layer, form the metal interconnecting layer contacted with described metal plug.
9. manufacture method according to claim 7, is characterized in that, makes the thickness stating interlayer dielectric layer be not less than 1/2nd of the width of described groove.
10. manufacture method according to claim 8, is characterized in that, makes active device and comprise in described active area:
At surface imp lantation second dopant of described active area, to form the tagma of the second doping type in described active area;
At surface imp lantation one dopant of described second doping type, to form the source region of the first doping type in described tagma.
11. manufacture methods according to claim 10, is characterized in that, described metal plug is contacted with described source region.
12. manufacture methods according to claim 7 to 11 any one, it is characterized in that, also be included in semiconductor substrate surface and inject the first dopant, to form described semiconductor layer, or the epitaxial loayer growing the first doping type is on a semiconductor substrate as described semiconductor layer.
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| US20020081820A1 (en) * | 1999-05-28 | 2002-06-27 | Masahiro Ikeda | Method for manufacturing semiconductor device capable of suppressing narrow channel width effect |
| CN1591817A (en) * | 2003-08-15 | 2005-03-09 | 台湾积体电路制造股份有限公司 | Isolation channel structure and manufacture method thereof |
| US20050101092A1 (en) * | 2002-12-31 | 2005-05-12 | Han Chang H. | Methods of fabricating semiconductor devices |
| US20100181598A1 (en) * | 2009-01-21 | 2010-07-22 | Tsutomu Sato | Semiconductor device and method of manufacturing semiconducer device |
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- 2015-01-30 CN CN201510047503.9A patent/CN104638012A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020081820A1 (en) * | 1999-05-28 | 2002-06-27 | Masahiro Ikeda | Method for manufacturing semiconductor device capable of suppressing narrow channel width effect |
| US20050101092A1 (en) * | 2002-12-31 | 2005-05-12 | Han Chang H. | Methods of fabricating semiconductor devices |
| CN1591817A (en) * | 2003-08-15 | 2005-03-09 | 台湾积体电路制造股份有限公司 | Isolation channel structure and manufacture method thereof |
| US20100181598A1 (en) * | 2009-01-21 | 2010-07-22 | Tsutomu Sato | Semiconductor device and method of manufacturing semiconducer device |
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