CN104617654A - Network bypass device and state setting method thereof - Google Patents
Network bypass device and state setting method thereof Download PDFInfo
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- CN104617654A CN104617654A CN201410686950.4A CN201410686950A CN104617654A CN 104617654 A CN104617654 A CN 104617654A CN 201410686950 A CN201410686950 A CN 201410686950A CN 104617654 A CN104617654 A CN 104617654A
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Abstract
The invention is applicable to the technical field of network communication and provides a network bypass device and a state setting method thereof. The network bypass device is composed of six functional circuits including a time-delayed power supply circuit (A), a power-off state control signal temporary storage circuit (B), a power-on state control signal driving circuit (C), a switching circuit (D), a magnetic latching relay driving circuit (E) and a magnetic latching relay set (F). The network bypass device is externally connected with two network electric ports and achieves a bypass function between the two electric ports. The network bypass device utilizes the GPIO signal lines (OFF_STATE_GPIO and ON_STATE_GPIO) of two systems and one signal (SYS_PWR_ON) indicating normal operation of a system power source. The network bypass device can set the on and off state of a bypass circuit during a power-off period according to the state of the OFF_STATE_GPIO, thereby achieving state setting of the bypass circuit in a power-off state.
Description
Technical field
The invention belongs to network communication technology field, particularly relate to a kind of network bypass device and state method to set up thereof.
Background technology
Network bypass (Network Bypass) technology, equipment and system are mainly used in the equipment such as gateway or fire compartment wall preventing from being connected in series in disparate networks becomes Single Point of Faliure because of unexpected inefficacy (as hardware fault, power failure, software deadlock etc.), or provide put-through channel when these serial connection equipment carry out upgrade maintenance, avoid because network switches the time delays and network O&M difficult management brought by hand, become the indispensable solution of availability in network operational support.Thus the technology of field of network safety application primary study is also become.At present, bypass equipment is divided into built-in bypass and external bypass in board form, is divided into electric port bypass and optical port bypass from the port type of bypass.
Existing or published network bypass technology can be divided into following a few class according to control mode:
1, power cut-off controls.When equipment is not energized, bypass functionality is opened, and after equipment energising, bypass functionality is adjusted to closed condition immediately.This method realizes simple, is applicable to the simple occasion of demand.
2, software-controlled manner.After entering operating system, support software carrys out control Bypass switch by GPIO (General PurposeInput/Output, universal input exports).Bypass functionality can be opened or closed by GPIO after equipment energising, thus there is certain intelligence.
3, house dog (Watchdog) control mode.By Watchdog supervisory control system, under deadlock state, control by-pass switch, thus realize the bypass functionality under software deadlock state.
4, the method combined.The related art features chosen in 1-3 carries out the bypass equipment in conjunction with practical function comparatively perfect.
The subject matter that prior art exists is, when network equipment system powers up, software arranges the switch of bypass circuit under system electrification state flexibly by GPIO, thus close or open bypass functionality, that is, under system electrification state, the state of bypass circuit can be arranged.But when system cut-off, the common relay switch due to bypass circuit use can get back to the on off state of acquiescence in the absence of a power supply, thus causes bypass circuit can only enter fixing state under powering-off state, can not arrange as required.A kind of method of improvement is had to be adopt magnetic latching relay, relay switch can keep on off state during electrifying condition under powering-off state, but this method can only realize state when following electrifying condition under powering-off state, require to close under cannot realizing requiring to close bypass functionality or electrifying condition under powering-off state as requiring under electrifying condition to open and the functional requirement that requires under powering-off state to open etc.
Along with the development of technology, the functional requirement of user to bypass circuit or equipment is also continuous growth, the state setting under bypass circuit needs control mode more flexibly to support powering-off state.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of network bypass device and state method to set up thereof, is intended to solve the bypass circuit state problem that can not arrange in the power-off state.
Realize like this time of the present invention, a kind of network bypass device, comprising: time delay power supply circuits and bypass circuit; Described bypass circuit comprises off-position control signal buffering circuit, power-up state control signal drive circuit, commutation circuit, drive circuit of magnetic latching relay and magnetic latching relay group;
Described time delay power supply circuits are connected with bypass circuit, and are connected with a system works power supply and time delay power supply; During system electrification, described system works power supply is to power-up state control signal drive circuitry, described time delay power supply obtains electric energy from system works power supply and powers to off-position control signal buffering circuit, commutation circuit, drive circuit of magnetic latching relay, magnetic latching relay group, simultaneously storage of electrical energy; In system cut-off moment, described time delay power supply utilizes the electric energy stored to carry out time delay power to off-position control signal buffering circuit, commutation circuit, drive circuit of magnetic latching relay, magnetic latching relay group;
Described off-position control signal buffering circuit receives the system signal OFF_STATE_GPIO for controlling shutdown transient bypass circuit switch state preset, during system electrification, described off-position control signal buffering circuit exports the signal OFF_STATE of the state of the described signal OFF_STATE_GPIO of reflection and is supplied to commutation circuit; In system cut-off moment, described off-position control signal buffering circuit temporarily stores and outputs signal OFF_STATE and be supplied to described commutation circuit;
Described power-up state control signal drive circuit receives the system signal ON_STATE_GPIO for the period bypass circuit switch state that controls to power on preset, during system electrification, described power-up state control signal drive circuit exports the signal ON_STATE of the state being reflected in the period described signal ON_STATE_GPIO that powers on and is supplied to described commutation circuit; In system cut-off moment, described power-up state control signal drive circuit is fixed output low level and is supplied to described commutation circuit;
Described commutation circuit is connected with described off-position control signal buffering circuit and described power-up state control signal drive circuit, and during system electrification, the signal ON_STATE of input exports as STATE signal by described commutation circuit; In system cut-off moment, the signal OFF_STATE of input exports as STATE signal by described commutation circuit;
Described drive circuit of magnetic latching relay is connected with described commutation circuit, produces drive singal DRV+ and DRV-for the STATE signal exported according to described commutation circuit, and described drive singal DRV+ and DRV-according to the difference of described STATE signal oppositely;
Described magnetic latching relay group is connected with described drive circuit of magnetic latching relay, for receiving described drive singal DRV+ and DRV-and carrying out the switching of bypass functionality.
Further, described time delay power supply circuits comprise: system works power supply, time delay power supply, diode, the first electric capacity, concrete circuit connecting mode is the negative electrode that described time delay power supply connects diode, described system works power supply connects the anode of diode, described first electric capacity one end is connected with time delay power supply, other end ground connection.
Further, described off-position control signal buffering circuit comprises: triode, the first resistance, the second electric capacity, concrete circuit connecting mode is: the base stage connected system working power of described triode, and receiving system signal OFF_STATE_GPIO, collector electrode connects time delay power supply, emitter connects commutation circuit, and simultaneously by described first grounding through resistance, described second electric capacity is connected to resistance two ends.
Further, described power-up state control signal drive circuit comprises: reverser, the second resistance, concrete circuit connecting mode is: described reverser connected system working power, the input Received signal strength ON_STATE_GPIO of described reverser, output connects commutation circuit, passes through described second resistive pull-downs to ground simultaneously.
Further, described commutation circuit comprises anti-door, d type flip flop or door, the 3rd resistance, the 3rd electric capacity, concrete circuit connecting mode is: the power end of described anti-door, d type flip flop or door all connects time delay power supply, the input receiving system power state signal SYS_PWR_ON of described anti-door, output connects the input end of clock CK of described d type flip flop; An input Received signal strength OFF_STATE of described d type flip flop, reset signal end CLR connect a low effective reset circuit that powers on consisted of the 3rd resistance and the 3rd electric capacity, an input of output connection or door; Another input Received signal strength ON_STATE of described or door, output connects drive circuit of magnetic latching relay.
Present invention also offers a kind of state method to set up of network bypass device, comprise the steps:
At shutdown transient, the electric energy stored is utilized to power to the time delay of off-position control signal buffering circuit;
Described off-position control signal buffering circuit receives the system signal OFF_STATE_GPIO for controlling shutdown transient bypass circuit switch state preset, and temporarily stores and export the signal OFF_STATE of the state of the described signal OFF_STATE_GPIO of reflection;
Signal OFF_STATE carries out the switching of bypass functionality accordingly.
The present invention compared with prior art, beneficial effect is to the invention provides a kind of network bypass device and state method to set up thereof, achieve the setting of bypass circuit state in the power-off state, wherein time delay power supply circuits by succinct circuit realiration a kind of time delay power demands that can meet this shunting device; Off-position control signal buffering circuit temporarily stores the function of OFF_STATE control signal under achieving powering-off state; Commutation circuit then utilizes ball bearing made using to achieve automatic switchover and the setting of state cleverly, and overall realizing circuit has low cost, high efficiency feature.
Accompanying drawing explanation
Fig. 1 is the functional block diagram of the network bypass device that the embodiment of the present invention provides;
Fig. 2 is the actual realizing circuit of one of the time delay power supply circuits (A) that the embodiment of the present invention provides;
Fig. 3 is the actual realizing circuit of one of the off-position control signal buffering circuit (B) that the embodiment of the present invention provides;
Fig. 4 is the actual realizing circuit of one of the power-up state control signal drive circuit (C) that the embodiment of the present invention provides;
Fig. 5 is the actual realizing circuit of one of the commutation circuit (D) that the embodiment of the present invention provides.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
The network bypass device that the present invention proposes as shown in Figure 1, this device is made up of six most of functional circuits, time delay power supply circuits (A), off-position control signal buffering circuit (B), power-up state control signal drive circuit (C), commutation circuit (D), drive circuit of magnetic latching relay (E) and magnetic latching relay group (F) respectively.This device externally connects two networks electricity port (electric port one, electric port 2), between these two electric ports, realize controlled bypass functionality.The signal SYS_PWR_ON (1: system power supply is normal, 0: system power supply power down) that this device uses the GPIO holding wire (OFF_STATE_GPIO, ON_STATE_GPIO) of 2 systems and an indication mechanism power supply normally to work.
This circuit arrangement can arrange the operating state of the period bypass circuit that powers on according to the state of the ON_STATE_GPIO of software design patterns, namely arrange the on off state of the period bypass circuit that powers on; According to the operating state of bypass circuit during the condition setting system power-off of OFF_STATE_GPIO between turnoff time, namely the on off state of bypass circuit between turnoff time is set.
The specific embodiment of each functional module is given below in conjunction with Fig. 2-5:
Fig. 2 is for the one provided is easily about the embodiment of time delay power supply circuits (A), time delay power supply circuits (A) comprising: system works power supply (Von), time delay power supply (Vdelay), diode, the first electric capacity CE1, wherein time delay power supply connects the negative electrode of diode, system works power supply (Von) connects the anode of diode, described first electric capacity CE1 one end is connected with time delay power supply (Vdelay), other end ground connection, concrete connected mode is as Fig. 2.Time delay power supply circuits (A) be input as system works power supply (Von), export as time delay power supply (Vdelay), when system normally powers on, system works power supply (Von) is effective, system works power supply (Von) is powered to power-up state control signal drive circuit (C), diode D1 conducting, time delay power supply (Vdelay) obtains power supply supply off-position control signal buffering circuit (B) from system works power supply (Von), commutation circuit (D), drive circuit of magnetic latching relay (E), magnetic latching relay group (F) works.When system cut-off, D1 oppositely by, prevent time delay power supply (Vdelay) to power to system load, now time delay power supply (Vdelay) is powered to off-position control signal buffering circuit, commutation circuit, drive circuit of magnetic latching relay, magnetic latching relay group by the electricity that electrolysis first electric capacity CE1 stores.When period type selecting, D1 should choose the lower germanium tube of pressure drop or Schottky diode.First electric capacity CE1 capacity can according to actual conditions according to following formulae discovery:
C＝(Vwork+Vmin)*I*t/(Vwork2-Vmin2)
Wherein, C is the nominal capacity of electric capacity, and unit is F; Vwork is normal working voltage, and unit is V; Vmin is cut-off operating voltage, and unit is V; T is the continuous working period required in circuit, and unit is s; I is load current, and unit is A;
Actual conditions first electric capacity CE1 selectable capacity according to this device circuit gets 1500uF-3300uF, can adjust according to actual conditions.
Fig. 3 is for the one provided is easily about the embodiment of off-position control signal buffering circuit (B), and off-position control signal buffering circuit (B) comprising: triode Q1, the first resistance R4, the second electric capacity C1; The wherein base stage connected system working power (Von) of triode Q1, and for receiving system signal OFF_STATE_GPIO, collector electrode connects time delay power supply (Vdelay), emitter is connected to another circuit module and commutation circuit (D), simultaneously by the first resistance R4 ground connection, second electric capacity C1 is connected to the first resistance R4 two ends, and its concrete connected mode is as Fig. 3.
When OFF_STATE_GPIO signal is high level, Q1 conducting, Vdelay makes the corresponding OFF_STATE of output be high level to the second electric capacity C1 charging, work as system cut-off, Von is now low level, and Q1 ends, and the state of OFF_STATE keeps a moment by the second electric capacity C1, be supplied to follow-up commutation circuit to use, thus play the effect temporarily stored;
When OFF_STATE_GPIO signal is low level, Q1 ends, R4 resistive pull-downs makes OFF_STATE correspondence export as low level, work as system cut-off, Von is now low level, Q1 ends, and the state of OFF_STATE is also remain low level by the first resistance R4 is drop-down, and is supplied to the use of follow-up commutation circuit.
Fig. 4 is for the one provided is easily about the embodiment of power-up state control signal drive circuit (C), power-up state control signal drive circuit (C) comprising: reverser U1, the second resistance R1, wherein reverser connected system working power, the input Received signal strength ON_STATE_GPIO of reverser, output connects commutation circuit, pull down to ground by described second resistance R1, its concrete connected mode is as Fig. 4 simultaneously.When system works power supply (Von) is effective (system electrification state), output to the state variation of the signal ON_STATE energy reaction signal ON_STATE_GPIO of commutation circuit (D); When system works power supply (Von) power-off (ON_STATE_GPIO blackout), signal ON_STATE pulls down to ground by the second resistance R1, exports fixing low level to commutation circuit (D).
Fig. 5 is for the one provided is easily about the embodiment of commutation circuit (D), commutation circuit (D) comprises anti-door U4, d type flip flop or door U2, the 3rd resistance R5, the 3rd electric capacity C2, wherein the power end of anti-door U4, d type flip flop or door U2 all connects time delay power supply, the input receiving system power state signal SYS_PWR_ON of described anti-door, output connects the input end of clock CK of described d type flip flop; An input Received signal strength OFF_STATE of described d type flip flop, reset signal end CLR connect a low effective reset circuit that powers on consisted of the 3rd resistance R5 and the 3rd electric capacity C2, an input of output connection or door U2; Another input Received signal strength ON_STATE of described or door U2, output connects drive circuit of magnetic latching relay, and its concrete connected mode is as Fig. 5.This circuit can switch ON_STATE signal and export to STATE signal when system electrification, control the state of follow-up magnetic latching relay group, and not by the variable effect of OFF_STATE state.Can automatically switch OFF_STATE state pre-set to STATE signal in system cut-off moment.Below make a concrete analysis of this circuit:
When circuit is at power-up state, the reset signal end CLR of d type flip flop U3 is connected to a low effective reset circuit that powers on consisted of the 3rd resistance R5 and the 3rd electric capacity C2, and thus exporting at powered on moment d type flip flop is 0.And now SYS_PWR_ON signal (power on period for high level) through being reversely connected to the clock CK signal end of trigger, owing to stabilizing to height at the period SYS_PWR_ON that powers on, CK holds correspondence to stabilize to low level, can not produce effective rising edge, the OFF_STATE signal being therefore connected to trigger D input can not output to the Q end of trigger.Thus power on period whole, trigger D stablizes output low level to two input or the inputs of door U2.Now ON_STATE signal is connected to or another input of door U2, due to 0 or any incoming level all equal this incoming level, what therefore now STATE exported is ON_STATE signal.
When the moment of down circuitry, due to the existence of time delay power supply (Vdelay), bypass circuit can work on a moment, now SYS_PWR_ON is by high step-down, an effective rising edge signal is created at the input end of clock CK of trigger by anti-door U4, therefore the OFF_STATE signal stored by off-position control signal buffering circuit (B) is output to the D output of trigger, and now ON_STATE signal pulled down to ground, be fixed as low level, therefore or the output signal of door U2 be OFF_STATE signal, achieve handoff functionality.
In addition, magnetic latching relay group (F) as shown in Figure 1, it connects two outside network electricity ports.Magnetic latching relay quantity depends on the type of electric port, when electric port is 100,000,000 network, needs the relay of 4 dpdt double-pole double-throw (DPDT) to realize the switching of 4 group network differential signals; When electric port is gigabit networking, need the relay of 8 dpdt double-pole double-throw (DPDT) to realize the switching of 8 group network differential signals.F partial circuit receives drive singal DRV+ and DRV-that E partial circuit transmits, and carries out the switching of bypass functionality according to system requirements; Drive singal DRV+ and DRV-that wherein E partial circuit transmits can be reverse according to the difference of described STATE signal, such as:
If
state＝1
drv+＝1
drv-＝0
And
state＝0
drv+＝0
drv-＝1
About circuit E and circuit F part, the magnetic latching relay circuit of existing universal models and corresponding drive circuit can be adopted, just do not provide specific embodiment at this.
The present invention can be applicable to network safety filed, as gateway device, and firewall box, gateway equipment etc.In this device can be directly applied in relevant device with built-in manner motherboard design with the form of Subcircuits module or be directly applied in relevant device with the form of external device (ED) and pass in and out between two electric ports.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a network bypass device, is characterized in that, comprising: time delay power supply circuits and bypass circuit; Described bypass circuit comprises off-position control signal buffering circuit, power-up state control signal drive circuit, commutation circuit, drive circuit of magnetic latching relay and magnetic latching relay group;
Described time delay power supply circuits are connected with bypass circuit, and are connected with a system works power supply and time delay power supply; During system electrification, described system works power supply is to power-up state control signal drive circuitry, described time delay power supply obtains electric energy from system works power supply and powers to off-position control signal buffering circuit, commutation circuit, drive circuit of magnetic latching relay, magnetic latching relay group, simultaneously storage of electrical energy; In system cut-off moment, described time delay power supply utilizes the electric energy stored to carry out time delay power to off-position control signal buffering circuit, commutation circuit, drive circuit of magnetic latching relay, magnetic latching relay group;
Described off-position control signal buffering circuit receives the system signal OFF_STATE_GPIO for controlling shutdown transient bypass circuit switch state preset, during system electrification, described off-position control signal buffering circuit exports the signal OFF_STATE of the state of the described signal OFF_STATE_GPIO of reflection and is supplied to commutation circuit; In system cut-off moment, described off-position control signal buffering circuit temporarily stores and outputs signal OFF_STATE and be supplied to described commutation circuit;
Described power-up state control signal drive circuit receives the system signal ON_STATE_GPIO for the period bypass circuit switch state that controls to power on preset, during system electrification, described power-up state control signal drive circuit exports the signal ON_STATE of the state being reflected in the period described signal ON_STATE_GPIO that powers on and is supplied to described commutation circuit; In system cut-off moment, described power-up state control signal drive circuit is fixed output low level and is supplied to described commutation circuit;
Described commutation circuit is connected with described off-position control signal buffering circuit and described power-up state control signal drive circuit, and during system electrification, the signal ON_STATE of input exports as STATE signal by described commutation circuit; In system cut-off moment, the signal OFF_STATE of input exports as STATE signal by described commutation circuit;
Described drive circuit of magnetic latching relay is connected with described commutation circuit, produces drive singal DRV+ and DRV-for the STATE signal exported according to described commutation circuit, and described drive singal DRV+ and DRV-according to the difference of described STATE signal oppositely;
Described magnetic latching relay group is connected with described drive circuit of magnetic latching relay, for receiving described drive singal DRV+ and DRV-and carrying out the switching of bypass functionality.
2. network bypass device as claimed in claim 1, it is characterized in that, described time delay power supply circuits comprise: system works power supply, time delay power supply, diode, the first electric capacity, concrete circuit connecting mode is the negative electrode that described time delay power supply connects diode, described system works power supply connects the anode of diode, described first electric capacity one end is connected with time delay power supply, other end ground connection.
3. network bypass device as claimed in claim 1, it is characterized in that, described off-position control signal buffering circuit comprises: triode, the first resistance, the second electric capacity, concrete circuit connecting mode is: the base stage connected system working power of described triode, and receiving system signal OFF_STATE_GPIO, collector electrode connects time delay power supply, and emitter connects commutation circuit, simultaneously by described first grounding through resistance, described second electric capacity is connected to resistance two ends.
4. network bypass device as claimed in claim 1, it is characterized in that, described power-up state control signal drive circuit comprises: reverser, the second resistance, concrete circuit connecting mode is: described reverser connected system working power, the input Received signal strength ON_STATE_GPIO of described reverser, output connects commutation circuit, passes through described second resistive pull-downs to ground simultaneously.
5. network bypass device as claimed in claim 1, it is characterized in that, described commutation circuit comprises anti-door, d type flip flop or door, the 3rd resistance, the 3rd electric capacity, concrete circuit connecting mode is: the power end of described anti-door, d type flip flop or door all connects time delay power supply, the input receiving system power state signal SYS_PWR_ON of described anti-door, output connects the input end of clock CK of described d type flip flop; An input Received signal strength OFF_STATE of described d type flip flop, reset signal end CLR connect a low effective reset circuit that powers on consisted of the 3rd resistance and the 3rd electric capacity, an input of output connection or door; Another input Received signal strength ON_STATE of described or door, output connects drive circuit of magnetic latching relay.
6. a state method to set up for network bypass device, is characterized in that, comprise the steps:
At shutdown transient, the electric energy stored is utilized to power to the time delay of off-position control signal buffering circuit;
Described off-position control signal buffering circuit receives the system signal OFF_STATE_GPIO for controlling shutdown transient bypass circuit switch state preset, and temporarily stores and export the signal OFF_STATE of the state of the described signal OFF_STATE_GPIO of reflection;
Signal OFF_STATE carries out the switching of bypass functionality accordingly.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410686950.4A CN104617654B (en) | 2014-11-25 | 2014-11-25 | A kind of network bypass device and state method to set up thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410686950.4A CN104617654B (en) | 2014-11-25 | 2014-11-25 | A kind of network bypass device and state method to set up thereof |
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| CN104617654A true CN104617654A (en) | 2015-05-13 |
| CN104617654B CN104617654B (en) | 2016-10-05 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108347094A (en) * | 2018-04-10 | 2018-07-31 | 北京数码视讯科技股份有限公司 | Switching circuit and electronic equipment |
| CN109713742A (en) * | 2018-12-05 | 2019-05-03 | 北京长城华冠汽车科技股份有限公司 | A kind of power cut-off device and method |
| CN110588688A (en) * | 2019-09-23 | 2019-12-20 | 珠海格力电器股份有限公司 | Clock control device, air conditioning system and clock control method thereof |
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| JP2002319927A (en) * | 2001-04-24 | 2002-10-31 | Nec Miyagi Ltd | Transmission line switching device and transmission system |
| CN102377586A (en) * | 2010-08-16 | 2012-03-14 | 研祥智能科技股份有限公司 | Network bypass device and method for processing network bypass |
| CN103064497A (en) * | 2011-10-21 | 2013-04-24 | 研祥智能科技股份有限公司 | Power source delayed power supply device, network main board and network host |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002319927A (en) * | 2001-04-24 | 2002-10-31 | Nec Miyagi Ltd | Transmission line switching device and transmission system |
| CN102377586A (en) * | 2010-08-16 | 2012-03-14 | 研祥智能科技股份有限公司 | Network bypass device and method for processing network bypass |
| CN103064497A (en) * | 2011-10-21 | 2013-04-24 | 研祥智能科技股份有限公司 | Power source delayed power supply device, network main board and network host |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108347094A (en) * | 2018-04-10 | 2018-07-31 | 北京数码视讯科技股份有限公司 | Switching circuit and electronic equipment |
| CN108347094B (en) * | 2018-04-10 | 2020-04-17 | 北京数码视讯科技股份有限公司 | Switching circuit and electronic device |
| CN109713742A (en) * | 2018-12-05 | 2019-05-03 | 北京长城华冠汽车科技股份有限公司 | A kind of power cut-off device and method |
| CN110588688A (en) * | 2019-09-23 | 2019-12-20 | 珠海格力电器股份有限公司 | Clock control device, air conditioning system and clock control method thereof |
| CN110588688B (en) * | 2019-09-23 | 2020-08-18 | 珠海格力电器股份有限公司 | Clock control device, air conditioning system and clock control method thereof |
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| Publication number | Publication date |
|---|---|
| CN104617654B (en) | 2016-10-05 |
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