CN104614908B - A kind of array base palte and liquid crystal display panel - Google Patents
A kind of array base palte and liquid crystal display panel Download PDFInfo
- Publication number
- CN104614908B CN104614908B CN201510054837.9A CN201510054837A CN104614908B CN 104614908 B CN104614908 B CN 104614908B CN 201510054837 A CN201510054837 A CN 201510054837A CN 104614908 B CN104614908 B CN 104614908B
- Authority
- CN
- China
- Prior art keywords
- metal layer
- pixel electrode
- insulating barrier
- electrode
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
Abstract
Include a substrate the invention discloses a kind of array base palte, and the first metal layer, the first insulating barrier, second metal layer, the second insulating barrier and pixel electrode layer on the substrate surface are set in turn in, the pixel electrode layer includes pixel electrode and public electrode；Projection is provided with second insulating barrier, it is described raised positioned between the pixel electrode and the public electrode, it is described raised for isolating the pixel electrode and public electrode.The present invention is prevented effectively from the problem of causing to occur short circuit due to the influence of particle, improves the quality of product.
Description
【Technical field】
The present invention relates to display technology field, more particularly to a kind of array base palte and liquid crystal display panel.
【Background technology】
In TFT-LCD (Thin Film Transistor Liquid Crystal Display, ultra-thin film transistor liquid
Crystal display) in industry, pixel can use the electric capacity that is formed between different metal to maintain pixel to show and prevent colour cast, when with
Made to same layer metal when electric capacity because same layer metal same layer not on, therefore, it is very easy to by particle
(particle) influence and the generation for causing short circuit.
Referring to Fig. 1, the structural representation of the array base palte provided for prior art.The array base palte includes a substrate
10, and be set in turn on the surface of substrate 10 the first metal layer 20, the first insulating barrier 30, second metal layer 40,
Two insulating barriers 50 and pixel electrode layer 60, wherein, pixel electrode in pixel electrode layer 60 with it is common on relative substrate
Electrode is as pixel capacitance, public electrode and the first metal layer 20 or the second metal layer 40 in pixel electrode layer 60
On common wire be used as storage capacitance.Pixel electrode layer 60 is made up of ITO (Indium Tin Oxide, tin-doped indium oxide).Can
Know, ITO has the effect of pixel capacitance and storage capacitance, when the purpose for forming electric capacity is to show, by main pixel
It is inconsistent that the electric charge of (main pixel) and sub-pixel (sub pixel) is distributed, so as to play a part of low colour cast.But it is this
Design has because ITO is located between same layer, the pixel electrode and the public electrode in the pixel electrode layer 60
There is gap, therefore particle is easy to fall in gap, so as to cause electric capacity ITO together with pixel ITO short circuits, so as to cause electricity
Appearance loses effect, ultimately results in display and exception occurs, reduces the quality of product.
Therefore, it is necessary to a kind of new technical scheme is proposed, to solve above-mentioned technical problem.
【The content of the invention】
It is an object of the invention to provide a kind of array base palte and liquid crystal display panel, it can be prevented effectively from due to particle
The problem of influenceing and cause to occur short circuit, improves the quality of product.
To solve the above problems, technical scheme is as follows：
A kind of array base palte, the array base palte includes：
One substrate；
One the first metal layer, the first metal layer is arranged on the substrate surface；The first metal layer includes thin
The grid and scan line of film transistor；
One first insulating barrier, first insulating barrier is arranged on the first metal layer, for isolating first gold medal
Belong to layer and second metal layer；
Second metal layer described in one, the second metal layer is arranged on first insulating barrier；The second metal layer
The drain electrode of source electrode, thin film transistor (TFT) including thin film transistor (TFT) and data wire；
One second insulating barrier, second insulating barrier is arranged in the second metal layer, for isolating second gold medal
Belong to layer and pixel electrode layer；
One is raised, and the projection is arranged on second insulating barrier；
Pixel electrode layer described in one, the pixel electrode layer is arranged on second insulating barrier；The pixel electrode layer
Including pixel electrode and public electrode；
Wherein, it is described raised positioned between the pixel electrode and the public electrode, it is described raised described for isolating
Pixel electrode and public electrode.
It is preferred that, in the array base palte, the thickness of second insulating barrier at the correspondence raised position is more than
The thickness of second insulating barrier at non-raised position.
It is preferred that, in the array base palte, the thickness of the second metal layer at the correspondence raised position is more than
The thickness of the second metal layer at non-raised position.
It is preferred that, in the array base palte, the first metal layer also includes common wire；The pixel electrode with it is relative
Substrate on common electrode be used as the common wire conduct on pixel capacitance, the public electrode and the first metal layer
Storage capacitance.
It is preferred that, in the array base palte, the second metal layer also includes common wire；The pixel electrode with it is relative
Substrate on common electrode be used as the common wire conduct in pixel capacitance, the public electrode and the second metal layer
Storage capacitance.
A kind of liquid crystal display panel, including array base palte, color membrane substrates and it is arranged at the array base palte and color film base
Liquid crystal cell between plate；Wherein,
The array base palte includes：
One substrate；
One the first metal layer, the first metal layer is arranged on the substrate surface；The first metal layer includes thin
The grid and scan line of film transistor；
One first insulating barrier, first insulating barrier is arranged on the first metal layer, for isolating first gold medal
Belong to layer and second metal layer；
Second metal layer described in one, the second metal layer is arranged on first insulating barrier；The second metal layer
The drain electrode of source electrode, thin film transistor (TFT) including thin film transistor (TFT) and data wire；
One second insulating barrier, second insulating barrier is arranged in the second metal layer, for isolating second gold medal
Belong to layer and pixel electrode layer；
One is raised, and the projection is arranged on second insulating barrier；
Pixel electrode layer described in one, the pixel electrode layer is arranged on second insulating barrier；The pixel electrode layer
Including pixel electrode and public electrode；
Wherein, it is described raised positioned between the pixel electrode and the public electrode, it is described raised described for isolating
Pixel electrode and public electrode.
It is preferred that, in the liquid crystal display panel, the thickness of second insulating barrier at the correspondence raised position
More than the thickness of second insulating barrier at non-raised position.
It is preferred that, in the liquid crystal display panel, the thickness of the second metal layer at the correspondence raised position
More than the thickness of the second metal layer at non-raised position.
It is preferred that, in the liquid crystal display panel, the first metal layer also includes common wire；The pixel electrode with
Common electrode on relative substrate is used as pixel capacitance, the public electrode and the common wire on the first metal layer
It is used as storage capacitance.
It is preferred that, in the liquid crystal display panel, the second metal layer also includes common wire；The pixel electrode with
Common electrode on relative substrate is used as pixel capacitance, the public electrode and the common wire in the second metal layer
It is used as storage capacitance.
Compared with the prior art, the present invention is described raised positioned at pixel electrode by being provided with projection over the second dielectric
It is described raised for isolating the pixel electrode and public electrode between pixel electrode and public electrode in layer.So that
Even if electric capacity ITO and pixel ITO are located at same layer, it will not also be influenceed by Particle, it is to avoid electric capacity ITO and pixel
Short circuit occurs for ITO, improves the quality of product., can be effective similar to wall gear between electric capacity ITO and pixel ITO
Prevent ITO short circuit generations, it is to avoid because short circuit occurs caused by Particle influence.The raised design causes
Particle is difficult to rest on the higher position of physical features；Even if there is Particle to fall in the raised position, but by aobvious
During shadow and etching, because the position of projection is easy to developed liquid or etching solution is etched away, therefore will substantially reduce because
The short circuit caused for Particle.
For the above of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, make
Describe in detail as follows.
【Brief description of the drawings】
The structural representation for the array base palte that Fig. 1 provides for prior art；
Fig. 2 is the structural representation for the array base palte that the embodiment of the present invention two is provided；
Fig. 3 is the structural representation for the array base palte that the embodiment of the present invention three is provided.
【Embodiment】
Word used in this specification " embodiment " means serving as example, example or illustration.In addition, this specification and institute
Article " one " used in attached claim can usually be interpreted to mean " one or more ", unless otherwise or
Understand guiding singulative from context.
In embodiments of the present invention, it is described raised positioned at pixel electrode layer by being provided with projection over the second dielectric
In pixel electrode and public electrode between, it is described raised to be used to isolate the pixel electrode and public electrode.So that i.e.
Electric capacity ITO and pixel ITO is located at same layer, will not also be influenceed by Particle, it is to avoid electric capacity ITO and pixel ITO
Generation short circuit, improves the quality of product.
Embodiment one
Referring to Fig. 2, being the structural representation of array base palte provided in an embodiment of the present invention.For convenience of description, only show
The part related to the embodiment of the present invention is gone out.
The array base palte includes：One substrate 100, a first metal layer 101, one first insulating barrier 102, one second metal
103, one second insulating barrier 104 of layer and a pixel electrode layer 105.Wherein, the first metal layer 101 is arranged at the base
On the surface of plate 100；First insulating barrier 102 is arranged on the first metal layer 101；The second metal layer 103 is set
In on first insulating barrier 102；First insulating barrier 102 is used to isolate the first metal layer 101 and second metal layer
103；Second insulating barrier 104 is arranged in the second metal layer 103；The pixel electrode layer 105 is arranged at described
On two insulating barriers 104；Second insulating barrier 104 is used to isolate the second metal layer 103 and pixel electrode layer 105.
In embodiments of the present invention, the first metal layer 101 is deposited on the surface of substrate 100, and followed by gold-tinted and erosion
The pattern of carving technology formation the first metal layer 101, wherein the grid of the pattern of the first metal layer 101 including thin film transistor (TFT) and
Scan line.When the public electrode in the pixel electrode layer 105 and the first metal layer 101 are as storage capacitance, then
The pattern of the first metal layer 101 also includes common wire, the common wire and public electrode formation storage capacitance.
In embodiments of the present invention, after sputtering sedimentation second metal layer 103, and formed followed by gold-tinted and etch process
The pattern of second metal layer 103, wherein, the pattern of the second metal layer 103 includes source electrode, the film crystal of thin film transistor (TFT)
The drain electrode of pipe and data wire.When the public electrode in the pixel electrode layer 105 and the second metal layer 103 are used as storage
During electric capacity, then the pattern of the second metal layer 103 also includes common wire, the common wire and public electrode formation storage capacitance.
In embodiments of the present invention, after the pixel electrode layer 105 of sputtering sedimentation one, and followed by gold-tinted and etch process shape
Into the pattern of the pixel electrode layer 105, wherein, the pattern of the pixel electrode layer 105 includes pixel electrode and public
Electrode.
In embodiments of the present invention, using ITO, (Indium Tin Oxide mix tin oxidation to the pixel electrode layer 105
Indium) or indium-zinc oxide IZO etc. material be made；First insulating barrier 102 can be made of G-Sinx materials；Described second
Insulating barrier 104 can be made of P-Sinx materials.It is understood, however, that above-mentioned material is not limited to, it is all the present invention's
Any modifications, equivalent substitutions and improvements made within spirit and principle etc., should be included in the scope of the protection.
In embodiments of the present invention, projection 106, described raised 106 is provided with the second insulating barrier 104 and is located at pixel electricity
Between pixel electrode and public electrode in pole layer 105, described raised 106 are used to isolate the pixel electrode and public electrode.
In embodiments of the present invention, the pixel electrode in the pixel electrode layer 105 and being total on relative substrate
Energization pole as pixel capacitance, the public electrode with it is public on the first metal layer 101 or the second metal layer 103
Line is used as storage capacitance；By having institute between the pixel electrode and the public electrode in the pixel electrode layer 105
Projection 106 is stated, therefore, it is possible to which the pixel electrode is isolated with the public electrode.
From the foregoing, it will be observed that described raised 106 are located at the pixel electrode layer 105 (i.e. between layer ITO), similar to a wall
Gear can effectively prevent ITO short circuit generations, it is to avoid because Particle influence causes between electric capacity ITO and pixel ITO
Short circuit generation.The raised design causes Particle to be difficult to rest on the higher position of physical features；Even if there is Particle
Fall in the raised position, but by development and etching during, because the position of projection be easy to developed liquid or
Etching solution is etched away, therefore will be substantially reduced because the short circuit that Particle is caused.
Embodiment two
Referring to Fig. 2, being the structural representation of array base palte provided in an embodiment of the present invention.For convenience of description, only show
The part related to the embodiment of the present invention is gone out.
The array base palte includes a substrate 100, and the first metal layer being set in turn on the surface of substrate 100
101st, the first insulating barrier 102, second metal layer 103, the second insulating barrier 104 and pixel electrode layer 105.Wherein, described first
Metal level 101 includes the grid and scan line of thin film transistor (TFT)；Source electrode of the second metal layer 103 including thin film transistor (TFT),
The drain electrode of thin film transistor (TFT) and data wire；The pixel electrode layer 105 includes pixel electrode and public electrode.Described first is exhausted
Edge layer 102 is used to isolate the first metal layer 101 and second metal layer 103；Second insulating barrier 104 is used to isolate described
Second metal layer 103 and pixel electrode layer 105.
In embodiments of the present invention, the pixel electrode in the pixel electrode layer 105 and being total on relative substrate
Energization pole as pixel capacitance, the public electrode with it is public on the first metal layer 101 or the second metal layer 103
Line is used as storage capacitance.Projection 106, described raised 106 is provided with the second insulating barrier 104 to be located in pixel electrode layer 105
Pixel electrode and public electrode between, described raised 106 be used for isolate the pixel electrode and public electrode.
In the present embodiment two, described raised 106 be as formed by being thickened the second metal layer 103.Correspond to described
The thickness of the second metal layer 103 at raised 106 positions is more than the thickness of the second metal layer 103 at non-raised position
Degree.The second metal layer of this part of the interstitial site i.e. between the correspondence pixel electrode and the public electrode
103, when the second metal layer 103 to this part carries out smearing photoresistance, exposure, development, etching operation so that the position
The thickness put is thicker than the thickness of other positions, so just causes the padded position of second metal layer 103 of the position
Second insulating barrier 104, so that the height of the position is higher by clearance height so that the gap shows projection, similar to a wall
Gear isolates electric capacity ITO and pixel ITO between electric capacity ITO and pixel ITO, can effectively prevent ITO short circuit generations, keep away
Short circuit occurs caused by exempting from the influence due to Particle.
Embodiment three
Referring to Fig. 3, being the structural representation of array base palte provided in an embodiment of the present invention.For convenience of description, only show
The part related to the embodiment of the present invention is gone out.
The array base palte includes：One substrate 100, a first metal layer 101, one first insulating barrier 102, one second metal
103, one second insulating barrier 104 of layer and a pixel electrode layer 105.Wherein, the first metal layer 101 is arranged at the base
On the surface of plate 100；First insulating barrier 102 is arranged on the first metal layer 101；The second metal layer 103 is set
In on first insulating barrier 102；First insulating barrier 102 is used to isolate the first metal layer 101 and second metal layer
103；Second insulating barrier 104 is arranged in the second metal layer 103；The pixel electrode layer 105 is arranged at described
On two insulating barriers 104；Second insulating barrier 104 is used to isolate the second metal layer 103 and pixel electrode layer 105.
Wherein, the first metal layer 101 includes the grid and scan line of thin film transistor (TFT)；The second metal layer 103
The drain electrode of source electrode, thin film transistor (TFT) including thin film transistor (TFT) and data wire；The pixel electrode layer 105 includes pixel electrode
And public electrode.When the public electrode in the pixel electrode layer 105 and the first metal layer 101 are as storage capacitance,
So the pattern of the first metal layer 101 also includes common wire, the common wire and public electrode formation storage capacitance.When the picture
Public electrode in plain electrode layer 105 with the second metal layer 103 as storage capacitance when, then the second metal layer 103
Pattern also include common wire, the common wire and public electrode formation storage capacitance.
In embodiments of the present invention, the pixel electrode in the pixel electrode layer 105 and being total on relative substrate
Energization pole as pixel capacitance, the public electrode with it is public on the first metal layer 101 or the second metal layer 103
Line is used as storage capacitance.Projection 106, described raised 106 is provided with the second insulating barrier 104 to be located in pixel electrode layer 105
Pixel electrode and public electrode between, described raised 106 be used for isolate the pixel electrode and public electrode.
In the present embodiment three, described raised 106 be as formed by being thickened second insulating barrier 104.Correspond to institute
The thickness for stating second insulating barrier 104 at raised position is more than the thickness of second insulating barrier 104 at non-raised position
Degree.Second insulating barrier of this part of the interstitial site i.e. between the correspondence pixel electrode and the public electrode
104, when second insulating barrier 104 to this part carries out smearing photoresistance, exposure, development, etching operation so that the position
The thickness put is thicker than the thickness of other positions, between so just make it that the height of the second insulating barrier 104 of the position is higher by
Gap height so that the gap shows projection, similar to wall gear between electric capacity ITO and pixel ITO, by electric capacity ITO and
Pixel ITO isolates, and can effectively prevent ITO short circuit generations, it is to avoid because short circuit occurs caused by Particle influence.Institute
The design of projection is stated so that Particle is difficult to rest on the higher position of physical features；Even if there is Particle to fall described raised
Position, but during by development and etching, because the position of projection is easy to developed liquid or etching solution is etched away, because
This will be substantially reduced because the short circuit that Particle is caused.
Example IV
The embodiment of the present invention additionally provides a kind of liquid crystal display panel.For convenience of description, it illustrate only real with the present invention
Apply the related part of example.The liquid crystal display panel include array base palte, color membrane substrates and be arranged at the array base palte with
Liquid crystal cell between color membrane substrates.
The array base palte includes：One substrate 100, a first metal layer 101, one first insulating barrier 102, one second metal
103, one second insulating barrier 104 of layer and a pixel electrode layer 105.Wherein, the first metal layer 101 is arranged at the base
On the surface of plate 100；First insulating barrier 102 is arranged on the first metal layer 101；The second metal layer 103 is set
In on first insulating barrier 102；First insulating barrier 102 is used to isolate the first metal layer 101 and second metal layer
103；Second insulating barrier 104 is arranged in the second metal layer 103；The pixel electrode layer 105 is arranged at described
On two insulating barriers 104；Second insulating barrier 104 is used to isolate the second metal layer 103 and pixel electrode layer 105.
Wherein, the first metal layer 101 includes the grid and scan line of thin film transistor (TFT)；The second metal layer 103
The drain electrode of source electrode, thin film transistor (TFT) including thin film transistor (TFT) and data wire；The pixel electrode layer 105 includes pixel electrode
And public electrode.When the public electrode in the pixel electrode layer 105 and the first metal layer 101 are as storage capacitance,
So the pattern of the first metal layer 101 also includes common wire, the common wire and public electrode formation storage capacitance.When the picture
Public electrode in plain electrode layer 105 with the second metal layer 103 as storage capacitance when, then the second metal layer 103
Pattern also include common wire, the common wire and public electrode formation storage capacitance.
In embodiments of the present invention, the pixel electrode in the pixel electrode layer 105 and being total on relative substrate
Energization pole as pixel capacitance, the public electrode with it is public on the first metal layer 101 or the second metal layer 103
Line is used as storage capacitance.Projection 106, described raised 106 is provided with the second insulating barrier 104 to be located in pixel electrode layer 105
Pixel electrode and public electrode between, described raised 106 be used for isolate the pixel electrode and public electrode.
It is understood, however, that the projection can be as formed by being thickened second insulating barrier；Correspond to institute
The thickness for stating second insulating barrier 104 at raised position is more than the thickness of second insulating barrier 104 at non-raised position
Degree.Either, the projection can be as formed by being thickened the second metal layer；Correspond at raised 106 position
The second metal layer 103 thickness be more than non-raised position at the second metal layer 103 thickness.
In summary, by being provided with projection over the second dielectric, the projection can be by second insulating barrier
Formed by thickening；Either, the projection can be as formed by being thickened the second metal layer；It is described raised positioned at picture
It is described raised for isolating the pixel electrode and public electrode between pixel electrode and public electrode in plain electrode layer.From
And make it that even if electric capacity ITO and pixel ITO are located at same layer, will not also be influenceed by Particle, it is to avoid electric capacity ITO and
Short circuit occurs for pixel ITO, improves the quality of product.Similar to wall gear between electric capacity ITO and pixel ITO, Ke Yiyou
What is imitated prevents ITO short circuit generations, it is to avoid because short circuit occurs caused by Particle influence.The raised design causes
Particle is difficult to rest on the higher position of physical features；Even if there is Particle to fall in the raised position, but by aobvious
During shadow and etching, because the position of projection is easy to developed liquid or etching solution is etched away, therefore will substantially reduce because
The short circuit caused for Particle.
Although the present invention, those skilled in the art has shown and described relative to one or more implementations
Based on the reading to the specification and drawings and understanding it will be appreciated that equivalent variations and modification.The present invention includes all such repair
Change and modification, and be limited only by the scope of the following claims.Particularly with the various functions performed by said modules, use
It is intended to correspond to the specified function of performing the component that (for example it is functionally of equal value in the term of the such component of description
) random component (unless otherwise instructed), with performing the exemplary realization of this specification shown in this article in structure
The open structure of function in mode is not equivalent.Although in addition, the special characteristic of this specification is relative to some realization sides
Only one in formula is disclosed, but this feature can with as can be expect and favorably for given or application-specific
Other one or more combinations of features of other implementations.Moreover, with regard to term " comprising ", " having ", " containing " or its deformation
For being used in embodiment or claim, such term is intended to the mode bag similar to term "comprising"
Include.
In summary, although the present invention it is disclosed above with preferred embodiment, but above preferred embodiment and be not used to limit
The system present invention, one of ordinary skill in the art without departing from the spirit and scope of the present invention, can make various changes and profit
Adorn, therefore protection scope of the present invention is defined by the scope that claim is defined.
Claims (8)
1. a kind of array base palte, it is characterised in that the array base palte includes：
One substrate；
One the first metal layer, the first metal layer is arranged on the substrate surface；It is brilliant that the first metal layer includes film
The grid and scan line of body pipe；
One first insulating barrier, first insulating barrier is arranged on the first metal layer, for isolating the first metal layer
And second metal layer；
Second metal layer described in one, the second metal layer is arranged on first insulating barrier；The second metal layer includes
The drain electrode of the source electrode, thin film transistor (TFT) of thin film transistor (TFT) and data wire；
One second insulating barrier, second insulating barrier is arranged in the second metal layer, for isolating the second metal layer
And pixel electrode layer；
One is raised, and the projection is arranged on second insulating barrier；
Pixel electrode layer described in one, the pixel electrode layer is arranged on second insulating barrier；The pixel electrode layer includes
Pixel electrode and public electrode；
Wherein, it is described raised positioned between the pixel electrode and the public electrode, it is described raised for isolating the pixel
Electrode and public electrode；
The thickness of the second metal layer at the wherein corresponding raised position is more than second gold medal at non-raised position
Belong to the thickness of layer.
2. array base palte according to claim 1, it is characterised in that second insulation at the correspondence raised position
The thickness of layer is more than the thickness of second insulating barrier at non-raised position.
3. array base palte according to claim 1, it is characterised in that the first metal layer also includes common wire；It is described
Common electrode on pixel electrode and relative substrate is as pixel capacitance, on the public electrode and the first metal layer
The common wire is used as storage capacitance.
4. array base palte according to claim 1, it is characterised in that the second metal layer also includes common wire；It is described
Common electrode on pixel electrode and relative substrate is as pixel capacitance, on the public electrode and the second metal layer
The common wire is used as storage capacitance.
5. a kind of liquid crystal display panel, including array base palte, color membrane substrates and it is arranged at the array base palte and color membrane substrates
Between liquid crystal cell；Characterized in that,
The array base palte includes：
One substrate；
One the first metal layer, the first metal layer is arranged on the substrate surface；It is brilliant that the first metal layer includes film
The grid and scan line of body pipe；
One first insulating barrier, first insulating barrier is arranged on the first metal layer, for isolating the first metal layer
And second metal layer；
Second metal layer described in one, the second metal layer is arranged on first insulating barrier；The second metal layer includes
The drain electrode of the source electrode, thin film transistor (TFT) of thin film transistor (TFT) and data wire；
One second insulating barrier, second insulating barrier is arranged in the second metal layer, for isolating the second metal layer
And pixel electrode layer；
One is raised, and the projection is arranged on second insulating barrier；
Pixel electrode layer described in one, the pixel electrode layer is arranged on second insulating barrier；The pixel electrode layer includes
Pixel electrode and public electrode；
Wherein, it is described raised positioned between the pixel electrode and the public electrode, it is described raised for isolating the pixel
Electrode and public electrode；
The thickness of the second metal layer at the wherein corresponding raised position is more than second gold medal at non-raised position
Belong to the thickness of layer.
6. liquid crystal display panel according to claim 5, it is characterised in that described second at the correspondence raised position
The thickness of insulating barrier is more than the thickness of second insulating barrier at non-raised position.
7. liquid crystal display panel according to claim 5, it is characterised in that the first metal layer also includes common wire；
Common electrode on the pixel electrode and relative substrate is as pixel capacitance, the public electrode and the first metal layer
On the common wire be used as storage capacitance.
8. liquid crystal display panel according to claim 5, it is characterised in that the second metal layer also includes common wire；
Common electrode on the pixel electrode and relative substrate is as pixel capacitance, the public electrode and the second metal layer
On the common wire be used as storage capacitance.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054837.9A CN104614908B (en) | 2015-02-02 | 2015-02-02 | A kind of array base palte and liquid crystal display panel |
| PCT/CN2015/072427 WO2016123800A1 (en) | 2015-02-02 | 2015-02-06 | Array substrate and liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510054837.9A CN104614908B (en) | 2015-02-02 | 2015-02-02 | A kind of array base palte and liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104614908A CN104614908A (en) | 2015-05-13 |
| CN104614908B true CN104614908B (en) | 2017-08-25 |
Family
ID=53149423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510054837.9A Active CN104614908B (en) | 2015-02-02 | 2015-02-02 | A kind of array base palte and liquid crystal display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104614908B (en) |
| WO (1) | WO2016123800A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154654B (en) * | 2016-08-26 | 2019-08-13 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN110718570A (en) * | 2019-09-17 | 2020-01-21 | 深圳市华星光电技术有限公司 | Display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837910A (en) * | 2005-03-23 | 2006-09-27 | Nec液晶技术株式会社 | Active matrix liquid crystal display device |
| CN1991480A (en) * | 2005-12-29 | 2007-07-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN103278979A (en) * | 2012-09-27 | 2013-09-04 | 上海天马微电子有限公司 | Array substrate of plane type liquid crystal displayer and manufacturing method thereof |
| CN203250093U (en) * | 2013-05-31 | 2013-10-23 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal displaying device |
| CN104007574A (en) * | 2014-06-18 | 2014-08-27 | 南京中电熊猫液晶显示科技有限公司 | Array substrate, display device and manufacturing method of display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5899103B2 (en) * | 2012-11-09 | 2016-04-06 | 株式会社ジャパンディスプレイ | Liquid crystal display |
-
2015
- 2015-02-02 CN CN201510054837.9A patent/CN104614908B/en active Active
- 2015-02-06 WO PCT/CN2015/072427 patent/WO2016123800A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1837910A (en) * | 2005-03-23 | 2006-09-27 | Nec液晶技术株式会社 | Active matrix liquid crystal display device |
| CN1991480A (en) * | 2005-12-29 | 2007-07-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN103278979A (en) * | 2012-09-27 | 2013-09-04 | 上海天马微电子有限公司 | Array substrate of plane type liquid crystal displayer and manufacturing method thereof |
| CN203250093U (en) * | 2013-05-31 | 2013-10-23 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal displaying device |
| CN104007574A (en) * | 2014-06-18 | 2014-08-27 | 南京中电熊猫液晶显示科技有限公司 | Array substrate, display device and manufacturing method of display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016123800A1 (en) | 2016-08-11 |
| CN104614908A (en) | 2015-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101419945A (en) | The manufacture method of semiconductor device | |
| CN104900633B (en) | A kind of manufacturing method of array base plate, array base palte and display device | |
| CN104280951A (en) | Array substrate, manufacturing method thereof, and display device | |
| CN103474471A (en) | Thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display device | |
| CN102655156A (en) | Array substrate and manufacturing method thereof | |
| CN209199077U (en) | A kind of touch-control display panel and display device | |
| CN107132710A (en) | A kind of array base palte and preparation method thereof, display panel | |
| CN103021940A (en) | Array substrate, manufacture method of array substrate and display device | |
| CN105161499A (en) | Display substrate, manufacturing method thereof and display device | |
| CN103048840B (en) | Array substrate, manufacture method of array substrate, liquid crystal display panel and display device | |
| CN106873238A (en) | A kind of opposite substrate, display panel, display device and preparation method | |
| CN103928400A (en) | Array substrate, manufacturing method thereof and display device | |
| CN104267550A (en) | Array substrate, display panel and display device | |
| CN103926733A (en) | Liquid crystal display device | |
| CN203519954U (en) | Array substrate and display device | |
| CN101436601A (en) | Array substrate of thin-film transistor | |
| CN106449660A (en) | Array substrate and manufacturing method thereof, and display device | |
| CN104779203B (en) | A kind of array base palte and its manufacture method, display device | |
| CN104614908B (en) | A kind of array base palte and liquid crystal display panel | |
| CN102650783A (en) | Display device, TFT-LCD (Thin Film Transistor-Liquid Crystal Display) pixel structure and manufacturing method of TFT-LCD pixel structure | |
| CN103926754A (en) | Array substrate and manufacturing method thereof, display panel and display device | |
| CN103715135A (en) | Via hole, making method thereof and array substrate | |
| CN102637634B (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN105206619B (en) | A kind of array base palte and preparation method thereof, display panel | |
| CN103605242B (en) | A kind of array base palte and preparation method thereof and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |