CN104600120B - A kind of p-type rf-ldmos semiconductor devices - Google Patents

A kind of p-type rf-ldmos semiconductor devices Download PDF

Info

Publication number
CN104600120B
CN104600120B CN201510021174.0A CN201510021174A CN104600120B CN 104600120 B CN104600120 B CN 104600120B CN 201510021174 A CN201510021174 A CN 201510021174A CN 104600120 B CN104600120 B CN 104600120B
Authority
CN
China
Prior art keywords
type
traps
heavy doping
drain
gate oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510021174.0A
Other languages
Chinese (zh)
Other versions
CN104600120A (en
Inventor
刘斯扬
孙陈超
王剑锋
叶然
张春伟
孙伟锋
陆生礼
时龙兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to CN201510021174.0A priority Critical patent/CN104600120B/en
Publication of CN104600120A publication Critical patent/CN104600120A/en
Application granted granted Critical
Publication of CN104600120B publication Critical patent/CN104600120B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A kind of p-type rf-ldmos semiconductor devices, including：N-type substrate, N-type epitaxy layer, formed with p-type lightly doped drain and N traps in N-type epitaxy layer, the side of the side of N traps and the p-type lightly doped drain is in contact；Formed with p-type heavy doping drain region in the p-type lightly doped drain；Formed with p-type heavy doping source region in the N traps, it is in contact in the opposite side of N traps formed with N-type heavy doping draw-out area, N-type heavy doping draw-out area through N-type epitaxy layer with N-type silicon substrate；Formed with gate oxide on N traps, and two borders of gate oxide are respectively positioned at the border of p-type heavy doping source region and p-type lightly doped drain top；Source metal is connected with N-type heavy doping draw-out area and p-type heavy doping source region, drain metal is connected with p-type heavy doping drain region, characterized in that, the gate oxide is stepped, it is provided with p-type doped region in the lower section of gate oxide and the p-type doped region is located in N traps.

Description

A kind of p-type rf-ldmos semiconductor devices
Technical field
It is laterally double more particularly to a kind of p-type applied to RF application the invention mainly relates to a kind of semiconductor devices Diffused metal oxide emiconductor device.
Background technology
RF power device is mainly used in the radio-frequency power amplifier of base stations in mobile communication system in wireless telecommunications.But Due to the deficiency of CMOS radio-frequency power performances, in radiofrequency power semiconductor in the market, until the mid-90 in last century, radio frequency work( Rate device is also all to use bipolar transistor or GaAs MOSFET.Until the later stage nineties, silicon-based lateral Diffused Metal Oxide Thing semiconductor transistor LDMOS appearance changes this situation.Rf-ldmos semiconductor (RF LDMOS) device is that the solid for the New Generation of Integrated that semiconductor integrated circuit technology enters with microwave electron technological incorporation is micro- Wave power semiconductor product, there is the good good linearity, high gain, high pressure, output power, heat endurance, efficiency high, broadband Matching performance is good, be easy to MOS techniques it is integrated the advantages that, and its price be far below GaAs device, is that one kind has very much The power device of competitiveness, it is widely used in the power amplifier of GSM, PCS, W-CDMA base station, and radio broadcasting and core Magnetic resonance etc..
The low-doped drift region that rf-ldmos semiconductor devices introduces between drain electrode and raceway groove, The breakdown voltage of device is improved, reduces the parasitic capacitance between source-drain electrode, improves the frequency characteristic of device.Pass through adjustment The length and doping concentration of low doped drain region, can be with the conducting resistance and breakdown voltage of adjusting device.P-type radio frequency transverse direction double diffusion The N-type heavy doping draw-out area of metal oxide semiconductor device realizes the connection of source electrode and substrate, during reducing radio frequency applications Source electrode lead inductance, increase the rf gain of common-source amplifier, improve the performance of device.
In the design process of rf-ldmos semiconductor devices, except requiring less electric conduction Outside resistance and big breakdown voltage, also require that less parasitic capacitance, including gate-source parasitic capacitance, gate-drain parasitic capacitances and source and drain are posted Raw electric capacity.For the certain rf-ldmos semiconductor devices of breakdown voltage and conducting resistance, grid Source parasitic capacitance and the size of gate-drain parasitic capacitances determine the size of cut-off frequency to a certain extent, gate-source parasitic capacitance and Gate-drain parasitic capacitances are bigger, and the cut-off frequency of device is with regard to smaller.In addition, power output of the source and drain parasitic capacitance to device, power Gain and efficiency have a significant impact, and the power output, power gain and efficiency of device can be improved by reducing source and drain parasitic capacitance.Cause The parasitic capacitance that this reduces device is significant to improving radio-frequency devices electric property.
The content of the invention
The invention provides a kind of p-type radio frequency that can be improved cut-off frequency and the threshold voltage of and can guarantee simultaneously and not reduce Lateral double-diffused metal-oxide semiconductor device.
The present invention adopts the following technical scheme that：A kind of p-type rf-ldmos semiconductor devices, bag Include：N-type substrate, formed with N-type epitaxy layer in N-type silicon substrate；Formed with p-type lightly doped drain and N in N-type epitaxy layer Trap, and N traps, in the side of the p-type lightly doped drain, the side of the side of N traps and the p-type lightly doped drain is in contact, Formed with the first p-type heavy doping drain region in the p-type lightly doped drain；Formed with the second p-type heavy-doped source in the N traps Area, connect in the opposite side of N traps formed with N-type heavy doping draw-out area, N-type heavy doping draw-out area with p-type heavy doping source region and N traps Touch, and be in contact through N-type epitaxy layer with N-type silicon substrate；Formed with gate oxide on N traps, and two sides of gate oxide Boundary respectively positioned at p-type heavy doping source region border and p-type lightly doped drain border above, the surface of gate oxide formed with Polysilicon gate；Source metal is connected with N-type heavy doping draw-out area and p-type heavy doping source region, is connected on p-type heavy doping drain region Drain metal is connected to, source metal and drain metal are isolated by field oxygen with polysilicon gate respectively, it is characterised in that the grid Oxide layer is stepped, is provided with p-type doped region in the lower section of gate oxide and the p-type doped region is located in N traps.
Compared with prior art, the invention has the advantages that：
(1), steplike-gate oxide layer 8 and p-type doped region 13 is applied in combination in the present invention, solves and individually uses step gates The grid oxygen that oxygen, p-type doped region and non-step-wise manner thicken combined with p-type doped region caused by problem so that the grid of device Source parasitic capacitance and gate-drain parasitic capacitances are reduced, cut-off frequency is improved, while and can ensures not dropping for threshold voltage It is low.
It is advantageous in that the cut-off frequency of device is improved existing for steplike-gate oxide layer 8 and p-type doped region 13.Cut An only important parameter of the frequency as rf-ldmos semiconductor devices, is typically posted by reducing grid source Electric capacity and gate-drain parasitic capacitances are given birth to improve its size.Gate-source parasitic capacitance and gate-drain parasitic capacitances are metal-insulator-half Capacitance of conductor, the electric capacity are the parallel connection of insulation body capacitance and semiconductor depletion region electric capacity, want to reduce the electric capacity typically from two sides Start with face：When increase gate oxide thickness, so as to reduce insulation body capacitance；Second, the width that increase semiconductor exhausts.P-type doped region 13 presence facilitates the exhausting to N-type epitaxy layer 2 and p-type lightly doped district 3 of N well regions 4 so that depletion region area increases, so Semiconductor depletion region electric capacity is reduced, therefore reduces gate-source parasitic capacitance and gate-drain parasitic capacitances.
But the introducing of p-type doped region 13 can shorten channel length, be substantially reduced threshold voltage, in order to not influence device On state characteristic, the channel length of retainer member is constant, only increases the length of grid covering N traps 4, will certainly so bring absolutely The increase of edge body capacitance.Steplike-gate oxide layer 8 covers the gate oxide thickness of the top of p-type doped region 13 in N traps 4 by increasing, and Due to the presence of p-type doped region 13, the gate oxide thickness above it can be accomplished very thick, thus completely inhibit because p-type is mixed The increase of insulation body capacitance caused by the introducing in miscellaneous area 13.
(2), accompanying drawing 3, accompanying drawing 4 and the accompanying drawing 5 respectively cut-off frequency of device and conventional device structure of the present invention, grid source are posted The comparison diagram of raw electric capacity and gate-drain parasitic capacitances, it can be found that device of the present invention is compared with conventional device, due to the parasitic electricity in grid source Hold and gate-drain parasitic capacitances substantially reduce, therefore the frequency characteristic of device is improved.
(3), benefit of the invention is that the presence of p-type doped region 13 also reduces resistance to a certain extent.By Advantage (1) is described, introduces after p-type doped region 13, and in order to not change the threshold voltage of device, only the raceway groove of guaranteed device is grown Degree does not change, therefore the only length of increase grid covering N traps 4, and the gate area of such device just increases, so as to grid Electrode resistance is reduced.In RF application, the reduction of resistance, the highest concussion frequency and power that can improve device increase Benefit.
(4), device of the present invention is advantageous in that the frequency characteristic for improving device, on the basis of reducing resistance, Breakdown voltage is held essentially constant.Accompanying drawing 6 is the breakdown voltage comparison diagram of device of the present invention and conventional device, it can be found that this hair Compared with conventional device, the breakdown voltage of device is held essentially constant funerary objects part.
(5), device of the present invention is advantageous in that the frequency characteristic for improving device, on the basis of reducing resistance, The ON state on state characteristic of device is held essentially constant.Accompanying drawing 7 is the I-V characteristic comparison diagram of device of the present invention and conventional device, can To find device of the present invention compared with conventional device, the ON state on state characteristic of device is held essentially constant.
Brief description of the drawings
Fig. 1 is existing p-type rf-ldmos semiconductor device structure profile.
Fig. 2 is the p-type rf-ldmos semiconductor device structure profile of the application.
Fig. 3 is the comparison figure of the cut-off frequency of device and conventional device of the present invention, it can be seen that device of the present invention to cut Only frequency is improved.
Fig. 4 is the comparison figure of the gate-source parasitic capacitance of device and conventional device of the present invention.It can be seen that device of the present invention makes Obtain gate-source parasitic capacitance and obtain obvious reduction.
Fig. 5 is the comparison figure of the gate-drain parasitic capacitances of device and conventional device of the present invention.It can be seen that device of the present invention makes Obtain gate-drain parasitic capacitances and obtain obvious reduction.
Fig. 6 is the comparison figure of the breakdown voltage of device and conventional device of the present invention.It can be seen that device of the present invention and routine Device is compared, and breakdown voltage is held essentially constant.
Fig. 7 is the comparison figure of the I-V characteristic of device and conventional device of the present invention.It can be seen that device of the present invention and conventional device Part is compared, and ON state on state characteristic is held essentially constant.
Embodiment
2 describe in detail below in conjunction with the accompanying drawings, a kind of p-type rf-ldmos semiconductor devices, including： N-type substrate 1, formed with N-type epitaxy layer 2 in N-type silicon substrate 1；Formed with p-type lightly doped drain 3 and N in N-type epitaxy layer 2 Trap 4, and N traps 4, in the side of the p-type lightly doped drain 3, the side of the side of N traps 4 and the p-type lightly doped drain 3 connects Touch, formed with the first p-type heavy doping drain region 5 in the p-type lightly doped drain 3；Formed with the second p-type weight in the N traps 4 Doping source region 6, N traps 4 opposite side formed with N-type heavy doping draw-out area 7, N-type heavy doping draw-out area 7 and p-type heavy-doped source Area 6 and N traps 4 are in contact, and are in contact through N-type epitaxy layer 2 with N-type silicon substrate 1；Formed with gate oxide 8 on N traps 4, and Two borders of gate oxide 8 are located above the border of p-type heavy doping source region 6 and the border of p-type lightly doped drain 3 respectively, The surface of gate oxide 8 is formed with polysilicon gate 9；Source electrode is connected with N-type heavy doping draw-out area 7 and p-type heavy doping source region 6 Metal 11, is connected with drain metal 12 on p-type heavy doping drain region 5, and source metal 11 and drain metal 12 pass through field oxygen respectively 10 are isolated with polysilicon gate 9, it is characterised in that the gate oxide 8 is stepped, and p-type is provided with the lower section of gate oxide 8 The doped region 13 and p-type doped region 13 is located in N traps 4.
Second ladder of described steplike-gate oxide layer (8) and the thickness ratio of the first ladder are 10:1 to 15:1.
The length of described p-type doped region (13) and the equal length of the second ladder of gate oxide (8).
The thickness of described p-type doped region (13) is less than the thickness of N traps (4), and size is more than 0 and less than 0.5 μm.
The doping concentration of described p-type doped region (13) is less than or equal to the doping concentration of N traps (4), and size is 2.0e17~9.0e17cm-3。
Described p-type rf-ldmos semiconductor devices, its channel length are 0.8~1.2 μm.

Claims (5)

1. a kind of p-type rf-ldmos semiconductor devices, including：N-type silicon substrate（1）, in N-type silicon substrate （1）On formed with N-type epitaxy layer（2）；In N-type epitaxy layer（2）In formed with p-type lightly doped drain（3）With N traps（4）, and N traps （4）In the p-type lightly doped drain（3）Side, N traps（4）Side and the p-type lightly doped drain（3）Side connect Touch, in the p-type lightly doped drain（3）In formed with the first p-type heavy doping drain region（5）；In the N traps（4）In formed with Two p-type heavy doping source regions（6）, in N traps（4）Opposite side formed with N-type heavy doping draw-out area（7）, N-type heavy doping draw-out area （7）With the second p-type heavy doping source region（6）With N traps（4）It is in contact, and passes through N-type epitaxy layer（2）With N-type silicon substrate（1）Connect Touch；In N traps（4）On formed with gate oxide（8）, and gate oxide（8）Two borders be located at the second p-type heavy-doped source respectively Area（6）Border and p-type lightly doped drain（3）Border above, in gate oxide（8）Surface formed with polysilicon gate（9）； In N-type heavy doping draw-out area（7）With the second p-type heavy doping source region（6）On be connected with source metal（11）, leaked in p-type heavy doping Area（5）On be connected with drain metal（12）, source metal（11）And drain metal（12）Pass through field oxygen respectively（10）With polysilicon Grid（9）It is isolated, it is characterised in that the gate oxide（8）To be stepped, in gate oxide（8）Lower section provided with p-type adulterate Area（13）And the p-type doped region（13）Positioned at N traps（4）In.
2. p-type rf-ldmos semiconductor devices according to claim 1, it is characterised in that ladder Shape gate oxide（8）The second ladder and the first ladder thickness ratio be 10:1 to 15:1.
3. p-type rf-ldmos semiconductor devices according to claim 2, it is characterised in that p-type Doped region（13）Length and gate oxide（8）The second ladder equal length.
4. p-type rf-ldmos semiconductor devices according to claim 1, it is characterised in that p-type Doped region（13）Thickness be less than N traps（4）Thickness, size is more than 0 and less than or equal to 0.5 μm.
5. p-type rf-ldmos semiconductor devices according to claim 1, it is characterised in that raceway groove Length is 0.8 ~ 1.2 μm.
CN201510021174.0A 2015-01-15 2015-01-15 A kind of p-type rf-ldmos semiconductor devices Active CN104600120B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510021174.0A CN104600120B (en) 2015-01-15 2015-01-15 A kind of p-type rf-ldmos semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510021174.0A CN104600120B (en) 2015-01-15 2015-01-15 A kind of p-type rf-ldmos semiconductor devices

Publications (2)

Publication Number Publication Date
CN104600120A CN104600120A (en) 2015-05-06
CN104600120B true CN104600120B (en) 2017-11-14

Family

ID=53125764

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510021174.0A Active CN104600120B (en) 2015-01-15 2015-01-15 A kind of p-type rf-ldmos semiconductor devices

Country Status (1)

Country Link
CN (1) CN104600120B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198129B1 (en) * 1999-08-31 2001-03-06 Oki Electric Industry Co., Ltd. Vertical type insulated gate transistor
CN101573799A (en) * 2007-01-04 2009-11-04 飞兆半导体公司 Integrated complementary low voltage rf-ldmos
CN101807604A (en) * 2010-04-02 2010-08-18 中国电子科技集团公司第五十五研究所 Point contact Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure transistor unit
CN103280455A (en) * 2013-04-28 2013-09-04 苏州市职业大学 Lateral diffusion type low on resistance MOS (metal oxide semiconductor) device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4070485B2 (en) * 2001-05-09 2008-04-02 株式会社東芝 Semiconductor device
KR100854078B1 (en) * 2001-09-12 2008-08-25 페어차일드코리아반도체 주식회사 MOS gated power semiconductor device and method for fabricating the same
US8680615B2 (en) * 2011-12-13 2014-03-25 Freescale Semiconductor, Inc. Customized shield plate for a field effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198129B1 (en) * 1999-08-31 2001-03-06 Oki Electric Industry Co., Ltd. Vertical type insulated gate transistor
CN101573799A (en) * 2007-01-04 2009-11-04 飞兆半导体公司 Integrated complementary low voltage rf-ldmos
CN101807604A (en) * 2010-04-02 2010-08-18 中国电子科技集团公司第五十五研究所 Point contact Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure transistor unit
CN103280455A (en) * 2013-04-28 2013-09-04 苏州市职业大学 Lateral diffusion type low on resistance MOS (metal oxide semiconductor) device

Also Published As

Publication number Publication date
CN104600120A (en) 2015-05-06

Similar Documents

Publication Publication Date Title
US6710416B1 (en) Split-gate metal-oxide-semiconductor device
US7126193B2 (en) Metal-oxide-semiconductor device with enhanced source electrode
EP2321850B1 (en) LDMOS having a field plate
EP1691419A2 (en) Field-effect transistor and method of manufacturing a field-effect transistor
CN101257047A (en) High pressure resistant lateral direction bilateral diffusion MOS transistor
CN114122123B (en) Silicon carbide split gate MOSFET (Metal-oxide-semiconductor field Effect transistor) integrated with high-speed freewheeling diode and preparation method
CN104992978B (en) A kind of radio frequency LDMOS transistor and its manufacturing method
JP2007503717A (en) Electronic device having LDMOS transistor
US9184278B2 (en) Planar vertical DMOS transistor with a conductive spacer structure as gate
CN115376924A (en) Manufacturing method of trench type silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) with low forward conduction voltage drop of body diode
US9178054B2 (en) Planar vertical DMOS transistor with reduced gate charge
CN104600098B (en) A kind of N-type radio frequency lateral double-diffused metal-oxide semiconductor device
CN104485360A (en) Radio frequency ldmos device and manufacturing method thereof
CN105140288B (en) Radio frequency ldmos device
TW201603288A (en) LDMOS device and resurf structure
CN112216745B (en) High-voltage asymmetric LDMOS device and preparation method thereof
US10355132B2 (en) Power MOSFETs with superior high frequency figure-of-merit
WO2004073015A2 (en) Multiple conductive plug structure including at least one conductive plug region and at least one between-conductive-plug region for lateral rf mos devices
CN104600120B (en) A kind of p-type rf-ldmos semiconductor devices
US20230352520A1 (en) Wide band gap semiconductor device
Jia et al. A novel high-performance trench lateral double-diffused MOSFET with buried oxide bump layer
CN104538441A (en) Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
Hou et al. RF LDMOS power transistor for multi-carrier GSM base station
CN104157690A (en) Strain NLDMOS device with groove structure and manufacturing method thereof
JP2006524430A (en) Semiconductor device and method for operating the semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant