CN104599955A - Process for shortening junction pushing time - Google Patents
Process for shortening junction pushing time Download PDFInfo
- Publication number
- CN104599955A CN104599955A CN201510008085.2A CN201510008085A CN104599955A CN 104599955 A CN104599955 A CN 104599955A CN 201510008085 A CN201510008085 A CN 201510008085A CN 104599955 A CN104599955 A CN 104599955A
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- CN
- China
- Prior art keywords
- knot
- junction
- time
- present
- shortening
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
Abstract
The invention provides a process for shortening junction pushing time, solving the problem that the junction pushing time is too long in the present semiconductor process. The method comprises the steps: uncovering the places, in need of PN junctions and the junction pushing process, on a wafer by means of a photo-etching process, and protecting the other places of the wafer with a photoresist; silicon-etching the uncovered places and etching a layer of silicon; and spreading and pushing junctions at the etched places and pushing the PN junctions to the needed places. On the basis of the present equipment, the process for shortening junction pushing time is capable of greatly shortening the needed junction pushing time in the prior art.
Description
Technical field
The invention relates to semiconductor technology, and relate to a kind of in existing Equipment Foundations especially, for coordinating the exploitation of new product, reaching by doing silicon etching at privileged site the technique reducing knot distance, reduce the knot time.
Background technology
In semiconductor manufacture flow path, often to use the process of knot, shift required position to reach onto by spreading the PN junction formed, meeting the requirement making and specify electrical property discrete device.In whole semiconductor manufacture flow path, knot occupies a large amount of time.How effectively the time reduced required for knot has become the big event reducing cost and fabrication cycle in current semiconductor technology.
The knot mode of current use is in boiler tube silicon chip being placed on high temperature and continues to pass into specific gas, PN junction is pushed into the position of specifying under the effect of high temperature.But As time goes on, the speed of knot can be more and more slower, so just causes the process time needed for knot quite long.Such as, suppose that the degree of depth of knot is x, the required process time is T, then usually only need about 1/3T at front 1/2x apart from the required time, even less; The knot of the distance of 1/2x below then needs the time of 2/3T, even longer.
For the defect of knot overlong time in above-mentioned existing semiconductor technology, the applicant is engaged in manufacturing experience and the technology accumulation of the industry then for many years with it, study energetically and how to improve from technique, to the disappearance of prior art can be improved, finally under the discretion of each side's condition is considered, develop the present invention.
Summary of the invention
The main purpose of the present invention is to provide a kind of technique reducing the knot time, by doing silicon etching at privileged site, the process time required for existing knot technique is reduced.
In order to achieve the above object and effect, the present invention adopts following technology contents:
Reduce the technique of knot time, comprise the following steps: first, a silicon chip is provided; Then, by photoetching process, described silicon chip spills the region needing to do PN junction and knot; Then, by silicon etching process, etch away one deck silicon on above-mentioned zone surface; Then, by diffusion technology, form PN junction at above-mentioned zone; Finally, by knot technique, described PN junction is pushed into required position.
The present invention at least has following beneficial effect:
Present invention is disclosed the process reducing the knot time.Use photoetching process, will wafer need the place of doing PN junction and knot technique spill, other places of wafer make to protect with photoresist.Do silicon etching in the place spilt, etch away one deck silicon on surface.Do in the place etched away afterwards and spread and knot, PN junction is pushed into required place.The present invention, when existing equipment board, significantly can reduce the time in current technique required for knot.
Other objects of the present invention and advantage can be further understood from the technology contents disclosed by the present invention.In order to above and other object of the present invention, feature and advantage can be become apparent, special embodiment below also coordinates institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 is the technological process of current existing diffusion knot.
Fig. 2 is the technological process that the present invention uses.
Embodiment
The content of the present invention's announcement relates to a kind of technique reducing the knot time, and its technical characteristics is, did a silicon etching, reduced the distance of knot, thus reduce the knot time before normally doing diffusion knot technique.
Next will coordinate institute's accompanying drawings through embodiment, and illustrate that the present invention has the unique technology parts such as innovation, progressive or effect compared with prior art, those of ordinary skill in the art can be realized according to this.Should be noted that, the modification that those of ordinary skill in the art carry out under not departing from spirit of the present invention and change, all do not depart from protection category of the present invention.
Refer to Fig. 1, current technological process, it mainly comprises the following steps:
First, step S100 is performed: provide a silicon chip (for illustrating in this block diagram 1);
Then, step S101 is performed: by photoetching process, silicon chip spills the region (for illustrating in this block diagram 1) needing to do PN junction and knot;
Then, perform step S102: by diffusion technology, form PN junction at above-mentioned zone;
Finally, step S103 is performed: by knot technique, PN junction is pushed into required position.The knot process time is Y1, and knot distance is X1.
Refer to Fig. 2, technological process of the present invention, it mainly comprises the following steps:
First, step S200 is performed: provide a silicon chip (for illustrating in this block diagram 2);
Then, step S201 is performed: by photoetching process, silicon chip spills the region (for illustrating in this block diagram 2) needing to do PN junction and knot;
Then, step S202 is performed: by silicon etching process, etch away one deck silicon on above-mentioned zone surface; In this step, etching depth is X2;
Then, perform step S203: by diffusion technology, form PN junction at above-mentioned zone;
Finally, step S204 is performed: by knot technique, PN junction is pushed into required position.In this step, the knot process time is Y2, and knot distance is X3.
In the enforcement of present invention process, in step S202, must guarantee to carry out the region of silicon etching and the region of follow-up PN junction generation; In step S202 and step S204, must X1=X2+X3 be guaranteed, namely guarantee that PN junction is pulled to the same position adopting former technique to shift onto.
The existing technique of comparison diagram 1 and the present invention process of Fig. 2: due to the knot distance X1 of the existing technique of knot distance X3< of the present invention, therefore the knot time Y1 of the existing technique of knot time Y2< of the present invention.
The foregoing is only embodiments of the invention, it is also not used to limit scope of patent protection of the present invention.Anyly have the knack of alike those skilled in the art, not departing from spirit of the present invention and scope, the equivalence of the change done and retouching is replaced, and still falls in scope of patent protection of the present invention.
Claims (1)
1. reduce the technique of knot time, it is characterized in that, comprise the following steps:
One silicon chip is provided;
By photoetching process, described silicon chip spills the region needing to do PN junction and knot;
By silicon etching process, etch away one deck silicon on above-mentioned zone surface;
By diffusion technology, form PN junction at above-mentioned zone;
By knot technique, described PN junction is pushed into required position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510008085.2A CN104599955B (en) | 2015-01-07 | 2015-01-07 | A kind of technique reducing the knot time |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510008085.2A CN104599955B (en) | 2015-01-07 | 2015-01-07 | A kind of technique reducing the knot time |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104599955A true CN104599955A (en) | 2015-05-06 |
| CN104599955B CN104599955B (en) | 2018-08-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510008085.2A Active CN104599955B (en) | 2015-01-07 | 2015-01-07 | A kind of technique reducing the knot time |
Country Status (1)
| Country | Link |
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| CN (1) | CN104599955B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250415A (en) * | 1988-08-12 | 1990-02-20 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| CN1913130A (en) * | 2006-08-28 | 2007-02-14 | 汤庆敏 | Manufacturing process of semiconductor device chip punch through isolation area and PN junction |
| CN101859703A (en) * | 2010-05-14 | 2010-10-13 | 深圳市芯威科技有限公司 | Low turn-on voltage diode and preparation method thereof |
| CN102610539A (en) * | 2012-01-18 | 2012-07-25 | 中国科学院上海微系统与信息技术研究所 | Method for measuring junction temperature of multi-chip embedded packaged chip by using integrated pn junction |
-
2015
- 2015-01-07 CN CN201510008085.2A patent/CN104599955B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0250415A (en) * | 1988-08-12 | 1990-02-20 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| CN1913130A (en) * | 2006-08-28 | 2007-02-14 | 汤庆敏 | Manufacturing process of semiconductor device chip punch through isolation area and PN junction |
| CN101859703A (en) * | 2010-05-14 | 2010-10-13 | 深圳市芯威科技有限公司 | Low turn-on voltage diode and preparation method thereof |
| CN102610539A (en) * | 2012-01-18 | 2012-07-25 | 中国科学院上海微系统与信息技术研究所 | Method for measuring junction temperature of multi-chip embedded packaged chip by using integrated pn junction |
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| Publication number | Publication date |
|---|---|
| CN104599955B (en) | 2018-08-14 |
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