CN104579362B - Partially-parallel architecture LDPC code decoding system and its method in a kind of space communication system - Google Patents
Partially-parallel architecture LDPC code decoding system and its method in a kind of space communication system Download PDFInfo
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Abstract
The present invention relates to partially-parallel architecture LDPC code decoding system and its method in a kind of space communication system, the system architecture includes iteration control unit, channel information memory, main storage, variable node processing module, code check node processing module, court verdict output buffer cell；Main-memory structures are simple, corresponded with non-zero submatrices in check matrix structure chart；The address processing unit of reading data is simple in construction from main storage, be easily achieved；The Partly parallel decoding structure design is out of the line several parallel code check node processing units, super columns a parallel variable node processing unit, and the implementation complexity of node messages more new algorithm is low, and institute's cost source is few.
Description
Technical field
The present invention relates to partially-parallel architecture LDPC code decoding system in a kind of space communication system, belong to parallel decoding skill
Art field.
Background technology
In space communication system, the signal that receiver is received is subjected to the influence such as fading channel and interference noise.In this regard,
Space communication system improves information transfer frequently with LDPC (low density parity check code) codes with high channel coding gain
Reliability, the bit error rate is reduced and shannon limit is approached.At present, LDPC code is used as CCSDS (Aerospace Data Systems information
The committee), one of recommendation channel coding schemes of the communication system of tissue such as Europe DVB (DVB).LDPC code is normal
It is described with check matrix or graph model, Tanner figure expressions are wherein relatively directly perceived, convenient a kind of, include two nodes
Set, variable node (variable node) set and check-node (check node) set.Each variable node correspondence
In a code element of code word, each check-node corresponds to a parity check constraint relation.Lead between two node sets
Side (edge) is crossed to be attached, and without the connection of any side inside node set.Tanner, which schemes to exist with check matrix, to be corresponded
Relation, i.e. variable node is corresponding with the row in check matrix, check-node with it is capable corresponding in check matrix, and side then with school
The nonzero element tested in matrix is corresponding.The number on the side being connected in Tanner figures with node is referred to as the degree (degree) of node,
The degree of node and the row weight (row weight) of check matrix are consistent.
The decoding algorithm of LDPC code has a lot, conventional belief propagation (BP) decoding algorithm log-likelihood ratio (LLR) table
Show probability messages, its algorithm steps is summarized as follows,
(1) initialize, it is P to calculate channel transfer to the probability of variable nodei, and corresponding likelihood ratio message count
According to for D (Pi), then set each variable node i and be transmitted to check-node j, j adjacent thereto span for j ∈ Mi, just
Beginning information is D(0)(qi→j)=D (Pi), N in formulajFor variable node i adjacent each check-node j set.
(2) check-node updates, and calculates variable node and is transmitted to the message of check-node for D(l)(rj→i), NjFor j-th of school
The adjacent variable node set of node is tested,
In formula, i' ∈ NjI represent set NjThe middle set for removing at i-th point, l represents this iterative decoding of l, and l-1 is represented
The l-1 times iterative decoding.
(3) variable node updates, during the l times iteration, calculates check-node and is transmitted to the message of variable node for D(l)(qi→j),
(4) decoding judgement, the hard decision information for calculating all variable nodes is D(l)(qi→j),
If D(l)(qi)>0, then 1 is judged to, is otherwise 0.The sequence that judgement is obtained is metH represents verification in formula
Matrix,The transposition of judgement data is represented, or reaches maximum iteration, then terminates decoding, otherwise goes to 1).
Minimum and (MS) algorithm can be derived from BP decoding algorithms.Its check-node, which updates, to be expressed as
In formula, sgn represents to take symbol bit manipulation.
It is minimum and with offset minimum-sum algorithm etc. in addition with the normalization to minimum and (MS) algorithm amendment, although with
The upper decoding algorithm passes through various simplification, and the realizations of LDPC decoding algorithms generally requires very complicated in digital receiver
Calculating and more resource consumption.So with greater need for simple, the efficient decoder of design in broadband spatial communication system.
The content of the invention
Present invention solves the technical problem that being：Overcome prior art not enough there is provided part in a kind of space communication system simultaneously
Row structure LDPC code decoding system, for code check R=1/2 in CCSDS (the Aerospace Data Systems information committee) system
(8192,4096) LDPC code designs partially-parallel architecture LDPC code interpretation method in a kind of space communication system, and the present invention has
It is distributed simple main storage, the address process being easily achieved and the low node messages updating block of implementation complexity, the design
The ldpc decoder design of other code checks of CCSDS deep space communication standards can be flexibly applied to.
The technical scheme that the present invention is solved is：Partially-parallel architecture LDPC code decoding system in a kind of space communication system,
Including iteration control unit, channel information memory, main storage, variable node processing module, code check node processing module, sentence
Certainly result exports buffer cell；
Channel information memory includes 4 dual port RAMs, and each RAM depth is L=2048, and main storage includes 15
Memory RAM, i.e. main storage RAM1, RAM2 ..., RAM15, for storing what is transmitted between variable node and check-node
Side information, the verification for the quasi-cyclic LDPC code that code efficiency of each memory RAM correspondence defined in CCSDS standards is R=1/2
Each non-zero submatrices in matrix H, each memory RAM depth is L=2048, i.e. main storage RAM1,
RAM2 ..., RAM15 respectively correspond to it is as follows：
The super row S1 of RAM1 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S1 of RAM2 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The super row S2 of RAM3 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S2 of RAM4 correspondences submatrix Πs corresponding with the H3 that is out of the line5；
The super row S2 of RAM5 correspondences submatrix Πs corresponding with the H3 that is out of the line6；
The super row P1 of RAM6 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P2 of RAM7 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row P2 of RAM8 correspondences submatrix Πs corresponding with the H3 that is out of the line7；
The super row P2 of RAM9 correspondences submatrix Πs corresponding with the H3 that is out of the line8；
The super row P3 of RAM10 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P3 of RAM11 correspondences submatrix Πs corresponding with the H1 that is out of the line1；
The super row P3 of RAM12 correspondences submatrix Πs corresponding with the H2 that is out of the line2；
The super row P3 of RAM13 correspondences submatrix Πs corresponding with the H2 that is out of the line3；
The super row P3 of RAM14 correspondences submatrix Πs corresponding with the H2 that is out of the line4；
The super row P3 of RAM15 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The row of check matrix H is divided into 3 be out of the line respectively H1, H2, H3, H1 be 0-2047 rows, H2 be 2048-4095 rows,
H3 is 4096-6143 rows；The row of check matrix H are divided into 5 super row S1, S2, P1, P2, P3, S1 is that 0-2047 is arranged, S2 is
2048-4095 row, P1 are that 4096-6143 is arranged, P2 is that 6144-8191 is arranged, P3 is 8192-10239 row, and this matrix divides such as Fig. 1
It is shown；
Variable node processing module includes this 5 variable node processing units of VNU1, VNU2, VNU3, VNU4 and VNU5, becomes
It is that 5 tunnels are parallel to measure endpoint processing unit；
Check-node address processing module includes CNU1, CNU2, CNU3 these three code check node processing units, CNU1,
CNU2, CNU3 are that 3 tunnels are parallel；
Channel information memory cell receives and stores this current frame likelihood information data of digital receiver demodulation, and will
In 4 RAM for storing to the likelihood information data order channel information memory cell, a frame likelihood information data are 8192
Individual, after the frame is received, channel information memory cell generation one receives signal and is sent to iteration control unit, believes
Road information memory cell receives 8192 data of next frame by ping-pong operation simultaneously；
Iteration control unit receives to receive after signal sends decoding commencing signal, channel to channel information memory cell
Information memory cell receives decoding commencing signal, by the ground of the likelihood information data order in the 4 RAM circuit-switched data of parallel output 4
D_llr gives variable node processing module,
4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, 4 circuit-switched data D_llr is divided
VNU1, VNU2, VNU3, VNU4 are not delivered to, 0 value is delivered into VNU5, while variable node processing module is from main storage
RAM1, RAM2 ..., in RAM15 according to the RAM1 in memory, RAM2 ..., RAM15 reading address Addr_VN order
Read RAM1, RAM2 ..., the side information D_a1 in RAM15, if the 1st iteration, the then side taken out from main storage
Information D_a1=0, by iteration control unit define the order for reading address Addr_VN for 0,1,2 ..., 2047, divide in the following manner
Side information D_a1 VNU1, VNU2, VNU3, VNU4, VNU5 are not delivered into：
RAM1, RAM2 data are sequentially read out according to Addr_VN and give VNU1；
RAM3~RAM5 data are sequentially read out according to Addr_VN and give VNU2；
RAM6 data are sequentially read out according to Addr_VN and give VNU3；
RAM7~RAM9 data are sequentially read out according to Addr_VN and give VNU4；
RAM10~RAM15 data are sequentially read out according to Addr_VN and give VNU5；
The likelihood information updated, the side information D_e1 after being updated are calculated according to D_llr and D_a1；By the side after renewal
Information D_e1 according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN and write ground
Location Addr_VN numerical value is identical, and difference is that allocating time is different, is generated by iteration control unit, be sequence address 0,1,2 ...,
2047；
Iteration control unit produces the reading address Addr_CN of check-node address processing module, and Addr_CN includes Addr_
CN1, Addr_CN2 ..., Addr_CN15, Addr_CN1, Addr_CN2 ..., Addr_CN15 pass through step (3) main storage
RAM1, RAM2 ..., the corresponding submatrixs of RAM15 calculate and obtain；
Code check node processing module according to reading address Addr_CN, from main storage RAM1, RAM2 ..., press in RAM15
In the following manner reads side information D_e1, is designated as side information D_a2, the CNU1 delivered in check-node address processing module, CNU2,
CNU3；
RAM10, RAM11 data are read according to Addr_CN10, Addr_CN11 and give CNU1；
By RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 data respectively according to Addr_CN1, Addr_CN3,
Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 read and give CNU2；
By RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 data respectively according to Addr_CN2, Addr_CN4, Addr_
CN5, Addr_CN8, Addr_CN9, Addr_CN15 read and give CNU3；
The likelihood information updated, the side information D_e2 after being updated again are calculated according to obtained side information D_a2；
Side information D_e2 after renewal is respectively written into master according to address Addr_CN1, Addr_CN2 ..., Addr_CN15
RAM1, RAM2 in memory ..., after RAM15, send this time iteration to iteration control unit and complete signal, read address
Addr_CN is identical with write address Addr_CN numerical value, and difference is that allocating time is different, is generated by iteration control unit；
Iteration control unit receives this time iteration and completes signal, starts next iteration, until reaching the frame of setting
Maximum iteration M, produce decoding termination signal Dec_E, then, by the side information D_ obtained after the completion of last time iteration
E1 ' be that 0 and 1, i.e. D_e1 ' are that just it is negative to adjudicate as 1, D_e1 ' according to positive and negative judgement, is adjudicated as 0, this court verdict is by sentencing
Certainly result output buffer cell exports court verdict, and this frame coding is finished, and then carries out the decoding of next frame, until digital received
All frame likelihood information data decodings of machine demodulation are completed.
The verification square for the quasi-cyclic LDPC code that the check matrix H is R=1/2 for the code check defined in CCSDS standards
Battle array, the code word size N of the quasi-cyclic LDPC code is that 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as：
I in matrix HLWith 0LRespectively 2048 × 2048 dimension unit matrixs and 0 matrix, Πk(k=1,2 ..., 8) be
2048 × 2048 dimension displacement battle arrays, displacement battle array ΠkT rows (t=0,1,2 ..., 2047) nonzero element column position πk(t)
For:
In formula, L=2048, mod represents modular arithmetic,Expression is rounded downwards to 4t/L, column position πk(t) letter in
Number θkWithValue see table 3-3, table 3-4 in CCSDS standard CC SDS 131.1-O-2, it is special with quasi- circulation
Property.
Described Addr_CN is according to check matrix of the code check in CCSDS standards for R=1/2 (8192,4096) LDPC code
H is calculated and obtained.
The D_llr and D_a1 calculate the likelihood information updated, as follows the step of side information D_e1 after being updated：
If n-th, n is 1,2,3,4,5, variable node processing unit reads m information D_a1, m from main storage and is
Positive integer, m ' is 1,2 ... m, m ' represents the sequence number of the individual information of m ' in m information, and the individual information D_a1 (m ') of m ' are corresponding
Fresh information D_e1 is equal to the channel likelihood information D_llr read from channel information memory plus the individual information D_ of removing m '
Other m-1 information D_a1 outside a1 (m ').
The D_a2 calculates the likelihood information updated, as follows the step of side information D_e2 after being updated：
(1) set p-th, p is 1,2,3, code check node processing unit reads k information D_a2, k for just from main storage
The sequence number of k, k ' represent kth in k information ' individual information that integer, k ' is 1,2 ..., kth ' individual information D_a2 (k ') is corresponding more
Fresh information D_e2 symbol bit manipulation is：Remove kth ' k-1 D_a2 sign bit outside individual fresh information D_a2 (k ') it is different
Or；
(2) k information D_a2 amplitude is compared, tries to achieve amplitude min value and amplitude sub-minimum, the two values are led to
Cross correction value multiplier and be multiplied by normalization factor α, by amplitude min value and kth ' amplitude of individual information compares, if identical,
Sub-minimum is exported, if it is different, then exporting minimum value, α scope is 0~1；
(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after being updated.
When the information D_e1 ' for being used to adjudicate output obtained after the completion of the last time iteration is equal to last time iteration
The channel likelihood information D_llr read from channel information memory plus m information D_a1 (m) and value.
Partially-parallel architecture LDPC code interpretation method in a kind of space communication system, including divide LDPC check matrix rank
Section and pipeline system Partly parallel decoding stage：
The division LDPC check matrix stage etch is as follows：
(1) code check defined in CCSDS standards is R=1/2 quasi-cyclic LDPC code, the code word of the quasi-cyclic LDPC code
Length N is that 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as
I in matrix HLWith 0LRespectively 2048 × 2048 dimension unit matrixs and 0 matrix, Πk(k=1,2 ..., 8) be
2048 × 2048 dimension displacement battle arrays, displacement battle array ΠkT rows (t=0,1,2 ..., 2047) nonzero element column position πk(t)
For:
In formula, L=2048, mod represents modular arithmetic,Expression is rounded downwards to 4t/L, column position πk(t) letter in
Number θkWithValue see table 3-3, table 3-4 in CCSDS standard CC SDS 131.1-O-2, it is special with quasi- circulation
Property；
(2) row of the check matrix H of step (1) is divided into 3 to be out of the line respectively：H1 (0-2047 rows), H2 (2048-
4095 rows), H3 (4096-6143 rows)；It is respectively S1 (0-2047 row), S2 (2048- that the row of check matrix H are divided into 5 super row
4095 row), P1 (4096-6143 row), P2 (6144-8191 row), P3 (8192-10239 row)；
(3) data storage needed for defining decoding includes：Channel information memory, main storage and decoding output caching
Unit；Channel information memory is used to cache channel likelihood information, comprising 4 dual port RAMs, and each RAM depth is 2048；It is main
Memory includes 15 memory RAMs, i.e. main storage RAM1, RAM2 ..., RAM15, for storing variable node and verification
Each non-zero submatrices in the side information transmitted between node, each memory RAM correspondence check matrix H, each storage
Device RAM depth is 2048, i.e. main storage RAM1, RAM2 ..., RAM15 corresponds to respectively：
The super row S1 of RAM1 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S1 of RAM2 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The super row S2 of RAM3 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S2 of RAM4 correspondences submatrix Πs corresponding with the H3 that is out of the line5；
The super row S2 of RAM5 correspondences submatrix Πs corresponding with the H3 that is out of the line6；
The super row P1 of RAM6 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P2 of RAM7 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row P2 of RAM8 correspondences submatrix Πs corresponding with the H3 that is out of the line7；
The super row P2 of RAM9 correspondences submatrix Πs corresponding with the H3 that is out of the line8；
The super row P3 of RAM10 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P3 of RAM11 correspondences submatrix Πs corresponding with the H1 that is out of the line1；
The super row P3 of RAM12 correspondences submatrix Πs corresponding with the H2 that is out of the line2；
The super row P3 of RAM13 correspondences submatrix Πs corresponding with the H2 that is out of the line3；
The super row P3 of RAM14 correspondences submatrix Πs corresponding with the H2 that is out of the line4；
The super row P3 of RAM15 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
Decoding output buffer unit is used to export decoding result；
The pipeline system Partly parallel decoding stage etch is as follows：
(4) channel information memory cell receives and stores this current frame likelihood information data of digital receiver demodulation,
And store the likelihood information data order in 4 RAM of channel information memory cell, a frame likelihood information data are 8192
Individual, after the frame is received, channel information memory cell generation one receives signal and is sent to iteration control unit, believes
Road information memory cell receives 8192 data of next frame by ping-pong operation simultaneously；
(5) iteration control unit sends decoding commencing signal to channel information memory cell；Channel information memory cell connects
Receive decoding commencing signal, by the likelihood information data order in 4 RAM the circuit-switched data D_llr of parallel output 4 to variable node
Processing module；
(6) 4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, variable node processing mould
Block includes this 5 variable node processing units of VNU1, VNU2, VNU3, VNU4 and VNU5, and 4 circuit-switched data D_llr is delivered to respectively
VNU1, VNU2, VNU3, VNU4, VNU5 is delivered to by 0 value, at the same variable node processing module from the RAM1 in main storage,
RAM2 ..., in RAM15 according to the RAM1 in memory, RAM2 ..., RAM15 reading address Addr_VN order reads
RAM1, RAM2 ..., the side information D_a1 in RAM15, if the 1st iteration, then the side information taken out from main storage
D_a1=0, by iteration control unit define the order for reading address Addr_VN for 0,1,2 ..., 2047, respectively will in the following manner
Side information D_a1 delivers to VNU1, VNU2, VNU3, VNU4, VNU5, and variable node processing unit is that 5 tunnels are parallel：
RAM1, RAM2 data are sequentially read out according to Addr_VN and give VNU1；
RAM3~RAM5 data are sequentially read out according to Addr_VN and give VNU2；
RAM6 data are sequentially read out according to Addr_VN and give VNU3；
RAM7~RAM9 data are sequentially read out according to Addr_VN and give VNU4；
RAM10~RAM15 data are sequentially read out according to Addr_VN and give VNU5；
(7) likelihood information updated is calculated according to the D_llr and D_a1 obtained in step (6), the side letter after being updated
Cease D_e1；
(8) by the side information D_e2 after updating in step (7) according to write address Addr_VN write main storage RAM1,
RAM2 ..., RAM15, read address Addr_VN it is identical with write address Addr_VN numerical value, difference be allocating time difference, by
Iteration control unit generate, be sequence address 0,1,2 ..., 2047；
(9) iteration control unit produces the reading address Addr_CN of code check node processing module, and Addr_CN includes Addr_
CN1, Addr_CN2 ... Addr_CN15, Addr_CN1, Addr_CN2 ... Addr_CN15 by step (3) main storage RAM1,
RAM2 ..., the corresponding submatrixs of RAM15 calculate and obtain；
Code check node processing module include CNU1, CNU2, CNU3, code check node processing module according to read address Addr_CN,
From main storage RAM1, RAM2 ..., the side information D_e1 in RAM15 in the following manner in reading step (8), be designated as side letter
Cease D_a2, CNU1, CNU2, the CNU3 delivered in code check node processing module, the CNU1 of code check node processing module, CNU2,
CNU3 is that 3 tunnels are parallel；
RAM10, RAM11 data are read according to Addr_CN10, Addr_CN11 and give CNU1；
By RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 data respectively according to Addr_CN1, Addr_CN3,
Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 read and give CNU2；
By RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 data respectively according to Addr_CN2, Addr_CN4, Addr_
CN5, Addr_CN8, Addr_CN9, Addr_CN15 read and give CNU3；
(10) likelihood information updated, the side information D_e2 after being updated are calculated according to the D_a2 obtained in step (9)；
(11) by the side information D_e2 after being updated in step (10) according to address Addr_CN1, Addr_CN2 ... Addr_
CN15 be respectively written into the RAM1 in main storage, RAM2 ..., after RAM15, send this time iteration to iteration control unit complete
Into signal, reading address Addr_CN is identical with write address Addr_CN numerical value, and difference is that allocating time is different, by iteration control list
Member generation；
(12) iteration control unit receives this time iteration completion signal of step (11), starts next iteration, that is, weighs
Multiple step is according to step (5)~step (12), until reaching the maximum iteration M of the frame of setting, produces decoding and terminates letter
Number Dec_E, according to positive and negative judgement be that 0 and 1, i.e. D_e1 ' are just, to sentence by the D_e1 ' obtained after the completion of last time iteration then
Certainly 1, D_e1 ' be negative, adjudicate as 0, this court verdict is translated by court verdict output buffer cell output court verdict, this frame
Code is finished, and is then returned to the decoding that step (4) carries out next frame, until all frame likelihood information data that digital receiver is demodulated
Decoding is completed.
Addr_CN described in the step (9) and (11) according to code check in CCSDS standards for R=1/2 (8192,
4096) H-matrix of LDPC code is calculated and obtained.
：D_llr and D_a1 calculates the likelihood information updated in the step (7), the side information D_e1's after being updated
Step is as follows：
If n-th, n is 1,2,3,4,5, variable node processing unit reads m information D_a1, m from main storage and is
Positive integer, m ' is 1,2 ... m, m ' represents the sequence number of the individual information of m ' in m information, and the individual information D_a1 (m ') of m ' are corresponding
Fresh information D_e1 is equal to the channel likelihood information D_llr read from channel information memory plus the individual information D_ of removing m '
Other m-1 information D_a1 outside a1 (m ').
The step of D_a2 calculates the likelihood information updated, side information D_e2 after being updated in the step (10) is such as
Under：
(1) set p-th, p is 1,2,3, code check node processing unit reads k information D_a2, k for just from main storage
The sequence number of k, k ' represent kth in k information ' individual information that integer, k ' is 1,2 ..., kth ' individual information D_a2 (k ') is corresponding more
Fresh information D_e2 symbol bit manipulation is：Remove kth ' k-1 D_a2 sign bit outside individual fresh information D_a2 (k ') it is different
Or；
(2) k information D_a2 amplitude is compared, tries to achieve amplitude min value and amplitude sub-minimum, the two values are led to
Cross correction value multiplier and be multiplied by normalization factor α, by amplitude min value and kth ' amplitude of individual information compares, if identical,
Sub-minimum is exported, if it is different, then exporting minimum value, α scope is 0~1；
(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after being updated.
The information D_e1 ' for being used to adjudicate output obtained in the step (12) after the completion of last time iteration is equal to finally
The channel likelihood information D_llr read during an iteration from channel information memory plus m information D_a1 (m) and value.
The advantage of the present invention compared with prior art is：
(1) the check matrix structure of code check R=1/2 (8192,4096) LDPC code in CCSDS systems is directed in the present invention
Figure has the characteristics of being out of the line, surpass row, main storage simple in construction is devised, with non-zero submatrices one in check matrix structure chart
One correspondence；The address processing unit of reading data is simple in construction from main storage, be easily achieved.
(2) Partly parallel decoding structure design of the invention several parallel code check node processing units that are out of the line, super row
Several parallel variable node processing units, the implementation complexity of node messages more new algorithm is low, and institute's cost source is few.
(3) decoding performance of the Partly parallel decoding designed by the present invention is good, and coding gain is up to 9dB.Meanwhile, the part
Parallel decoding structure extends to other code efficiency LDPC code words.
Brief description of the drawings
Fig. 1 is the check matrix structure chart of LDPC code word in interpretation method of the present invention；
Fig. 2 is the system block diagram of the partially-parallel architecture of interpretation method of the present invention；
The schematic diagram for the address Addr_CN that Fig. 3 uses for code check node processing in the structure of interpretation method of the present invention；
Fig. 4 is subframe Π in the structure of interpretation method of the present invention1The read/write address Addr_CN signals of corresponding main storage
Figure.
Embodiment
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
As shown in Fig. 2 partially-parallel architecture LDPC code decoding system in a kind of space communication system, including iteration control list
Member, channel information memory, main storage, variable node processing module, code check node processing module, court verdict output buffering
Unit；
Channel information memory includes 4 dual port RAMs, and each RAM depth is L=2048, and main storage includes 15
Memory RAM, i.e. main storage RAM1, RAM2 ..., RAM15, for storing what is transmitted between variable node and check-node
Side information, the verification for the quasi-cyclic LDPC code that code efficiency of each memory RAM correspondence defined in CCSDS standards is R=1/2
Each non-zero submatrices in matrix H, each memory RAM depth is L=2048, i.e. main storage RAM1,
RAM2 ..., RAM15 respectively correspond to it is as follows：
The super row S1 of RAM1 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S1 of RAM2 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The super row S2 of RAM3 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S2 of RAM4 correspondences submatrix Πs corresponding with the H3 that is out of the line5；
The super row S2 of RAM5 correspondences submatrix Πs corresponding with the H3 that is out of the line6；
The super row P1 of RAM6 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P2 of RAM7 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row P2 of RAM8 correspondences submatrix Πs corresponding with the H3 that is out of the line7；
The super row P2 of RAM9 correspondences submatrix Πs corresponding with the H3 that is out of the line8；
The super row P3 of RAM10 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P3 of RAM11 correspondences submatrix Πs corresponding with the H1 that is out of the line1；
The super row P3 of RAM12 correspondences submatrix Πs corresponding with the H2 that is out of the line2；
The super row P3 of RAM13 correspondences submatrix Πs corresponding with the H2 that is out of the line3；
The super row P3 of RAM14 correspondences submatrix Πs corresponding with the H2 that is out of the line4；
The super row P3 of RAM15 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The row of check matrix H is divided into 3 be out of the line respectively H1, H2, H3, H1 be 0-2047 rows, H2 be 2048-4095 rows,
H3 is 4096-6143 rows；The row of check matrix H are divided into 5 super row S1, S2, P1, P2, P3, S1 is that 0-2047 is arranged, S2 is
2048-4095 row, P1 are that 4096-6143 is arranged, P2 is that 6144-8191 is arranged, P3 is 8192-10239 row, and this matrix divides such as Fig. 1
It is shown；
Variable node processing module includes this 5 variable node processing units of VNU1, VNU2, VNU3, VNU4 and VNU5, becomes
It is that 5 tunnels are parallel to measure endpoint processing unit；
Check-node address processing module includes CNU1, CNU2, CNU3 these three code check node processing units, CNU1,
CNU2, CNU3 are that 3 tunnels are parallel；
Channel information memory cell receives and stores this current frame likelihood information data of digital receiver demodulation, and will
In 4 RAM for storing to the likelihood information data order channel information memory cell, a frame likelihood information data are 8192
Individual, after the frame is received, channel information memory cell generation one receives signal and is sent to iteration control unit, believes
Road information memory cell receives 8192 data of next frame by ping-pong operation simultaneously；
Iteration control unit receives to receive after signal sends decoding commencing signal, channel to channel information memory cell
Information memory cell receives decoding commencing signal, by the ground of the likelihood information data order in the 4 RAM circuit-switched data of parallel output 4
D_llr gives variable node processing module,
4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, 4 circuit-switched data D_llr is divided
VNU1, VNU2, VNU3, VNU4 are not delivered to, 0 value is delivered into VNU5, while variable node processing module is from main storage
RAM1, RAM2 ..., in RAM15 according to the RAM1 in memory, RAM2 ..., RAM15 reading address Addr_VN order
Read RAM1, RAM2 ..., the side information D_a1 in RAM15, if the 1st iteration, the then side taken out from main storage
Information D_a1=0, by iteration control unit define the order for reading address Addr_VN for 0,1,2 ..., 2047, divide in the following manner
Side information D_a1 VNU1, VNU2, VNU3, VNU4, VNU5 are not delivered into：
RAM1, RAM2 data are sequentially read out according to Addr_VN and give VNU1；
RAM3~RAM5 data are sequentially read out according to Addr_VN and give VNU2；
RAM6 data are sequentially read out according to Addr_VN and give VNU3；
RAM7~RAM9 data are sequentially read out according to Addr_VN and give VNU4；
RAM10~RAM15 data are sequentially read out according to Addr_VN and give VNU5；
The likelihood information updated, the side information D_e1 after being updated are calculated according to D_llr and D_a1；By the side after renewal
Information D_e1 according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN and write ground
Location Addr_VN numerical value is identical, and difference is that allocating time is different, is generated by iteration control unit, be sequence address 0,1,2 ...,
2047；
Iteration control unit produces the reading address Addr_CN of check-node address processing module, and Addr_CN includes Addr_
CN1, Addr_CN2 ..., Addr_CN15, Addr_CN1, Addr_CN2 ..., Addr_CN15 pass through step (3) main storage
RAM1, RAM2 ..., the corresponding submatrixs of RAM15 calculate and obtain；
Code check node processing module according to reading address Addr_CN, from main storage RAM1, RAM2 ..., press in RAM15
In the following manner reads side information D_e1, is designated as side information D_a2, the CNU1 delivered in check-node address processing module, CNU2,
CNU3；
RAM10, RAM11 data are read according to Addr_CN10, Addr_CN11 and give CNU1；
By RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 data respectively according to Addr_CN1, Addr_CN3,
Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 read and give CNU2；
By RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 data respectively according to Addr_CN2, Addr_CN4, Addr_
CN5, Addr_CN8, Addr_CN9, Addr_CN15 read and give CNU3；
The likelihood information updated, the side information D_e2 after being updated again are calculated according to obtained side information D_a2；
Side information D_e2 after renewal is respectively written into master according to address Addr_CN1, Addr_CN2 ..., Addr_CN15
RAM1, RAM2 in memory ..., after RAM15, send this time iteration to iteration control unit and complete signal, read address
Addr_CN is identical with write address Addr_CN numerical value, and difference is that allocating time is different, is generated by iteration control unit；
Iteration control unit receives this time iteration and completes signal, starts next iteration, until reaching the frame of setting
Maximum iteration M, produce decoding termination signal Dec_E, then, by the side information D_ obtained after the completion of last time iteration
E1 ' be that 0 and 1, i.e. D_e1 ' are that just it is negative to adjudicate as 1, D_e1 ' according to positive and negative judgement, is adjudicated as 0, this court verdict is by sentencing
Certainly result output buffer cell exports court verdict, and this frame coding is finished, and then carries out the decoding of next frame, until digital received
All frame likelihood information data decodings of machine demodulation are completed.
The verification square for the quasi-cyclic LDPC code that the check matrix H is R=1/2 for the code check defined in CCSDS standards
Battle array, the code word size N of the quasi-cyclic LDPC code is that 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as：
I in matrix HLWith 0LRespectively 2048 × 2048 dimension unit matrixs and 0 matrix, Πk(k=1,2 ..., 8) be
2048 × 2048 dimension displacement battle arrays, displacement battle array ΠkT rows (t=0,1,2 ..., 2047) nonzero element column position πk(t)
For:
In formula, L=2048, mod represents modular arithmetic,Expression is rounded downwards to 4t/L, column position πk(t) letter in
Number θkWithValue see table 3-3, table 3-4 in CCSDS standard CC SDS 131.1-O-2, it is special with quasi- circulation
Property.
Described Addr_CN is according to check matrix of the code check in CCSDS standards for R=1/2 (8192,4096) LDPC code
H is calculated and obtained.
The D_llr and D_a1 calculate the likelihood information updated, as follows the step of side information D_e1 after being updated：
If n-th, n is 1,2,3,4,5, variable node processing unit reads m information D_a1, m from main storage and is
Positive integer, m ' is 1,2 ... m, m ' represents the sequence number of the individual information of m ' in m information, and the individual information D_a1 (m ') of m ' are corresponding
Fresh information D_e1 is equal to the channel likelihood information D_llr read from channel information memory plus the individual information D_ of removing m '
Other m-1 information D_a1 outside a1 (m ').
The D_a2 calculates the likelihood information updated, as follows the step of side information D_e2 after being updated：
(1) set p-th, p is 1,2,3, code check node processing unit reads k information D_a2, k for just from main storage
The sequence number of k, k ' represent kth in k information ' individual information that integer, k ' is 1,2 ..., kth ' individual information D_a2 (k ') is corresponding more
Fresh information D_e2 symbol bit manipulation is：Remove kth ' k-1 D_a2 sign bit outside individual fresh information D_a2 (k ') it is different
Or；
(2) k information D_a2 amplitude is compared, tries to achieve amplitude min value and amplitude sub-minimum, the two values are led to
Cross correction value multiplier and be multiplied by normalization factor α, by amplitude min value and kth ' amplitude of individual information compares, if identical,
Sub-minimum is exported, if it is different, then exporting minimum value, α scope is 0~1；
(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after being updated.
When the information D_e1 ' for being used to adjudicate output obtained after the completion of the last time iteration is equal to last time iteration
The channel likelihood information D_llr read from channel information memory plus m information D_a1 (m) and value.
Partially-parallel architecture LDPC code interpretation method in a kind of space communication system, including divide LDPC check matrix rank
Section and pipeline system Partly parallel decoding stage：
Divide LDPC check matrix stage etch as follows：
(1) code check defined in CCSDS standards is R=1/2 quasi-cyclic LDPC code, the code word of the quasi-cyclic LDPC code
Length N is that 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as
I in matrix HLWith 0LRespectively 2048 × 2048 dimension unit matrixs and 0 matrix, Πk(k=1,2 ..., 8) be
2048 × 2048 dimension displacement battle arrays, displacement battle array ΠkT rows (t=0,1,2 ..., 2047) nonzero element column position πk(t)
For:
In formula, L=2048, mod represents modular arithmetic,Expression is rounded downwards to 4t/L, column position πk(t) letter in
Number θkWithValue see table 3-3, table 3-4 in CCSDS standard CC SDS 131.1-O-2, it is special with quasi- circulation
Property；
(2) row of the check matrix H of step (1) is divided into 3 to be out of the line respectively：H1 (0-2047 rows), H2 (2048-
4095 rows), H3 (4096-6143 rows)；It is respectively S1 (0-2047 row), S2 (2048- that the row of check matrix H are divided into 5 super row
4095 row), P1 (4096-6143 row), P2 (6144-8191 row), P3 (8192-10239 row), this matrix division as shown in Figure 1；
(3) data storage needed for defining decoding includes：Channel information memory, main storage and decoding output caching
Unit；Channel information memory is used to cache channel likelihood information, comprising 4 dual port RAMs, and each RAM depth is 2048；It is main
Memory includes 15 memory RAMs, i.e. main storage RAM1, RAM2 ..., RAM15, for storing variable node and verification
Each non-zero submatrices in the side information transmitted between node, each memory RAM correspondence check matrix H, each storage
Device RAM depth is 2048, i.e. main storage RAM1, RAM2 ..., RAM15 corresponds to respectively：
The super row S1 of RAM1 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S1 of RAM2 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The super row S2 of RAM3 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S2 of RAM4 correspondences submatrix Πs corresponding with the H3 that is out of the line5；
The super row S2 of RAM5 correspondences submatrix Πs corresponding with the H3 that is out of the line6；
The super row P1 of RAM6 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P2 of RAM7 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row P2 of RAM8 correspondences submatrix Πs corresponding with the H3 that is out of the line7；
The super row P2 of RAM9 correspondences submatrix Πs corresponding with the H3 that is out of the line8；
The super row P3 of RAM10 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P3 of RAM11 correspondences submatrix Πs corresponding with the H1 that is out of the line1；
The super row P3 of RAM12 correspondences submatrix Πs corresponding with the H2 that is out of the line2；
The super row P3 of RAM13 correspondences submatrix Πs corresponding with the H2 that is out of the line3；
The super row P3 of RAM14 correspondences submatrix Πs corresponding with the H2 that is out of the line4；
The super row P3 of RAM15 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
Decoding output buffer unit is used to export decoding result；
Pipeline system Partly parallel decoding stage etch is as follows：
(4) channel information memory cell receives and stores this current frame likelihood information data of digital receiver demodulation,
And store the likelihood information data order in 4 RAM of channel information memory cell, a frame likelihood information data are 8192
Individual, after the frame is received, channel information memory cell generation one receives signal and is sent to iteration control unit, believes
Road information memory cell receives 8192 data of next frame by ping-pong operation simultaneously；
(5) iteration control unit sends decoding commencing signal to channel information memory cell；Channel information memory cell connects
Receive decoding commencing signal, by the likelihood information data order in 4 RAM the circuit-switched data D_llr of parallel output 4 to variable node
Processing module；
(6) 4 circuit-switched data D_llr of variable node processing module receiving channel information memory cell, variable node processing mould
Block includes this 5 variable node processing units of VNU1, VNU2, VNU3, VNU4 and VNU5, and 4 circuit-switched data D_llr is delivered to respectively
VNU1, VNU2, VNU3, VNU4, VNU5 is delivered to by 0 value, at the same variable node processing module from the RAM1 in main storage,
RAM2 ..., in RAM15 according to the RAM1 in memory, RAM2 ..., RAM15 reading address Addr_VN order reads
RAM1, RAM2 ..., the side information D_a1 in RAM15, if the 1st iteration, then the side information taken out from main storage
D_a1=0, by iteration control unit define the order for reading address Addr_VN for 0,1,2 ..., 2047, respectively will in the following manner
Side information D_a1 delivers to VNU1, VNU2, VNU3, VNU4, VNU5, and variable node processing unit is that 5 tunnels are parallel：
RAM1, RAM2 data are sequentially read out according to Addr_VN and give VNU1；
RAM3~RAM5 data are sequentially read out according to Addr_VN and give VNU2；
RAM6 data are sequentially read out according to Addr_VN and give VNU3；
RAM7~RAM9 data are sequentially read out according to Addr_VN and give VNU4；
RAM10~RAM15 data are sequentially read out according to Addr_VN and give VNU5；
(7) likelihood information updated is calculated according to the D_llr and D_a1 obtained in step (6), the side letter after being updated
Cease D_e1；
(8) by the side information D_e2 after updating in step (7) according to write address Addr_VN write main storage RAM1,
RAM2 ..., RAM15, read address Addr_VN it is identical with write address Addr_VN numerical value, difference be allocating time difference, by
Iteration control unit generate, be sequence address 0,1,2 ..., 2047；
(9) iteration control unit produces the reading address Addr_CN of code check node processing module, and Addr_CN includes Addr_
CN1, Addr_CN2 ... Addr_CN15, Addr_CN1, Addr_CN2 ... Addr_CN15 by step (3) main storage RAM1,
RAM2 ..., the corresponding submatrixs of RAM15 calculate and obtain；
Code check node processing module include CNU1, CNU2, CNU3, code check node processing module according to read address Addr_CN,
From main storage RAM1, RAM2 ..., the side information D_e1 in RAM15 in the following manner in reading step (8), be designated as side letter
Cease D_a2, CNU1, CNU2, the CNU3 delivered in code check node processing module, the CNU1 of code check node processing module, CNU2,
CNU3 is that 3 tunnels are parallel；
RAM10, RAM11 data are read according to Addr_CN10, Addr_CN11 and give CNU1；
By RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 data respectively according to Addr_CN1, Addr_CN3,
Addr_CN7, Addr_CN12, Addr_CN13, Addr_CN14 read and give CNU2；
By RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 data respectively according to Addr_CN2, Addr_CN4, Addr_
CN5, Addr_CN8, Addr_CN9, Addr_CN15 read and give CNU3；
(10) likelihood information updated, the side information D_e2 after being updated are calculated according to the D_a2 obtained in step (9)；
(11) by the side information D_e2 after being updated in step (10) according to address Addr_CN1, Addr_CN2 ... Addr_
CN15 be respectively written into the RAM1 in main storage, RAM2 ..., after RAM15, send this time iteration to iteration control unit complete
Into signal, reading address Addr_CN is identical with write address Addr_CN numerical value, and difference is that allocating time is different, by iteration control list
Member generation；
(12) iteration control unit receives this time iteration completion signal of step (11), starts next iteration, that is, weighs
Multiple step is according to step (5)~step (12), until reaching the maximum iteration M of the frame of setting, produces decoding and terminates letter
Number Dec_E, according to positive and negative judgement be that 0 and 1, i.e. D_e1 ' are just, to sentence by the D_e1 ' obtained after the completion of last time iteration then
Certainly 1, D_e1 ' be negative, adjudicate as 0, this court verdict is translated by court verdict output buffer cell output court verdict, this frame
Code is finished, and is then returned to the decoding that step (4) carries out next frame, until all frame likelihood information data that digital receiver is demodulated
Decoding is completed.
Addr_CN described in step (9) and (11) is according to (8192,4096) that code check in CCSDS standards is R=1/2
The H-matrix of LDPC code is calculated and obtained.For example for the H1 that is out of the line submatrix Is corresponding with super row P3L、Π1It is respectively as shown in Figure 4.That
Address Addr_CN value is 1644,1645 ..., 2047,1536,1537 ..., 1643,0,1 ..., 1535.It can similarly obtain
To other addresses, all address Addr_CN are as shown in Figure 3.
D_llr and D_a1 calculate the likelihood information updated in step (7), the step of side information D_e1 after being updated such as
Under：
If n-th, n is 1,2,3,4,5, variable node processing unit reads m information D_a1, m from main storage and is
Positive integer, m ' is 1,2 ... m, m ' represents the sequence number of the individual information of m ' in m information, and the individual information D_a1 (m ') of m ' are corresponding
Fresh information D_e1 is equal to the channel likelihood information D_llr read from channel information memory plus the individual information D_ of removing m '
Other m-1 information D_a1 outside a1 (m ').
For example, during for n=2, correspondence VNU2 units read 1 channel likelihood information D_ from channel information memory
Llr, reads m=3 information D_a1 from RAM3~RAM5 of main storage.So m '=1 information D_a1 (1) is corresponding
Fresh information D_e1=D_llr+D_a1 (2)+D_a1 (3)；The corresponding fresh information D_e1=of m '=2 information D_a1 (2)
D_llr+D_a1(1)+D_a1(3)；The corresponding fresh information D_e1=D_llr+D_a1 (1) of m '=3 information D_a1 (3)+
D_a1(2)；
The information D_e1 ' for being used to adjudicate output obtained in step (12) after the completion of last time iteration is equal to last time
The channel likelihood information D_llr read during iteration from channel information memory plus m information D_a1 (m) and value.For example,
During for n=2, correspondence VNU2 units read 1 channel likelihood information D_llr, from main storage from channel information memory
RAM3~RAM5 in read m=3 information D_a1.So D_e1 '=D_llr+D_a1 (1)+D_a1 (2)+D_a1 (3),
Realize in structure, combined here by fresh information D_e1 computational items corresponding with the individual information D_a1 of m ', only need to first be calculated
D_e1 ' and then D_a1 (m ') is subtracted so as to overall reduction implementation complexity.
Corresponding fresh information the D_e1=D_e1 '-D_a1 (1) of so m '=1 information D_a1 (1)；Believe m '=2
Cease corresponding fresh information the D_e1=D_e1 '-D_a1 (2) of D_a1 (2)；The corresponding fresh informations of m '=3 information D_a1 (3)
D_e1=D_e1 '-D_a1 (3)；
The step of D_a2 calculates the likelihood information updated, side information D_e2 after being updated in step (10) is as follows：(1)
If p-th, p is 1,2,3, it is positive integer that code check node processing unit reads k information D_a2, k from main storage, and k ' is 1,
2 ... k, k ' represent the corresponding fresh information D_e2's of the individual information D_a2 (k ') of the kth sequence number of individual information ', kth ' in k information
Symbol bit manipulation is：Remove kth ' XOR of k-1 D_a2 sign bit outside individual fresh information D_a2 (k ').(2) by k letter
Breath D_a2 amplitude compares, and tries to achieve amplitude min value and amplitude sub-minimum, the two values are multiplied by by correction value multiplier
The amplitude of the individual information of normalization factor α, by amplitude min value and kth ' compares, if identical, exports sub-minimum, if it is different,
Minimum value is then exported, α scope is 0~1.(3) according to the sign bit of step (1) and the range value of step (2), obtain after renewal
Side information D_e2.For example, for p=3, correspondence CNU3 units, from the RAM2 of main storage, RAM4, RAM5, RAM8, RAM9,
The corresponding fresh information D_e2 computational methods of the individual information D_a2 (k ') of the k=6 data D_a2 that RAM15 is read, then kth ' are：
Compare k=6 data D_a2 size, obtain minimum value D_a2 (min1) and sub-minimum D_a2 (min2), then
For kth '=corresponding fresh information the D_e2 of 1 information D_a2 (k ') sign bit sgn (1 ')=XOR { sgn [D_a2
(2)], sgn [D_a2 (3)], sgn [D_a2 (4)], sgn [D_a2 (5)], sgn [D_a2 (6)] }, then if D_a2 (1)=D_
A2 (min1), D_e2=sgn (1 ') × D_a2 (min2), otherwise D_e2=sgn (1 ') × D_a2 (min1)；For kth '=2
The corresponding fresh information D_e2 of individual information D_a2 (k ') sign bit sgn (2 ')=XOR { sgn [D_a2 (1)], sgn [D_a2
(3)], sgn [D_a2 (4)], sgn [D_a2 (5)], sgn [D_a2 (6)] }, then if D_a2 (2)=D_a2 (min1), D_e2
=sgn (1 ') × D_a2 (min2), otherwise D_e2=sgn (1 ') × D_a2 (min1), for kth '=3,4,5,6 similarly can be with
Obtain.
Embodiment：
Carry out upper plate test on modem platform, FPGA model xc6slx150, using ISE13.4 and
ModelSim6.5g developing instruments, quasi-cyclic LDPC (8192,4096) code is completed by Verilog HDL hardware description languages
The design of decoder.
When data rate is 4Mbps, modulation system is BPSK, during selection 1/2 code check (8192,4096) LDPC code, system
Test result is：When decoding iteration number of times maximum is set to M=45, correspondence BER=1-10-7Demodulation threshold be 2.2dB, phase
The coding gain answered is 9dB.
The resource requirement of the decoder is as follows：Register number：2221, LUT numbers：2119；18k memory RAMs：29；
Non-elaborated part of the present invention belongs to techniques well known.
Claims (10)
1. partially-parallel architecture LDPC code decoding system in a kind of space communication system, it is characterised in that：Including iteration control list
Member, channel information memory, main storage, variable node processing module, code check node processing module, court verdict output buffering
Unit；
Channel information memory includes 4 dual port RAMs, and each RAM depth is L=2048, and main storage includes 15 storages
Device RAM, i.e. main storage RAM1, RAM2 ..., RAM15, transmitted for storing between variable node and check-node side letter
Breath, the check matrix for the quasi-cyclic LDPC code that code efficiency of each memory RAM correspondence defined in CCSDS standards is R=1/2
Each non-zero submatrices in H, each memory RAM depth is L=2048, i.e. main storage RAM1, RAM2 ...,
RAM15 corresponds to as follows respectively：
The super row S1 of RAM1 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S1 of RAM2 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The super row S2 of RAM3 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S2 of RAM4 correspondences submatrix Πs corresponding with the H3 that is out of the line5；
The super row S2 of RAM5 correspondences submatrix Πs corresponding with the H3 that is out of the line6；
The super row P1 of RAM6 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P2 of RAM7 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row P2 of RAM8 correspondences submatrix Πs corresponding with the H3 that is out of the line7；
The super row P2 of RAM9 correspondences submatrix Πs corresponding with the H3 that is out of the line8；
The super row P3 of RAM10 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P3 of RAM11 correspondences submatrix Πs corresponding with the H1 that is out of the line1；
The super row P3 of RAM12 correspondences submatrix Πs corresponding with the H2 that is out of the line2；
The super row P3 of RAM13 correspondences submatrix Πs corresponding with the H2 that is out of the line3；
The super row P3 of RAM14 correspondences submatrix Πs corresponding with the H2 that is out of the line4；
The super row P3 of RAM15 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The row of check matrix H is divided into 3 be out of the line respectively H1, H2, H3, and H1 is that 0-2047 rows, H2 are that 2048-4095 rows, H3 are
4096-6143 rows；The row of check matrix H are divided into 5 super row S1, S2, P1, P2, P3, S1 is that 0-2047 is arranged, S2 is 2048-
4095 row, P1 are that 4096-6143 is arranged, P2 is that 6144-8191 is arranged, P3 is 8192-10239 row；
Variable node processing module includes VNU1, VNU2, VNU3, VNU4 and VNU5 this 5 variable node processing units, variable section
Point processing unit is that 5 tunnels are parallel；
Check-node address processing module includes CNU1, CNU2, CNU3 these three code check node processing units, CNU1, CNU2,
CNU3 is that 3 tunnels are parallel；
Channel information memory receives and stores this current frame likelihood information data of digital receiver demodulation, and by the likelihood
Information data is stored sequentially in 4 RAM of channel information memory, and a frame likelihood information data are 8192, when the frame
After receiving, channel information memory generation one receives signal and is sent to iteration control unit, channel information storage
Device receives 8192 data of next frame by ping-pong operation simultaneously；
Iteration control unit receives to receive after signal sends decoding commencing signal to channel information memory, and channel information is deposited
Reservoir receives decoding commencing signal, by the likelihood information data order in 4 RAM the circuit-switched data D_llr of parallel output 4 to become
Measure node processing module,
4 circuit-switched data D_llr of variable node processing module receiving channel information memory, 4 circuit-switched data D_llr is delivered to respectively
VNU1, VNU2, VNU3, VNU4, VNU5 is delivered to by 0 value, at the same variable node processing module from the RAM1 in main storage,
RAM2 ..., in RAM15 according to the RAM1 in memory RAM, RAM2 ..., RAM15 reading address Addr_VN order reads
Take RAM1, RAM2 ..., the side information D_a1 in RAM15, if the 1st iteration, then the side letter taken out from main storage
Cease D_a1=0, by iteration control unit define the order for reading address Addr_VN for 0,1,2 ..., 2047, distinguish in the following manner
Side information D_a1 is delivered into VNU1, VNU2, VNU3, VNU4, VNU5：
RAM1, RAM2 data are sequentially read out according to Addr_VN and give VNU1；
RAM3~RAM5 data are sequentially read out according to Addr_VN and give VNU2；
RAM6 data are sequentially read out according to Addr_VN and give VNU3；
RAM7~RAM9 data are sequentially read out according to Addr_VN and give VNU4；
RAM10~RAM15 data are sequentially read out according to Addr_VN and give VNU5；
The likelihood information updated, the side information D_e1 after being updated are calculated according to D_llr and D_a1；By the side information after renewal
D_e1 according to write address Addr_VN write main storage RAM1, RAM2 ..., RAM15, read address Addr_VN and write address
Addr_VN numerical value is identical, and difference is that allocating time is different, is generated by iteration control unit, be sequence address 0,1,2 ...,
2047；
Iteration control unit produce check-node address processing module reading address Addr_CN, Addr_CN include Addr_CN1,
Addr_CN2 ..., Addr_CN15, Addr_CN1, Addr_CN2 ..., Addr_CN15 by main storage RAM1,
RAM2 ..., the corresponding submatrixs of RAM15 calculate and obtain；
Code check node processing module according to reading address Addr_CN, from main storage RAM1, RAM2 ..., in RAM15 by following
Mode reads side information D_e1, is designated as side information D_a2, CNU1, CNU2, the CNU3 delivered in check-node address processing module；
RAM10, RAM11 data are read according to Addr_CN10, Addr_CN11 and give CNU1；
By RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 data respectively according to Addr_CN1, Addr_CN3, Addr_
CN7, Addr_CN12, Addr_CN13, Addr_CN14 read and give CNU2；
By RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 data respectively according to Addr_CN2, Addr_CN4, Addr_CN5,
Addr_CN8, Addr_CN9, Addr_CN15 read and give CNU3；
The likelihood information updated, the side information D_e2 after being updated again are calculated according to obtained side information D_a2；
Side information D_e2 after renewal is respectively written into primary storage according to address Addr_CN1, Addr_CN2 ..., Addr_CN15
RAM1, RAM2 in device ..., after RAM15, send this time iteration to iteration control unit and complete signal, read address Addr_
CN is identical with write address Addr_CN numerical value, and difference is that allocating time is different, is generated by iteration control unit；
Iteration control unit receives this time iteration and completes signal, starts next iteration, until reaching the frame of setting most
Big iterations M, produces decoding termination signal Dec_E, then, by the side information D_e1 ' obtained after the completion of last time iteration
Be 0 and 1, i.e. D_e1 ' for just, it be negative to adjudicate as 1, D_e1 ' according to positive and negative judgement, adjudicate as 0, this court verdict passes through judgement knot
Fruit output buffer cell output court verdict, this frame coding is finished, and the decoding of next frame is then carried out, until digital receiver solution
All frame likelihood information data decodings adjusted are completed.
2. partially-parallel architecture LDPC code decoding system, its feature in a kind of space communication system according to claim 1
It is：The check matrix for the quasi-cyclic LDPC code that the check matrix H is R=1/2 for the code check defined in CCSDS standards,
The code word size N of the quasi-cyclic LDPC code is that 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as：
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</msub>
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</mtr>
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<mi>&Pi;</mi>
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</mfenced>
</mrow>
I in matrix HLWith 0LRespectively 2048 × 2048 dimension unit matrixs and 0 matrix, Πk(k=1,2 ..., 8) for 2048 ×
2048 dimension displacement battle arrays, displacement battle array ΠkT rows (t=0,1,2 ..., 2047) nonzero element column position πk(t) it is:
In formula, L=2048, mod represents modular arithmetic,Expression is rounded downwards to 4t/L, θkWithFor row position
Put πk(t) function in.
3. partially-parallel architecture LDPC code decoding system, its feature in a kind of space communication system according to claim 2
It is：Described Addr_CN is according to check matrix H meter of the code check in CCSDS standards for R=1/2 (8192,4096) LDPC code
Obtain.
4. partially-parallel architecture LDPC code decoding system, its feature in a kind of space communication system according to claim 1
It is：The D_llr and D_a1 calculate the likelihood information updated, as follows the step of side information D_e1 after being updated：
If n-th, n is 1,2,3,4,5, it is just whole that variable node processing unit reads m information D_a1, m from main storage
Number, m ' be 1,2 ... m, m ' represent m information in the individual information of m ' sequence number, the individual information D_a1 (m ') of m ' it is corresponding renewal
Information D_e1 is equal to the channel likelihood information D_llr read from channel information memory plus the individual information D_a1 of removing m '
Other m-1 information D_a1 outside (m ').
5. partially-parallel architecture LDPC code decoding system, its feature in a kind of space communication system according to claim 1
It is：The D_a2 calculates the likelihood information updated, as follows the step of side information D_e2 after being updated：
(1) set p-th, p is 1,2,3, it is just whole that code check node processing unit reads k information D_a2, k from main storage
The sequence number of k, k ' represent kth in k information ' individual information that number, k ' is 1,2 ..., kth ' the corresponding renewal of individual information D_a2 (k ')
Information D_e2 symbol bit manipulation is：Remove kth ' XOR of k-1 D_a2 sign bit outside individual fresh information D_a2 (k ')；
(2) k information D_a2 amplitude is compared, tries to achieve amplitude min value and amplitude sub-minimum, by the two values by repairing
Normalization factor α being multiplied by the occasion of multiplier, by amplitude min value and kth ' amplitude of individual information compares, if identical, exports
Sub-minimum, if it is different, then exporting minimum value, α scope is 0~1；
(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after being updated.
6. partially-parallel architecture LDPC code decoding system, its feature in a kind of space communication system according to claim 1
It is：Obtained after the completion of the last time iteration be used for adjudicate output information D_e1 ' be equal to last time iteration when from
The channel likelihood information D_llr read in channel information memory plus m information D_a1 (m) and value.
7. partially-parallel architecture LDPC code interpretation method in a kind of space communication system, it is characterised in that：Including dividing LDPC code
Check matrix stage and pipeline system Partly parallel decoding stage：
The division LDPC check matrix stage etch is as follows：
(1) code check defined in CCSDS standards is R=1/2 quasi-cyclic LDPC code, the code word size of the quasi-cyclic LDPC code
N is that 8192, information bit length K is 4096, and the check matrix H of this yard is expressed as
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I in matrix HLWith 0LRespectively 2048 × 2048 dimension unit matrixs and 0 matrix, Πk(k=1,2 ..., 8) for 2048 ×
2048 dimension displacement battle arrays, displacement battle array ΠkT rows (t=0,1,2 ..., 2047) nonzero element column position πk(t) it is:
In formula, L=2048, mod represents modular arithmetic,Expression is rounded downwards to 4t/L, θkWithFor row position
Put πk(t) function in；
(2) row of the check matrix H of step (1) is divided into 3 to be out of the line respectively：H1 (0-2047 rows), H2 (2048-4095
OK), H3 (4096-6143 rows)；It is respectively S1 (0-2047 row), S2 (2048-4095 that the row of check matrix H are divided into 5 super row
Row), P1 (4096-6143 row), P2 (6144-8191 row), P3 (8192-10239 row)；
(3) data storage needed for defining decoding includes：Channel information memory, main storage and decoding output caching are single
Member；Channel information memory is used to cache channel likelihood information, comprising 4 dual port RAMs, and each RAM depth is 2048；Host
Reservoir includes 15 memory RAMs, i.e. main storage RAM1, RAM2 ..., RAM15, saved for storing variable node and verification
Each non-zero submatrices in the side information transmitted between point, each memory RAM correspondence check matrix H, each memory
RAM depth is 2048, i.e. main storage RAM1, RAM2 ..., RAM15 corresponds to respectively：
The super row S1 of RAM1 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S1 of RAM2 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
The super row S2 of RAM3 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row S2 of RAM4 correspondences submatrix Πs corresponding with the H3 that is out of the line5；
The super row S2 of RAM5 correspondences submatrix Πs corresponding with the H3 that is out of the line6；
The super row P1 of RAM6 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P2 of RAM7 correspondences submatrix Is corresponding with the H2 that is out of the lineL；
The super row P2 of RAM8 correspondences submatrix Πs corresponding with the H3 that is out of the line7；
The super row P2 of RAM9 correspondences submatrix Πs corresponding with the H3 that is out of the line8；
The super row P3 of RAM10 correspondences submatrix Is corresponding with the H1 that is out of the lineL；
The super row P3 of RAM11 correspondences submatrix Πs corresponding with the H1 that is out of the line1；
The super row P3 of RAM12 correspondences submatrix Πs corresponding with the H2 that is out of the line2；
The super row P3 of RAM13 correspondences submatrix Πs corresponding with the H2 that is out of the line3；
The super row P3 of RAM14 correspondences submatrix Πs corresponding with the H2 that is out of the line4；
The super row P3 of RAM15 correspondences submatrix Is corresponding with the H3 that is out of the lineL；
Decoding output buffer unit is used to export decoding result；
The pipeline system Partly parallel decoding stage etch is as follows：
(4) channel information memory receives and stores this current frame likelihood information data of digital receiver demodulation, and should
The storage of likelihood information data order is arrived in 4 RAM of channel information memory, and a frame likelihood information data are 8192, when this
After frame is received, channel information memory generation one receives signal and is sent to iteration control unit, and channel information is deposited
Reservoir receives 8192 data of next frame by ping-pong operation simultaneously；
(5) iteration control unit sends decoding commencing signal to channel information memory；Channel information memory receives decoding
Commencing signal, by the likelihood information data order in 4 RAM the circuit-switched data D_llr of parallel output 4 give variable node handle mould
Block；
(6) 4 circuit-switched data D_llr of variable node processing module receiving channel information memory, variable node processing module includes
This 5 variable node processing units of VNU1, VNU2, VNU3, VNU4 and VNU5, by 4 circuit-switched data D_llr deliver to respectively VNU1,
VNU2, VNU3, VNU4, VNU5 is delivered to by 0 value, at the same variable node processing module from the RAM1 in main storage,
RAM2 ..., in RAM15 according to the RAM1 in memory RAM, RAM2 ..., RAM15 reading address Addr_VN order reads
Take RAM1, RAM2 ..., the side information D_a1 in RAM15, if the 1st iteration, then the side letter taken out from main storage
Cease D_a1=0, by iteration control unit define the order for reading address Addr_VN for 0,1,2 ..., 2047, distinguish in the following manner
Side information D_a1 is delivered into VNU1, VNU2, VNU3, VNU4, VNU5, variable node processing unit is that 5 tunnels are parallel：
RAM1, RAM2 data are sequentially read out according to Addr_VN and give VNU1；
RAM3~RAM5 data are sequentially read out according to Addr_VN and give VNU2；
RAM6 data are sequentially read out according to Addr_VN and give VNU3；
RAM7~RAM9 data are sequentially read out according to Addr_VN and give VNU4；
RAM10~RAM15 data are sequentially read out according to Addr_VN and give VNU5；
(7) likelihood information updated, the side information D_ after being updated are calculated according to the D_llr and D_a1 obtained in step (6)
e1；
(8) by the side information D_e2 after updating in step (7) according to write address Addr_VN write main storage RAM1,
RAM2 ..., RAM15, read address Addr_VN it is identical with write address Addr_VN numerical value, difference be allocating time difference, by
Iteration control unit generate, be sequence address 0,1,2 ..., 2047；
(9) iteration control unit produce code check node processing module reading address Addr_CN, Addr_CN include Addr_CN1,
Addr_CN2 ... Addr_CN15, Addr_CN1, Addr_CN2 ... Addr_CN15 by step (3) main storage RAM1,
RAM2 ..., the corresponding submatrixs of RAM15 calculate and obtain；
Code check node processing module includes CNU1, CNU2, CNU3, and code check node processing module is according to address Addr_CN is read, from master
Memory RAM 1, RAM2 ..., the side information D_e1 in RAM15 in the following manner in reading step (8), be designated as side information D_
A2, CNU1, CNU2, the CNU3 delivered in code check node processing module, CNU1, CNU2, CNU3 of code check node processing module are 3
Road is parallel；
RAM10, RAM11 data are read according to Addr_CN10, Addr_CN11 and give CNU1；
By RAM1, RAM3, RAM7, RAM12, RAM13, RAM14 data respectively according to Addr_CN1, Addr_CN3, Addr_
CN7, Addr_CN12, Addr_CN13, Addr_CN14 read and give CNU2；
By RAM2, RAM4, RAM5, RAM8, RAM9, RAM15 data respectively according to Addr_CN2, Addr_CN4, Addr_CN5,
Addr_CN8, Addr_CN9, Addr_CN15 read and give CNU3；
(10) likelihood information updated, the side information D_e2 after being updated are calculated according to the D_a2 obtained in step (9)；
(11) by the side information D_e2 after being updated in step (10) according to address Addr_CN1, Addr_CN2 ... Addr_CN15 points
RAM1 that Xie Ru be in main storage, RAM2 ..., after RAM15, send this time iteration to iteration control unit and complete to believe
Number, reading address Addr_CN is identical with write address Addr_CN numerical value, and difference is that allocating time is different, is given birth to by iteration control unit
Into；
(12) iteration control unit receives this time iteration completion signal of step (11), starts next iteration, that is, repeats to walk
Suddenly according to step (5)~step (12), until reaching the maximum iteration M of the frame of setting, decoding termination signal is produced
Dec_E, then, by the D_e1 ' obtained after the completion of last time iteration according to positive and negative judgement be 0 and 1, i.e. D_e1 ' just, to adjudicate
It is negative for 1, D_e1 ', adjudicates as 0, this court verdict, which passes through court verdict and exports buffer cell, exports court verdict, this frame coding
Finish, be then returned to the decoding that step (4) carries out next frame, until all frame likelihood information data that digital receiver is demodulated are translated
Code is completed.
8. partially-parallel architecture LDPC code interpretation method, its feature in a kind of space communication system according to claim 7
It is：Addr_CN described in step (9) and (11) is according to (8192,4096) LDPC that code check in CCSDS standards is R=1/2
The H-matrix of code is calculated and obtained.
9. partially-parallel architecture LDPC code interpretation method, its feature in a kind of space communication system according to claim 7
It is：D_llr and D_a1 calculate the likelihood information updated in the step (7), the step of side information D_e1 after being updated
It is as follows：
If n-th, n is 1,2,3,4,5, it is just whole that variable node processing unit reads m information D_a1, m from main storage
Number, m ' be 1,2 ... m, m ' represent m information in the individual information of m ' sequence number, the individual information D_a1 (m ') of m ' it is corresponding renewal
Information D_e1 is equal to the channel likelihood information D_llr read from channel information memory plus the individual information D_a1 of removing m '
Other m-1 information D_a1 outside (m ').
10. partially-parallel architecture LDPC code interpretation method, its feature in a kind of space communication system according to claim 7
It is：The step of D_a2 calculates the likelihood information updated, side information D_e2 after being updated in the step (10) is as follows：
(1) set p-th, p is 1,2,3, it is just whole that code check node processing unit reads k information D_a2, k from main storage
The sequence number of k, k ' represent kth in k information ' individual information that number, k ' is 1,2 ..., kth ' the corresponding renewal of individual information D_a2 (k ')
Information D_e2 symbol bit manipulation is：Remove kth ' XOR of k-1 D_a2 sign bit outside individual fresh information D_a2 (k ')；
(2) k information D_a2 amplitude is compared, tries to achieve amplitude min value and amplitude sub-minimum, by the two values by repairing
Normalization factor α being multiplied by the occasion of multiplier, by amplitude min value and kth ' amplitude of individual information compares, if identical, exports
Sub-minimum, if it is different, then exporting minimum value, α scope is 0~1；
(3) according to the sign bit of step (1) and the range value of step (2), the side information D_e2 after being updated.
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