CN104579111A - Control method of cascaded type frequency converter based on DSP and FPGA - Google Patents

Abstract

The invention discloses a control method of a cascaded type frequency converter based on a DSP and an FPGA. According to the control method, the DSP is adopted to receive an input frequency from a keyboard, a modulation degree is calculated, and the modulating wave frequency and the voltage modulation degree are sent to the FPGA through a unique SPI; the FPGA is adopted and used for generating an SPWM signal according to the input modulating wave frequency and the voltage modulation degree in order to control connection and disconnection of a power tube in a main circuit; the main circuit comprises a phase-shifting transformer and n cascaded power modules, and the n is an integer and is larger than or equal to three. Through the control method of the cascaded type frequency converter based on the DSP and the FPGA, the carrier frequency, the modulating wave frequency and the modulation degree can be flexibly adjusted, response is rapid, and the speed control performance of the frequency converter can be effectively guaranteed.

Description

Based on the control method of the unit cascaded type frequency converter of DSP and FPGA

Technical field

The present invention relates to a kind of control method of the unit cascaded type frequency converter based on DSP and FPGA.

Background technology

Along with the reinforcement of people's energy-conserving and environment-protective meaning, the application of frequency converter is more and more universal, but China's motor driven systems energy utilization rate is very low, especially in high-voltage motor field, substantially lower than external average level by 30%, the frequency control promoting high-voltage motor at home obtains the attention of country gradually.Power module cascade connection type high voltage converter is widely used in high-pressure frequency-conversion field due to its high reliability and perfect output waveform.

Existing motor variable-frequency speed-regulating, the general work adopting DSP to carry out control inverter, DSP both completed correlation computations, also need to form pulse, cannot ensure the real-time of control, control effects is not ideal, therefore, the control method designing a kind of unit cascaded type frequency converter is completely newly necessary.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of control method of the unit cascaded type frequency converter based on DSP and FPGA, carrier frequency, frequency of modulated wave, modulation degree can should be adjusted flexibly based on the control method of the unit cascaded type frequency converter of DSP and FPGA, response is rapid, the speed adjusting performance of energy effective guarantee frequency converter.

The technical solution of invention is as follows:

Based on a control method for the unit cascaded type frequency converter of DSP and FPGA, the main circuit of described unit cascaded type frequency converter comprises n power model of phase shifting transformer and cascade; N is integer, and n >=3;

Grid side voltage is through phase shifting transformer step-down, and produce phase shift in secondary side winding, each power model is powered by a secondary side winding of phase shifting transformer respectively, mutually insulated between phase shifting transformer secondary side winding, each power model all adopts the inverter structure of AC-DC-AC voltage-source type of three-phase input rectifying, single-phase output; Inversion module in each power model comprises power tube V1 ~ V4, and power tube V1 ~ V4 is corresponding is respectively linked to be the first brachium pontis with sustained diode 1 ~ D4, V1 and V2; V3 and V4 is linked to be the second brachium pontis;

Same phase power model inversion output is followed in series to form single-phase, single-phase described in three connects with Y type, the number of power module cascade connection and the output voltage of single power model determine the output voltage of frequency converter, and the electric current of single power model determines the output current of frequency converter;

Phase shifting transformer makes phase shift π/3n electrical degree between single-phase each power model;

Implement to control to frequency converter by DSP and FPGA:

Adopt DSP to be used for receiving incoming frequency from keyboard and calculating modulation degree, and frequency of modulated wave and voltage modulated degree are sent to FPGA by SPI interface;

FPGA is adopted to produce SPWM modulation signal to control the break-make of the power tube in main circuit according to the frequency of modulated wave of input and voltage modulated degree;

By input through keyboard frequency of modulated wave, communicated by SCI (serial communication interface) between keyboard with DSP, every button once, frequency of modulated wave increase once, can realize each plus-minus 1 hertz or plus-minus 10 hertz by different buttons, pre-set a kind of V/F curve, voltage modulated degree and the sexual intercourse of frequency of modulated wave retention wire, voltage modulated degree is the frequency of modulated wave according to input, according to the algorithm in DSP, automatically calculates in dsp; Adjusting frequency is incoming frequency, and modulation degree is output voltage and rated voltage ratio, according to described V/F curve, before corner frequency, voltage modulated degree is not with change of adjusting frequency, after corner frequency, incoming frequency and voltage modulated degree linear, slope is motor magnetic flux, is constant;

The expression formula of V/F curve is as follows:

$V_{\mathrm{out}}=\left\{\begin{array}{cc}{V}_{\min }& f\&le;{\mathrm{Low}}_f\\ f\&times;(V_{\max }-V_{\min })/({\mathrm{Hig}}_f-{\mathrm{Low}}_f)& {\mathrm{Low}}_f<f<{\mathrm{Hig}}_f\\ V_{\max }& {\mathrm{Hig}}_f\&le;f\end{array}\right.;$

Wherein f is incoming frequency, Low _ffor corner frequency, be set to 5hz, Hig _ffor highest frequency, be set to 50hz, V _minfor breakover voltage, be set to 22V, V _maxfor rated voltage 220V; V _outfor output voltage; Voltage modulated degree M=V _out/ V _max.

V/F curve as shown in Figure 4.Adjust frequency i.e. incoming frequency, modulation degree is output voltage and rated voltage ratio, and before corner frequency, voltage modulated degree is not with change of adjusting frequency, after corner frequency, incoming frequency and voltage modulated degree linear, slope is motor magnetic flux, is constant.In system, corner frequency is 5HZ, and turnover output voltage is 22V.

Use the SCI implement of interruption function between button and DSP adjust ripple frequency data transmit: during each key change frequency of modulated wave, can trigger a SCI and interrupt, when being set in each triggering SCI interruption in DSP, data to be sent in FPGA once by DSP.

FPGA is deposited in RAM after receiving the data of DSP transmission, sinusoidal wave according to the half period of 8192 points stored in FPGA, adjustment modulating wave waveform, when generating SPWM signal, adopt unipolarity modulation system: during positive half cycle, V1 conducting, V2 ends, sinusoidal modulation wave Ur compares with triangular carrier Uc, [native system intermediate cam carrier frequency is 1K hertz] is as Ur > Uc, V4 conducting, V3 ends, output voltage Uo=Ud, Ud is that [busbar voltage is the direct voltage after rectifying and wave-filtering to busbar voltage, the i.e. supply power voltage of inverter, the voltage at electric capacity place in other words], when Ur < Uc, V4 are by, D3 conducting afterflow, now V3 can not conducting, Uo=0, during negative half period, V1 by, V2 conducting, as Ur > Uc, V3 conducting, V4 is by, Uo=-Ud, and as Ur < Uc, V3 is by, D4 conducting afterflow, and now V4 can not conducting, Uo=0, V1 and V2 is according to positive-negative half-cycle signal controlling break-make, V3 and V4 controls break-make according to comparative result and positive-negative half-cycle.

The frequency of the serial communication clock of FPGA is 1MHz; By the system clock of DSP through low speed prescaler setting after, be converted into 37.5MHz clock, afterwards again through frequency division be 1MHz clock.

SPI interface uses 4 signals: serial shift clock signal SCLK, data output signal MOSI, data input signal MISO, Low level effective from enable signal SS;

Use the SPI interface of DSP as main equipment, send data-signal SPIDAT, No. SCLK, tranmitting data register letter and chip selection signal SS, FPGA is as the data from equipment from MOSI serial received from SPIDAT, when MOSI receives the data of full 16, data are deposited the reception buffer register BUF2 of in FPGA defined 16, then the data received in buffer register BUF2 are stored in the RAM of FPGA, complete transfer of data;

Data transfer procedure is as follows:

First DSP writes data by program to transmission buffer register SPITXBUF, and SPITXBUF is transferred to SPIDAT by needing the partial data sent, and when data write shift register SPIDAT, will start MOSI pin and start to send data; It is all left-Aligned that data are put at SPITXBUF register and SPIDAT register memory, namely store from a high position, SPIDAT is through each clock pulse, complete transmission or the reception of a data, suppose when the rising edge of clock pulse, the highest order of data sends by SPIDAT, then remaining all data is moved to left 1; Next bit data are sent, until all data in SCITXBUF are all sent completely when treating next rising edge;

N=5, DSP select the TMS320F2812 chip of TI company, and FPGA selects the EP2C8Q208C8 chip of the CyclongII series of altera corp.

Beneficial effect:

The invention discloses a kind of control method of the unit cascaded type frequency converter based on DSP and FPGA, core of the present invention is, for the digital cell level connection type high-voltage frequency converter of 3 phase 3n roads (n <=16) the dislocation phase shift difficult point that DSP (digital signal processor) communicates with FPGA (field programmable gate array) in Speed Process of DC Motor, to propose a kind of serial communication method of application SPI (Serial Peripheral Interface (SPI)) agreement.Experimental result shows that the method that the present invention proposes not only can produce 3n (n <=16) road automatically, when modulating time precision is 1us, 48 tunnel dislocation phase shift SPWM (sinusoidal pulse width modulation) signals can be produced at most, carrier frequency, dislocation time can also be set flexibly, namely the time that wherein misplaces change the phase shifting angle of carrier wave, produce the modulating wave on 3n road, carrier wave is phase shift π/n angle, frequency of modulated wave, modulation degree successively, effectively achieve the frequency control of three phase units cascaded high-voltage, speed adjusting performance index produces a desired effect.

DSP of the present invention selects the TMS320F2812 chip of TI company, FPGA selects the EP2C8Q208C8 chip of the Cyclong II series of altera corp, and then build communications platform, take DSP as primary control, take FPGA as major calculations device, in test, native system three-phase has shared 3n (n=3 or 5) individual inverted power module and has built inversion platform, and total system realizes exporting adjustable to three-phase phase voltage.

Compared with prior art the present invention mainly contains following advantage: 1, adopt DSP as main control chip, adopts multiple Single-chip Controlling more to have the advantage controlled with in computing, be more conducive to later application comparatively.When 2, driving IGBT, used ready-made module comparatively, use special driving chip herein, more professional, also cost-saving.3, in generation drive singal process, needed to participate in computing by single-chip microcomputer comparatively, and in this system, do not need the participation of dsp controller, only just need can be produced by FPGA, save the resource of controller.And the drive singal produced is more accurate.

The present invention adopt original creation based on the communication between SPI Interface realization FPGA and DSP, because FPGA is essentially hardware module, thus response speed is exceedingly fast, real-time is high, and compact conformation is seen, programming is convenient, easy to implement, emulation and actual measurement all show that system and method for the present invention is effective.

Accompanying drawing explanation

Fig. 1 is voltage superposition schematic diagram;

Fig. 2 is the topological structure of main circuit;

Fig. 3 is single power module architectures figure;

Fig. 4 is V/F curve synoptic diagram;

Fig. 5 is FPGA receiving interface schematic diagram;

Fig. 6 is DSP internal configurations flow process;

Fig. 7 is RTL (Real-time Logic emulation) view;

Fig. 8 is that logic analyzer receives datagram;

Fig. 9 is single power unit module four switch modulation waveforms;

Figure 10 is single power cell inversion output waveform;

Figure 11 is single-phase power cells inversion output waveform;

Figure 12 is the unit cascaded inversion waveform of three-phase three; [namely inverter exports three-phase voltage waveform]

Oscillogram when Figure 13 is modulating wave 50HZ modulation degree 0.9;

Oscillogram when Figure 14 is modulating wave 25HZ modulation degree 0.5; [in Figure 13 and 14, first three curve is abc phase voltage waveform, and standby when the 4th article of curve is test, without any physical meaning, indicates hereby].

Embodiment

Below with reference to the drawings and specific embodiments, the present invention is described in further details:

Embodiment 1:

As Fig. 1-14, power module cascade connection type high voltage converter is connected at the output of multiple independently low pressure and low power module, realize high voltage to export, 6KV voltage is exported for 5 power module cascade connections, principle as shown in Figure 1, the topological structure of main circuit as shown in Figure 2, grid side high pressure is through phase shifting transformer step-down, and produce phase shift in secondary side winding, each power model is powered by a secondary side winding of phase shifting transformer respectively, mutually insulated between phase shifting transformer secondary side winding, each power model all adopts three-phase input rectifying, the inverter structure of the AC-DC-AC voltage-source type of single-phase output, inversion module in each power model comprises power tube V1 ~ V4, power tube V1 ~ V4 is corresponding to sustained diode 1 ~ D4 respectively, V1 and V2 is linked to be the first brachium pontis, V3 and V4 is linked to be the second brachium pontis.As shown in Figure 3, same phase power model inversion output is followed in series to form single-phase, single-phase described in three connects with Y type, the number of power module cascade connection and the output voltage of single power model determine the output voltage of frequency converter, and the electric current of single power model determines the output current of frequency converter.

This system middle rank connection type high-voltage frequency converter is primarily of the main control circuit composition of phase shifting transformer, power model, DSP and FPGA composition.In governor circuit, DSP is used for receiving incoming frequency from keyboard and calculating modulation degree, and frequency of modulated wave and voltage modulated degree are sent to FPGA by SPI interface; FPGA is used for producing SPWM modulation signal to control the break-make of the power tube in main circuit according to the frequency of modulated wave inputted and voltage modulated degree; Main circuit comprises n power model of phase shifting transformer and cascade; N is integer, and n >=3; Because cascade connection type frequency converter is not adopt the mode of traditional devices in series to realize High voltage output, but adopt the mode of power module cascade connection, so there is not the unbalanced problem of voltage because devices in series causes, there is not the unbalanced problem of DC side derided capacitors voltage that similar diode clamping circuit or electric capacity clamp circuit cause yet.

In order to reduce the harmonic content of input current, phase shifting transformer not only needs isolation, the effect of transformation, also need to adopt phase shift design, to reach the object reducing input harmonic current, when having n power model to connect for individual event, phase shifting transformer makes phase shift π/3n electrical degree between single-phase each power model, power to respectively n power model, go into the rectification circuit of 6n pulse wave, only 6nk ± 1 subharmonic is contained after the electric current of rectification circuit converts primary side by transformer, under the prerequisite not adding filter, the requirement of electrical network to current harmonics distortion can be met.

Triangular carrier phase shift SPWM method is a kind of method being suitable for cascaded high-voltage frequency converter modulation.The SPWM pulse signal of each power model is compared by sinusoidal modulation wave and triangular carrier and is produced, and each power model of every phase adopts same sinusoidal modulation wave, but there is certain phase shifting angle between the triangular carrier of same phase adjacent block.This just makes the amplitude of each power model SPWM modulating pulse first-harmonic all identical with phase place, certain angle but modulating pulse is staggered.Therefore the equivalent switching frequency of the final superposition output voltage of each power model comparatively traditional approach greatly improve.Therefore, under the prerequisite not improving switching frequency, the harmonic wave exported can be reduced.

FPGA and DSP communications platform design basis ground motion

FPGA and DSP communication scheme thought

In the present system, the relevant informations such as the frequency of input through keyboard are received by DSP, voltage modulated degree is calculated according to the rule of VF variable voltage variable frequency, and incoming frequency and voltage modulated degree are converted into hexadecimal information, be sent to FPGA, it can thus be appreciated that the data communication between FPGA and DSP is system research emphasis.DSP inside is embedded with 1 SPI interface, by by the system clock of DSP through low speed prescaler setting after, be converted into 37.5M clock, afterwards again through frequency division be 1M clock, clock is as serial communication clock thus, FPGA writes a SPI module, mainly comprises clock module, receive buffer module, so just can realize the high-speed serial data communication between DSP and FPGA.

Input through keyboard and SPWM signal export

In system, by input through keyboard frequency of modulated wave, communicated by SCI (serial communication interface) between keyboard with DSP, every button once, frequency of modulated wave increase once, each plus-minus 1 hertz or plus-minus 10 hertz can be realized by different buttons, due to simulate be V/F (variable voltage variable frequency) control, so keep magnetic flux constant in control procedure, pre-set a kind of V/F curve, as shown in Figure 4, wherein, incoming frequency is frequency of modulated wave, and output voltage and rated voltage ratio are voltage modulated degree.Due to when low speed, Stator resistance voltage dropping can not be ignored, and magnetic flux can be caused to reduce, torque is reduced, admittedly will compensated torque be carried out, namely when frequency is lower than a value, voltage modulated degree does not reduce with frequency, increases the value of voltage modulated degree, magnetic flux is remained unchanged, time higher than compensated torque frequency, voltage modulated degree and the sexual intercourse of frequency of modulated wave retention wire, voltage modulated degree is the frequency of modulated wave according to input, according to the algorithm in DSP, automatically calculate in dsp, algorithm is shown in formula 1.

$V_{\mathrm{out}}=\left\{\begin{array}{cc}{V}_{\min }& f\&le;{\mathrm{Low}}_f\\ f\&times;(V_{\max }-V_{\min })/({\mathrm{Hig}}_f-{\mathrm{Low}}_f)& {\mathrm{Low}}_f<f<{\mathrm{Hig}}_f\\ V_{\max }& {\mathrm{Hig}}_f\&le;f\end{array}\right.---\left(1\right)$

Wherein f is incoming frequency, Low _ffor corner frequency is set to 5hz, Hig _ffor highest frequency 50hz, V _minfor breakover voltage is set to 22V, V _maxfor rated voltage 220V.V _outfor output voltage.Voltage modulated degree M=V _out/ V _max.

Finally frequency of modulated wave is sent to FPGA by SPI together with voltage modulated degree, find in actual debug process, due to SPI transmission is hexadecimal values, so convert frequency of modulated wave and voltage modulated degree to hexadecimal by the decimal system in dsp again, when sending these two data, find that DSP is ceaselessly being sent to FPGA, cause the SPWM waveform instability produced in FPGA, have impact on the stability of the final cascade level signal generated, after thinking, if find each only transmission one secondary data, this situation would not be there is, SCI implement of interruption function between final utilization button and DSP frequency of modulated wave data stabilization is transmitted, during each key change frequency of modulated wave, a SCI can be triggered interrupt, when being set in each triggering SCI interruption in DSP, data to be sent in FPGA once by DSP.Finally solve the problem generating SPWM jitter.

FPGA is deposited in RAM after receiving the data of DSP transmission, sinusoidal wave according to the half period of 8192 points stored in FPGA, adjustment Sine Modulated waveform.When generating SPWM signal, adopt unipolarity modulation system, as shown in Figure 3: during positive half cycle, V1 conducting, V2 ends, and sinusoidal modulation wave Ur compares with triangular carrier Uc, and wherein native system intermediate cam carrier frequency selects 1KHZ.As Ur > Uc, V4 conducting, V3 ends, Uo=Ud (Ud is busbar voltage); When Ur < Uc, V4 are by, D3 conducting afterflow (V3 can not conducting), Uo=0; During negative half period, V1 by, V2 conducting, as Ur > Uc, V3 conducting, V4 by, Uo=-Ud, as Ur < Uc, V3 by, D4 conducting afterflow (V4 can not conducting), Uo=0.V1 and V2 is according to positive-negative half-cycle signal controlling break-make, V3 and V4 controls break-make according to comparative result and positive-negative half-cycle.

The hardware design

SPI the earliest Shi You motorola inc defines in its MC68HC** series processors, for providing a low cost, wieldy high-speed synchronous serial communication interface between MCU or DSP and peripheral chip.SPI, with master-slave mode work, generally has 1 main equipment with one or more from equipment.All transmission clock that all reference 1 is common, this synchronizing clock signals is produced by main equipment (DSP), uses clock to carry out synchronization to the reception of serial bit stream from equipment (FPGA).SPI interface generally uses 4 signals: serial shift clock signal (SCLK), data output signal (MOSI), data input signal (MISO), Low level effective from enable signal line (SS).

Use the SPI interface of DSP as main equipment in system, send data-signal SPIDAT, No. SCLK, tranmitting data register letter and chip selection signal SS, FPGA is as the data from equipment from MOSI serial received from SPIDAT pin, when FPGA receives the data of full 16 by MOSI, data are deposited the buffer register of in FPGA defined 16.FPGA receiving interface as shown in Figure 2, first DSP sends buffer register SPITXBUF by program to DSP and writes data, SPITXBUF is transferred to SPIDAT by needing the partial data sent, and when data write shift register SPIDAT, will start MOSI pin and start to send data.It is all left-Aligned that data are put at SPITXBUF register and SPIDAT register memory, namely store from a high position, SPIDAT is through each clock pulse, complete transmission or the reception of a data, suppose that the highest order of data sends by SPIDAT when the rising edge of clock pulse, then remaining all data are moved to left 1, next bit data are sent, until all data in SPITXBUF when treating next rising edge.

Software section designs

The setting of DSP serial ports under SPI protocol

In fact the setting of SPI is exactly its control register of initialization.Comprise configuration control register SPICCR, job control register SPICTL, baud rate register SPIBRR, and SPI clock is enable and GPIO mouth.Initial work is as follows:

(1) clock configuration and mode of operation are arranged: under SPI protocol, transfer of data uses the clock of the 1M provided by DSP, first the 30M crystal oscillator of DSP becomes 150M after frequency multiplication, then this clock is arranged through the predetermined scalar register file of high speed and the predetermined scalar register file of low speed, 75M and 37.5M clock can be produced, be 1M clock by 37.5M clock division afterwards, clock configuration refers to SPI in what moment of clock pulse goes to send or receive data.The CLOCK_POLARITY position of SPICCR register and the CLOCK_PHASE position of register SPICTL determine the clock characteristic of SPI, and when native system uses CLOCK_POLARITY=0, SPICLK not to have data to send, SPICLK is in low level.

(2) send data to arrange: the data length that SPI single sends is 1 to 16, in system, low four of configuration control register SPICCR are arranged, being configured to send word length is 16, arranges baud rate register SPIBRR low six, makes baud rate be 1M hertz.

(3) receive interruption is arranged: SPI does not use interruption, owing between input through keyboard and DSP being SCI communication, system uses SCI receive interruption herein, data format is 8 bit data patterns, baud rate is set to 38400bps, when incoming frequency is set by keyboard, a SCI receive interruption of DSP can be triggered, the data received are processed.

DSP internal configurations flow process is as shown in Figure 6: the initialization first carrying out dsp board, comprises CPU mode of operation, the setting of system clock etc., then to SPI, SCI, GPIO etc. are arranged, and comprise baud rate, working method, I/O port transmission data mode etc., then enable DSP interruption at different levels, then just arranges input data by keyboard, after process, be sent to FPGA.DSP is by the SCI interface between keyboard, receive the frequency of modulated wave of input through keyboard, keyboard can arrange frequency of modulated wave and carrier frequency in DSP in theory, native system is only provided with frequency of modulated wave, carrier frequency is arranged by FPGA, do not need to be sent to FPGA by DSP, voltage modulated degree draws according to frequency of modulated wave and V/F curve calculation by DSP, because frequency of modulated wave in DSP and voltage modulated degree are the decimal system, it is hexadecimal that SPI sends data, so need to carry out a system conversion at DSP, be finally sent to FPGA by DSP.

The programming realization of FPGA

There is no SPI interface in FPGA, so the reception data time sequence by simulating SPI, receiving data in low level, receiving the data that DSP sends.The frequency of the serial communication clock of FPGA is 1MHz, use DSP system clock through low speed prescaler setting after, be converted into 37.5MHz clock, afterwards again through frequency division be the clock of 1MHz.Because SPI is serial line interface, in reception data procedures, carry out necessary serioparallel exchange, and be stored in the register defined, send into RAM, sinusoidal wave according to the half period stored in FPGA, adjustment modulating wave waveform, adopts unipolarity modulation system, generates SPWM waveform, by online logic analyzer, can find to have received corresponding data in register.FPGA receiving unit program example is as follows:

In FPGA, RTL view as shown in Figure 7.Logic analyzer receives data as shown in Figure 8.

Experimental result and analysis

For the validity of checking institute of the present invention extracting method; build a set of unit cascaded type high-voltage inverter device; independently DC power supply is directly used to replace phase shifting transformer and friendship-straight rectification circuit; every by 3 power module cascade connections, three-phase shares 9 power models, shares 9 independent current sources and powers; each power model is by light-coupled isolation; control circuit and bus circuit are separated, leaves phase current protection interface, can protection system emergency power off under abnormal condition.

Use F2812 the data of input through keyboard to be calculated in native system, process, be sent to the RAM of FPGA by SPI, download by download program in FPGA, by Keyboard Control frequency of modulated wave and modulation degree by JTAG.Single power model four switch modulation waveforms as shown in Figure 9.Single power cell inversion output waveform as shown in Figure 10.Single-phase three unit cascaded inversion waveforms as shown in figure 11.The unit cascaded inversion waveform of three-phase three as shown in figure 12.Three-phase phase voltage arranges frequency of modulated wave and modulation by input through keyboard, and Figure 13, Figure 14 are respectively three-phase phase voltage waveform when modulating wave 50HZ modulation degree 0.9 and modulating wave 25HZ modulation degree 0.5.Contrast waveform finds, after arranging change incoming frequency by keyboard, modulation degree, substantially with the V/F curvilinear motion pre-set, reaching when keeping magnetic flux constant, allowing motor run, producing a desired effect.

Conclusion

The present invention is directed to unit cascaded type high-voltage frequency conversion and speed-adjusting DSP and FPGA communication scheme, build the dislocation phase shift SPWM signal generator communicated based on DSP and FPGA, propose and use the mode of SPI communication to carry out data flow exchange, by input through keyboard frequency of modulated wave, according to DSP internal algorithm, calculate voltage modulated degree and be sent to the computing that FPGA participates in dislocation phase shift SPWM signal generator.In the circuit debugging process of reality, by oscilloscope observation data flow transmission and three-phase phase voltage waveform known, system synthesis debugging produces a desired effect, for providing scheme reference based on the communication of DSP+FPGA and cascaded high-voltage frequency converter speed governing.

Claims (5)

1. based on a control method for the unit cascaded type frequency converter of DSP and FPGA, it is characterized in that, the main circuit of described unit cascaded type frequency converter comprises n power model of phase shifting transformer and cascade; N is integer, and n >=3;

Grid side voltage is through phase shifting transformer step-down, and produce phase shift in secondary side winding, each power model is powered by a secondary side winding of phase shifting transformer respectively, mutually insulated between phase shifting transformer secondary side winding, each power model all adopts the inverter structure of AC-DC-AC voltage-source type of three-phase input rectifying, single-phase output; Inversion module in each power model comprises power tube V1 ~ V4, and power tube V1 ~ V4 is corresponding is respectively linked to be the first brachium pontis with sustained diode 1 ~ D4, V1 and V2; V3 and V4 is linked to be the second brachium pontis;

Same phase power model inversion output is followed in series to form single-phase, single-phase described in three connects with Y type, the number of power module cascade connection and the output voltage of single power model determine the output voltage of frequency converter, and the electric current of single power model determines the output current of frequency converter;

Phase shifting transformer makes phase shift π/3n electrical degree between single-phase each power model;

Implement to control to frequency converter by DSP and FPGA:

Adopt DSP to be used for receiving incoming frequency from keyboard and calculating modulation degree, and frequency of modulated wave and voltage modulated degree are sent to FPGA by SPI interface;

FPGA is adopted to produce SPWM modulation signal to control the break-make of the power tube in main circuit according to the frequency of modulated wave of input and voltage modulated degree;

By input through keyboard frequency of modulated wave, communicated by SCI between keyboard with DSP, every button once, frequency of modulated wave increase once, can realize each plus-minus 1 hertz or plus-minus 10 hertz by different buttons, pre-set a kind of V/F curve, voltage modulated degree and the sexual intercourse of frequency of modulated wave retention wire, voltage modulated degree is the frequency of modulated wave according to input, according to the algorithm in DSP, automatically calculates in dsp; Adjusting frequency is incoming frequency, and modulation degree is output voltage and rated voltage ratio, according to described V/F curve, before corner frequency, voltage modulated degree is not with change of adjusting frequency, after corner frequency, incoming frequency and voltage modulated degree linear, slope is motor magnetic flux, is constant;

The expression formula of V/F curve is as follows:

$V_{\mathrm{out}}=\left\{\begin{array}{cc}{V}_{\min }& f\&le;{\mathrm{Low}}_f\\ f\&times;(V_{\max }-V_{\min })/({\mathrm{Hig}}_f-{\mathrm{Low}}_f)& {\mathrm{Low}}_f<f<{\mathrm{Hig}}_f\\ V_{\max }& {\mathrm{Hig}}_f\&le;f\end{array}\right.;$

Wherein f is incoming frequency, Low _ffor corner frequency, be set to 5hz, Hig _ffor highest frequency, be set to 50hz, V _minfor breakover voltage, be set to 22V, V _maxfor rated voltage 220V; V _outfor output voltage; Voltage modulated degree M=V _out/ V _max.

2. control method according to claim 1, it is characterized in that, use the SCI implement of interruption function between button and DSP to adjust ripple frequency data to transmit: during each key change frequency of modulated wave, a SCI can be triggered interrupt, be set in each SCI of triggering in DSP when interrupting, data to be sent in FPGA once by DSP.

3. control method according to claim 2, is characterized in that, FPGA is deposited in RAM after receiving the data of DSP transmission, sinusoidal wave according to the half period of 8192 points stored in FPGA, adjustment modulating wave waveform, when generating SPWM signal, adopt unipolarity modulation system: during positive half cycle, V1 conducting, V2 ends, sinusoidal modulation wave Ur compares with triangular carrier Uc, as Ur > Uc, V4 conducting, V3 ends, output voltage Uo=Ud, Ud are busbar voltage; When Ur < Uc, V4 are by, D3 conducting afterflow, now V3 can not conducting, Uo=0; During negative half period, V1 by, V2 conducting, as Ur > Uc, V3 conducting, V4 is by, Uo=-Ud, and as Ur < Uc, V3 is by, D4 conducting afterflow, and now V4 can not conducting, Uo=0; V1 and V2 is according to positive-negative half-cycle signal controlling break-make, V3 and V4 controls break-make according to comparative result and positive-negative half-cycle.

4. control method according to claim 3, is characterized in that, the frequency of the serial communication clock of FPGA is 1MHz; By the system clock of DSP through low speed prescaler setting after, be converted into 37.5MHz clock, afterwards again through frequency division be 1MHz clock.

5. control method according to claim 4, is characterized in that, SPI interface uses 4 signals: serial shift clock signal SCLK, data output signal MOSI, data input signal MISO, Low level effective from enable signal SS;

Use the SPI interface of DSP as main equipment, send data-signal SPIDAT, No. SCLK, tranmitting data register letter and chip selection signal SS, FPGA is as the data from equipment from MOSI serial received from SPIDAT, when MOSI receives the data of full 16, data are deposited the reception buffer register BUF2 of in FPGA defined 16, then the data received in buffer register BUF2 are stored in the RAM of FPGA, complete transfer of data;

Data transfer procedure is as follows:

First DSP writes data by program to transmission buffer register SPITXBUF, and SPITXBUF is transferred to SPIDAT by needing the partial data sent, and when data write shift register SPIDAT, will start MOSI pin and start to send data; It is all left-Aligned that data are put at SPITXBUF register and SPIDAT register memory, namely store from a high position, SPIDAT is through each clock pulse, complete transmission or the reception of a data, suppose when the rising edge of clock pulse, the highest order of data sends by SPIDAT, then remaining all data is moved to left 1; Next bit data are sent, until all data in SCITXBUF are all sent completely when treating next rising edge;

N=5, DSP select the TMS320F2812 chip of TI company, and FPGA selects the EP2C8Q208C8 chip of the Cyclong II series of altera corp.