CN101409518B - Method for implementing bi-level specific resonance-eliminating pulse-width modulation base on IGCT - Google Patents

Abstract

The invention relates to a method used for realizing two-level SHEPWM (specific harmonic eliminating pulse width modulation) on the basis of IGCT; corresponding switch pulse sequence is generated by modulation ratio m arranged from big to small; the forming format is memorized in a FLASH memory; a digital signal processor reads out the switch angle of 1/4 period corresponding to A phase in the FLASH memory according to the corresponding modulation ratio and the frequency parameter, symmetrically extends the angle to 360 DEG and constructs the switch angles for B phase and C phase; a timer is started after conversion calculation; in a timing breaking sub-program, the IGCT switch action time interval between three phases complies with the requirement after phase pulse width disposal. According to the switch characteristic of the IGCT, the design characteristic and the like of the output LC filter circuit, the method adopts specific harmonic elimination pulse width modulation to realize that the high-voltage frequency converter to have excellent output waveform in the whole output frequency section, and only needs to memory the switch angle data of 1/4 period of A phase at the same time, thus having small memory quantity.

Description

Two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT

Technical field

The invention belongs to the power electronics applied technical field, relate in particular to a kind of two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT.

Background technology

The high-pressure frequency-conversion technology is as the power electronics application technology, the high-tension electricity of fixed frequency and amplitude is converted to the voltage signal that can change frequency and amplitude arbitrarily, the electromagnetic torque that makes electric energy produce carries out flexibility with the load high-voltage motor and cooperates, obtain drive characteristic preferably, and at utmost improve the utilance of electric energy.External major company such as GE, ABB, ROBINCON, SIMENS and more domestic companies all have the high voltage converter product, present selective harmonic elimination pulse duration modulation method is mostly based on IGBT, but it needs very big switching angle degrees of data memory space, generally need to store three corresponding switching angle degrees of data, data volume is big, handles and uses complexity.

Summary of the invention

For solving the deficiencies in the prior art, the objective of the invention is two level converters of connecting, a kind of selective harmonic elimination pulse-width modulation implementation method based on digital signal processor (DSP) and programmable logic controller (PLC) (FPGA) is provided at the IGCT that is applied in the high voltage occasion.

For achieving the above object, the present invention is achieved by the following technical solutions:

A kind of two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT is characterized in that it comprises following steps:

(1), according to two level selective harmonic elimination pulse width modulation algorithm and the requirement of IGCT switching frequency, and according to modulation ratio m, the corresponding switching pulse sequence of ascending generation forms form and deposits in the inner FLASH memory of digital signal processor (DSP);

1., according to the requirement of IGCT switching loss characteristic, frequency control frequency range, harmonic wave of output voltage composition require, LC output filter natural frequency, constitute half period umber of pulse M/ Frequency Distribution form;

2., inverter is made of IGCT, A, B, C three-phase brachium pontis are divided into upper and lower half-bridge arm respectively, on each half-bridge arm IGCT are housed respectively; The pulse sequence lagged behind for 1/3 cycle successively between three-phase, IGCT series operation on each half-bridge arm, the control signal unanimity, the complementation of upper and lower half-bridge arm signal condition, each half-bridge arm produces one tunnel pulse, after the expansion and Dead Time processing of totally 6 tunnel pulses through programmable logic controller (PLC) FPGA, control the state of whole inverter;

3., generate the switch angle of above-mentioned pulse according to the purpose of selective harmonic elimination:

Application Fourier analysis method draws impulse function and is:

$s\left(t\right)=\underset{k}{\overset{\∞}{\mathrm{\Σ}}}{W}_k\sin \left(k{\mathrm{\ω}}_{1}t\right)(k=\mathrm{1,3,5},...)$

$W_k=\frac{4}{\mathrm{k\π}}[1+2\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{(-1)}^j\cos \left(k{\mathrm{\α}}_j\right)](k=\mathrm{1,3,5},...)$

Wherein: S (t) switch function, W _kBe the each harmonic amplitude, k is a harmonic number, ω ₁Be the first-harmonic angular frequency, t is that j is the angle sequence number, α constantly _jBe the switch angle, M is the half period umber of pulse.

Configuration switch angle (α ₁, α ₂, α ₃..., α _M) initial value, modulation ratio m is evenly divided into Q value, according to half period umber of pulse M/ Frequency Distribution form, under different modulation ratio m values, find the solution following equation group with Newton iteration method:

$\left\{\begin{array}{c}{W}_1=m\\ W_n=0,n=\mathrm{5,7},...,3M-1\end{array}\right.$

Wherein: m is a modulation ratio, and n is eliminated harmonic number.

Obtain the switch angle under the different modulating ratio; The theoretical value of calculating is handled, is made | α _i-α _j|≤ε, wherein: α _iBe the switch angle, ε is a minimum pulse width; Round again after the switch angle that calculates be multiply by 180,, and deposit in the inner FLASH memory of digital signal processor (DSP) according to m value sequential configuration Q group switching angle degrees of data from small to large;

4., the comparand register by digital signal processor (DSP) produces the PWM output signal, for the fixed base wave frequency, use fixedly timing cycle, calculate the angle step of timing cycle correspondence under certain m value, make and have only a compute switch angle in the timing cycle or do not have the compute switch angle, round again after the angle step that calculates be multiply by 180, deposit the end position of the corresponding switching angle degrees of data of each m value in; Simultaneously, in 90 degree scopes, cut apart round after angle step be 3 multiple;

(2) when frequency converter normally moves, digital signal processor (DSP) is according to the modulation ratio and the frequency parameter of correspondence, read the A switch angle of corresponding four/one-period from FLASH storage switch angle-data table, and symmetry expands to 360 degree scopes and constructs B phase and C switch angle mutually, digital signal processor (DSP) is read corresponding angle step simultaneously, and conversion Calculation is the cycle parameter of timer, starts timer; In timer timing interruption subroutine, with A, B, the C threephase switch angle of reading in, through sending needed pulse after the alternate pulsewidth processing, made for the three alternate IGCT switch motion time intervals satisfy the main inverter circuit designing requirement, guarantee the operation of frequency converter long-term safety.

Aforesaid two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT, it is characterized in that described step (1) 3. in, with Newton iteration method solving equation group, switch angle (α ₁, α ₂, α ₃..., α _M) the following initial value setting of employing:

α ₁＝0

；

α ₂＝120/(M+1)

I=3,5,7 ... during M-2,

α _i＝60(i+1)/(M+1)-0.1×30/(M+1)

；

α _i+1＝60(i+1)/(M+1)+0.1×30/(M+1)

α _M-1＝60

α _M＝60(M+3)/(M+1)

Aforesaid two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT, it is characterized in that described step (1) 3. in, be the interval with modulation ratio m with 0.01, be evenly divided into Q value.

Aforesaid two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT, it is characterized in that the timer timing interruption subroutine in the described step (2), contain following steps successively: read next switch angle, calculate the bound of the switch angle of next timing cycle simultaneously; The switch angle that adjustment A, B, C three-phase are read makes it angular range at 0～360 degree; Judge that switch angle that A reads mutually whether within next timing cycle scope, if not in this scope, then removes comparand register (CMPR); If in this scope, judge that then switch angle that B reads mutually whether within next timing cycle scope, if in this scope, then carries out the alternate pulsewidth handling process of AB; The alternate pulsewidth handling process with AB of alternate pulsewidth handling process between AC, the BC phase is same.

Aforesaid two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT, it is characterized in that in the alternate pulsewidth handling process of described AB, if the alternate pulsewidth of AB is less than 40 μ s, B phase switch angle is greater than two/one-period simultaneously, then A mutually next switch angle be adjusted on the basis of B phase switch angle and add 40us, otherwise A mutually next switch angle be adjusted on the basis of B phase and subtract 40us.

Aforesaid two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT is characterized in that on described each half-bridge arm three IGCT being housed.

Aforesaid two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT, it is characterized in that by finishing based on the controller of digital signal processor (DSP), described controller based on digital signal processor (DSP) contains digital signal processor (DSP), master controller is connected with digital signal processor (DSP) by dual port RAM, the delivery outlet of digital signal processor (DSP) is connected with programmable logic controller (PLC) (FPGA), programmable logic controller (PLC) (FPGA) is extended to 18 road signals and is connected with photoelectric switching circuit, the output light signal, this light signal is connected by the optical signal interface of optical fiber with 18 IGCT of inverter.

The invention has the beneficial effects as follows: the present invention is directed to the IGCT that is applied to high-voltage motor control two level converters of connecting, considered that main circuit absorbs the requirement of the characteristics of circuit, the constraint of IGCT switching frequency, LC output filter, switching characteristic and main circuit according to IGCT absorb circuit and the design feature of exporting the LC filter circuit, adopted the selective harmonic elimination pulse-width modulation to realize that this kind high voltage converter is in the good output waveform of whole output frequency section, guarantee the trouble free service of IGCT simultaneously, and only need store four/one-period switching angle degrees of data of A phase.Experimental results show that it has reached the requirement of expection.

Description of drawings

Fig. 1 is that selective harmonic elimination width-modulation pulse of the present invention produces circuit theory diagrams;

Fig. 2 is of the present invention based on IGCT series connection two-level inversion device main circuit schematic diagram;

Fig. 3 is the switch function schematic diagram of the switching device A1 among Fig. 2 of the present invention;

Fig. 4 is the main program flow chart that pulse of the present invention produces;

Fig. 5 is the timer Timer1 interruption subroutine flow chart that pulse of the present invention produces;

Fig. 6 is that direct voltage of the present invention is 9Kv, M=5, m=1.0, the oscillogram of output line voltage during f=50HZ;

Fig. 7 is that direct voltage of the present invention is 9Kv, M=5, m=1.0, the Fourier analysis figure of output line voltage during f=50HZ;

Fig. 8 is the program circuit that is used for obtaining in advance the corresponding timing cycle of each modulation ratio m (angle step) of the present invention.

Embodiment

Below in conjunction with accompanying drawing the present invention is done concrete introduction.

Fig. 1 is that selective harmonic elimination width-modulation pulse of the present invention produces circuit theory diagrams.The present invention is applied to two level high-voltage RHVC, mainly comprises parts such as major loop, monitor protective system, pulse-generating circuit, and pulse-generating circuit wherein is the important channel of contact major loop and monitor protective system.Pulse-generating circuit receives the control command that monitor protective system sends, and forms and send 6 tunnel required pulse trains, controls conducting and the shutoff of the integral gate commutation thyristor IGCT in the major loop, forms the output voltage electric current of required frequency and amplitude.

According to two level selective harmonic elimination pulse width modulation algorithm and the requirement of IGCT switching frequency, and according to modulation ratio m, the corresponding switching pulse sequence of ascending generation forms form and deposits in the inner FLASH memory of digital signal processor (DSP).According to the requirement of IGCT switching loss characteristic, frequency control frequency range, the requirement of harmonic wave of output voltage composition, LC output filter natural frequency, constitute half period umber of pulse M/ Frequency Distribution form.As shown in table 1.

The frequency converter that the present invention is suitable for adopts as shown in Figure 2, and two-level inversion device structure constitutes upward (or down) brachium pontis by 3 IGCT series connection, and control mode is the selective harmonic elimination pulse modulation technology.Inverter is made of 18 IGCT, and wherein first brachium pontis of A phase IGCT is A1, A2, A3, and second brachium pontis IGCT is A4, A5, A6; B first brachium pontis IGCT mutually is B1, B2, B3, and second brachium pontis IGCT is B4, B5, B6; C first brachium pontis IGCT mutually is C1, C2, C3, and second brachium pontis IGCT is C4, C5, C6.Three IGCT state synchronized of each half-bridge arm, the device state complementation of the correspondence of half-bridge arm up and down, i.e. A1 and the complementation of A4 state, A2 and the complementation of A5 state, A3 and the complementation of A6 state; B, C are mutually identical with A.Three alternate pulse trains lagged behind for 1/3 cycle successively, three IGCT series operations of each half-bridge arm, control signal unanimity.Therefore pulse-generating circuit only need generate 6 tunnel pulses corresponding to A1, A4, B1, B4, C1, C4, through expansion and dead band and alternate pulsewidth handle the just state of energy control inverter of back.

Fig. 3 is the switch function schematic diagram of IGCT A1 among Fig. 2, demonstration be the one-period waveform, half period has M pulse, left and right sides odd symmetry so independently switch angle of M is arranged, is used the Fourier analysis method, the switch function of A1 pulse is expressed as can be known:

$s_{A1}\left(t\right)=\underset{k}{\overset{\∞}{\mathrm{\Σ}}}{A}_k\sin \left(k{\mathrm{\ω}}_{1}t\right)(k=\mathrm{1,3,5},...)$

(1)

$A_k=\frac{4}{\mathrm{k\π}}[1+2\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{(-1)}^j\cos \left(k{\mathrm{\α}}_j\right)](k=\mathrm{1,3,5},...)$

A wherein _kBe the each harmonic amplitude.

Configuration switch angle (α ₁, α ₂, α ₃..., α _M) initial value, under different modulation ratio m values, find the solution following formula with Newton iteration method:

$\left\{\begin{array}{c}{A}_1=m\\ A_n=0,n=\mathrm{5,7},...,3M-1\end{array}\right.---\left(2\right)$

Can obtain the switch angle under the different modulating ratio.Because IGCT has specific minimum pulse width ε requirement, the theoretical value of calculating also will make through handling | α _i-α _j|≤ε.In order to improve the computational accuracy of digital signal processor (DSP), again the switch angle that calculates be multiply by 180, according to m value sequential configuration Q group switching angle degrees of data from small to large, and deposit in the inner FLASH memory of digital signal processor (DSP).

If three-phase three-wire system is adopted in frequency converter output, then the minimum number of times of harmonic wave is 3M+1 (M is an even number) or 3M+2 (M is an odd number) in the line voltage, just can reach the frequency of adjusting output voltage and the purpose of amplitude by changing half period umber of pulse M, frequency f and modulation ratio m.The function of pulse-generating circuit is realized by following steps:

At first determine half period umber of pulse/frequency assignment chart: (1) output harmonic wave content requirement according to following factors; (2) frequency control frequency range; (3) switching frequency of IGCT constraint.

The switching frequency of IGCT is limited, operated by rotary motion is about 500HZ, according to two level selective harmonic elimination pulse duration modulation methods, IGCT switching frequency and half period umber of pulse and output fundamental frequency are closed and are: IGCT switching frequency=2 * half period umber of pulse M * output fundamental frequency.Therefore the frequency control frequency range also influences the selection of IGCT switching frequency and half period umber of pulse.For two level converters, output line voltage generally contains abundant harmonic components, adopt the selective harmonic elimination pulse duration modulation method, the minimum subfrequency of output line voltage=(3M+1) * output fundamental frequency (M is an even number), the perhaps minimum subfrequency of output line voltage=(3M+2) * output fundamental frequency (M is an odd number).In order to suppress the influence of high order harmonic component to motor, to under the switching frequency limit of regulation, improve the minimum subfrequency of output line voltage on the one hand, to install the LC output filter additional on the other hand, high order harmonic component composition in the filtering output voltage, and the LC filter itself has a natural mode shape, therefore for fear of resonance, should with the natural frequency design of LC filter the minimum subfrequency of output voltage 1/2 near.As seen the minimum subfrequency of output voltage requires with the switching frequency restriction of IGCT certain contradiction is arranged.Reference frequency output zoning section can be adopted different half period umber of pulse M in different sections.When output frequency was 50HZ, by formula IGCT switching frequency=2 * half period umber of pulse M * output fundamental frequency, the half period umber of pulse should not be higher than 5 as can be known; If setting the frequency of oscillation of LC output filter is 300HZ, so by the minimum subfrequency of the minimum subfrequency of formula output line voltage=(3M+1) * output fundamental frequency (M is an even number) or output line voltage=(3M+2) * output fundamental frequency (M is an odd number), as can be known, the half period umber of pulse should be not less than 3, when therefore output frequency is 50HZ, the half period umber of pulse can select 5,4, one of 3, when M=5, the reference frequency output that is suitable for is wider, when output frequency is 40HZ, switching frequency is 400HZ, and the minimum subfrequency of output line voltage is 680HZ.Therefore in the scope of 40HZ～50HZ, it is suitable selecting M=5.Same other frequency band is all acted on the selection that mentioned above principle is carried out M, and can further finely tune by emulation.

For specific m and M, equation group (2) comprises M independent equation and M unknown number, when adopting Newton iterative to find the solution, and switch angle (α ₁, α ₂, α ₃..., α _M) the following initial value setting of employing (unit is degree):

α ₁＝0

①

α ₂＝120/(M+1)

2. i=3,5,7 ... during M-2,

α _i＝60(i+1)/(M+1)-0.1×30/(M+1)

α _i+1＝60(i+1)/(M+1)+0.1×30/(M+1)

α _M-1＝60

③

α _M＝60(M+3)/(M+1)

Form final half period umber of pulse/frequency assignment chart according to following factor:

(1) under certain M value, under the modulation ratio m scope of determining, equation group (2) will be separated, and the switch angle intervals of obtaining will satisfy the minimum pulse width requirement under the IGCT normal running (operation) conditions.

(2) modulation ratio m and output frequency are wanted proportional relation, thereby guarantee that induction machine keeps specified stator magnetic flux, avoid the saturated adverse effect of magnetic flux.

Table 1 is half period umber of pulse/frequency assignment chart, first line display wherein: when the half period umber of pulse was 5, the corresponding modulating ratio was 0.80～1.00, reference frequency output 40～50HZ, the switching frequency of IGCT is at 400～500HZ at this moment, and the minimum subfrequency of device output is 680HZ.

Modulation ratio in the table 1 from 0.01 to 1.00 serves as to have 100 m values at interval with 0.01, and the switching angle degrees of data (α of a correspondence is arranged for each m value ₁, α ₂, α ₃..., α _M), it has determined the switching sequence of switching device A1, the switching angle degrees of data of other device can obtain according to the phase relation of control strategy regulation.

Simultaneously, the angle step number of cutting apart in 90 degree scopes is 3 multiple; The angle step that calculates be multiply by 180, deposit the end position of the corresponding switching angle degrees of data of each m value in, be convenient to DSP and table look-up.

Theoretically, as long as 100 groups of storage in the switching angle degrees of data table are got off, just can generate corresponding pulse train according to the m/f parameter, wherein the m value has determined to adopt where organize the switching angle degrees of data, f has determined the pairing time width of angle.In fact in order to realize this target, the present invention adopts the mode of storage switch angle and angle step to achieve the goal, for the ease of storage, with switching angle degrees of data (α ₁, α ₂, α ₃..., α _M) multiply by 180 and round again, promptly there is the end position of switching angle degrees of data in stored angles increment after every group of switching angle degrees of data.It is corresponding with digital signal processor (DSP) timing cycle that this angle step is actually, search the flow process of this angle step and see Fig. 8, because the present invention adopts the task manager of digital signal processor (DSP) to produce pulse, utilize comparand register, for fixing fundamental frequency, digital signal processor (DSP) is designed to fixedly timing cycle, calculate the angle step of timing cycle correspondence under certain m value, in each timing cycle, only allow two kinds of situations: 1, do not have the switch angle to change; 2, have only a switch angle to change; The angle step of this timing cycle correspondence in fact also is through multiply by 180 data that round again after the processing simultaneously, and these data also must be 3 multiples.Because the present invention only stores the A1 switching angle degrees of data (α of four/one-period ₁, α ₂, α ₃..., α _M), so the data space that digital signal processor (DSP) needs is very little, but must call among the SRAM before the real time execution in program, data are expanded to the whole cycle, construct B and C complete period switching angle degrees of data mutually simultaneously, A, B, C mutually between phase angle mutual deviation 120 degree, be that 3 multiple could guarantee that B is satisfied under this angle step with C so have only angle step: do not have the variation of switch angle, perhaps have only the condition of a switch angle variation.

Pulse generation algorithm corresponding application program and pulse generation data all are stored in the FLASH memory of digital signal processor (DSP), comprise main program and interruption subroutine, and flow chart is seen Fig. 4 and Fig. 5.Program process is as follows:

In the main program, after DSP resets, at first carry out initialization, remove IE, the IF register is forbidden timer Timer1 and global interrupt, setting T1 interrupts, and some necessary parameter, receive various instructions by dual port RAM, when frequency converter is in running status, after calculating corresponding output running frequency, by V/F is that the formula of constant calculates corresponding modulation ratio m, reads in A phase switch angle then by tabling look-up, and carries out 360 ° of expansions and structure B, C phase switching angle degrees of data, and deposit data in dual port RAM, simultaneously DSP reads corresponding angle step, and conversion Calculation is the cycle parameter of timer Timer1, starts Timer1.If be in malfunction, program just is provided with stopped status.

In the Timer1 interruption subroutine, from dual port RAM, read A, B, C three corresponding next switch angles, calculate the angle bound of next timing cycle simultaneously; The switch angle that adjustment A, B, C three-phase are read makes it angular range at 0～360 degree; Judge that switch angle that A reads mutually is whether within next timing cycle scope, if not in this scope, then remove comparand register CMPR; If in this scope, judge that then switch angle that B reads mutually is whether within next timing cycle scope, if in this scope, then carry out the alternate pulsewidth handling process of AB: suppose that the alternate pulsewidth of AB is less than 40 μ s, B phase switch angle is greater than two/one-period simultaneously, so A mutually next switch angle be adjusted on the basis of B phase switch angle and add 40us, otherwise A mutually next switch angle be adjusted on the basis of B phase and subtract 40us; Alternate pulsewidth handling process between same AC, the BC is similar;

Two level selective harmonic elimination width-modulation pulses produce circuit as shown in Figure 1, comprise digital signal processor (DSP), memory, programmable logic controller (PLC) (FPGA), photoelectric switching circuit.But digital signal processor adopts the fixed-point processor TMS320LF2407A of TI company.Memory comprises static memory (SRAM) and dual port RAM (DPRAM), and static memory (SRAM) SRAM is made of a slice ISSIIS62C1024, and dual port RAM (DPRAM) is made of a slice CY7C0241AV.Programmable logic controller (PLC) (FPGA) is made of a slice EPF10K30AQC240-3.Master controller is connected with digital signal processor (DSP) by two RAM, the delivery outlet of digital signal processor (DSP) is connected with programmable logic controller (PLC) (FPGA), programmable logic controller (PLC) (FPGA) is extended to 18 road signals and is connected with photoelectric switching circuit, the output light signal, this light signal is connected by the optical signal interface of optical fiber with 18 IGCT of inverter.

Fig. 6 is that direct voltage is 9Kv, M=5, m=1.0, the oscillogram of output line voltage during f=50HZ, Fig. 7 direct voltage are 9Kv, M=5, m=1.0, the Fourier analysis figure of output line voltage during f=50HZ, the harmonic components that wherein is lower than 17 times in output line voltage is eliminated substantially, has reached predetermined purpose.

Table 1 half period pulse/frequency assignment chart

The half period umber of pulse	Modulation ratio	Reference frequency output	The switching frequency scope	Minimum subfrequency
					5	0.80-1.00	40.0-50.0	400-500	680
7	0.59-0.79	29.5-39.5	413-553	678.5
					9	0.49-0.58	24.50-29.00	441-522	710.5
13	0.29-0.48	14.50-24.00	377-624	594.5
					25	0.17-0.28	8.50-14.00	425-700	654.5
49	0.01-0.16	3.00-8.00	300-800	452

The foregoing description does not limit the present invention in any way, and all employings are equal to the technical scheme that mode obtained of replacement or equivalent transformation, all drop in protection scope of the present invention.

Claims (6)

1. based on the two level selective harmonic elimination pulse-width modulation implementation methods of IGCT, it is characterized in that it comprises following steps:

(1), according to two level selective harmonic elimination pulse width modulation algorithm and the requirement of IGCT switching frequency, and according to modulation ratio m, the corresponding switching pulse sequence of ascending generation forms binary data and deposits in the FLASH memory of digital signal processor inside;

1., according to IGCT switching loss characteristic require, the reference frequency output of frequency control, harmonic wave of output voltage composition require, LC output filter natural frequency, constitute the half period umber of pulse M/ Frequency Distribution form of being made up of half period umber of pulse, modulation ratio, reference frequency output, switching frequency scope and minimum subfrequency;

2., inverter is made of IGCT, A, B, C three-phase brachium pontis are divided into upper and lower half-bridge arm respectively, on each half-bridge arm IGCT are housed respectively; The pulse sequence lagged behind for 1/3 cycle successively between three-phase, IGCT series operation on each half-bridge arm, the control signal unanimity, the complementation of upper and lower half-bridge arm signal condition, each half-bridge arm produces one tunnel pulse, after the expansion and Dead Time processing of totally 6 tunnel pulses through programmable logic controller (PLC), control the state of whole inverter;

3., generate the switch angle of above-mentioned pulse according to the purpose of selective harmonic elimination:

Application Fourier analysis method draws impulse function and is:

$S\left(t\right)=\underset{k}{\overset{\∞}{\mathrm{\Σ}}}{W}_k\sin \left({\mathrm{k\ω}}_{1}t\right)(k=\mathrm{1,3,5},...)$

$W_k=\frac{4}{\mathrm{k\π}}[1+2\underset{j=1}{\overset{M}{\mathrm{\Σ}}}{(-1)}^j\cos \left({\mathrm{k\α}}_j\right)](k=\mathrm{1,3,5},...)$

Configuration switch angle (α ₁, α ₂, α ₃..., α _M) initial value, modulation ratio m is evenly divided into Q value, according to half period umber of pulse M/ Frequency Distribution form, under different modulation ratio m values, find the solution following equation group with Newton iteration method:

$\left\{\begin{array}{c}{W}_1=m\\ W_n=0,n=\mathrm{5,7},...,3M-1\end{array}\right.$

Obtain the switch angle under the different modulating ratio; The theoretical value of calculating is handled, is made | α _i-α _j|≤ε, wherein ε is a minimum pulse width; Round again after the switch angle that calculates be multiply by 180,, and deposit in the FLASH memory of digital signal processor inside according to m value sequential configuration Q group switching angle degrees of data from small to large;

4., the comparand register by digital signal processor produces output signal, for the fixed base wave frequency, use fixedly timing cycle, calculate the angle step of timing cycle correspondence under certain m value, make and have only a compute switch angle in the timing cycle or do not have the compute switch angle, round again after the angle step that calculates be multiply by 180, deposit the end position of the corresponding switching angle degrees of data of each m value in; Simultaneously, in 90 degree scopes, cut apart round after angle step be 3 multiple;

(2) when frequency converter normally moves, digital signal processor is according to the modulation ratio and the frequency parameter of correspondence, read the A switch angle of corresponding four/one-period from FLASH storage switch angle-data table, and symmetry expands to 360 degree scopes and constructs B phase and C switch angle mutually, digital signal processor is read corresponding angle step simultaneously, and conversion Calculation is the cycle parameter of timer, starts timer; In timer timing interruption subroutine, with A, B, the C threephase switch angle of reading in, through sending needed pulse after the alternate pulsewidth processing, made for the three alternate IGCT switch motion time intervals satisfy the main inverter circuit designing requirement, guarantee the operation of frequency converter long-term safety; Described alternate pulsewidth is handled, in handling process, if the alternate pulsewidth of AB is less than 40 μ s, B phase switch angle is greater than two/one-period simultaneously, then A mutually next switch angle be adjusted on the basis of B phase switch angle and add 40us, otherwise A mutually next switch angle be adjusted on the basis of B phase and subtract 40us;

Wherein: S (t) is an impulse function, W _kBe the each harmonic amplitude, k is a harmonic number, ω ₁Be the first-harmonic angular frequency, t is that j is the angle sequence number, α constantly _jBe the switch angle, M is the half period umber of pulse, and m is by the harmonic elimination number of times for modulation ratio n.

2. two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT according to claim 1, it is characterized in that described step (1) 3. in, with Newton iteration method solving equation group, switch angle (α ₁, α ₂, α ₃..., α _M) the following initial value setting of employing:

α ₁＝0

α ₂＝120/(M+1)；

I=3,5,7 ... during M-2,

α _i＝60(i+1)/(M+1)-0.1×30/(M+1)

α _i+1＝60(i+1)/(M+1)+0.1×30/(M+1)；

α _M-1＝60

α _M＝60(M+3)/(M+1)

3. two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT according to claim 1, it is characterized in that described step (1) 3. in, be the interval with modulation ratio m with 0.01, be evenly divided into Q value.

4. two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT according to claim 1, it is characterized in that the timer timing interruption subroutine in the described step (2), contain following steps successively: read next switch angle, calculate the bound of the switch angle of next timing cycle simultaneously; The switch angle that adjustment A, B, C three-phase are read makes it angular range at 0～360 degree; Judge that switch angle that A reads mutually is whether within next timing cycle scope, if not in this scope, then remove comparand register; If in this scope, judge that then switch angle that B reads mutually whether within next timing cycle scope, if in this scope, then carries out the alternate pulsewidth handling process of AB; The alternate pulsewidth handling process with AB of alternate pulsewidth handling process between AC, the BC phase is same.

5. two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT according to claim 1 is characterized in that on described each half-bridge arm three IGCT being housed.

6. two level selective harmonic elimination pulse-width modulation implementation methods based on IGCT according to claim 5, it is characterized in that finishing by controller based on digital signal processor, described controller based on digital signal processor contains digital signal processor, master controller is connected with digital signal processor by dual port RAM, the delivery outlet of digital signal processor is connected with programmable logic controller (PLC), programmable logic controller (PLC) is extended to 18 road signals and is connected with photoelectric switching circuit, the output light signal, this light signal is connected by the optical signal interface of optical fiber with 18 IGCT of inverter.

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