CN104576404B - A kind of method and system making semiconductor bottom plate - Google Patents
A kind of method and system making semiconductor bottom plate Download PDFInfo
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- CN104576404B CN104576404B CN201410452718.4A CN201410452718A CN104576404B CN 104576404 B CN104576404 B CN 104576404B CN 201410452718 A CN201410452718 A CN 201410452718A CN 104576404 B CN104576404 B CN 104576404B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Photovoltaic Devices (AREA)
- Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)
- Wire Bonding (AREA)
- Laminated Bodies (AREA)
Abstract
The present invention describes the method and system of production semiconductor bottom plate.A kind of setting according to the embodiment, semiconductor particle are placed in the backing material of semiconductor bottom plate, using the perforation in backing material or the perforation in removable supporting member, and the semiconductor bottom plate are constructed on the supporting member.For example, semiconductor particle is arranged in the perforation on supporting member, so that a part of semiconductor particle is prominent from supporting member.Apply suction to semiconductor particle to keep semiconductor particle in perforation, applies sealing material layer and cover the protrusion on supporting member.The supporting member then removal from semiconductor particle and sealing material layer, semiconductor particle and sealing material layer are formed together the component of semiconductor particle and sealing material layer.Described a part of semiconductor particle is then planarized.
Description
Technical field
Subject specification relates generally to production semiconductor structures, in particular to a kind of method for making semiconductor bottom plate and are
System.
Background technique
Monocrystalline silicon is used for most electronic device applications.It removes existing such as display and some imagers, amorphous
Silicon is used for glass substrate also to manipulate the pixel of display or imager.In a number of applications, display or imager quilt
Manufacture is in the top of silicon electronic device.For being applied to liquid crystal display (LCDs), amorphous silicon provides excellent performance.For
Next generation display part such as Organic Light Emitting Diode (OLED), active matrix (AM, the Active made of amorphous silicon
Matrix) driving transistor has been demonstrated that there are problems.Basically, LCDs uses voltage devices, and active matrix light-emitting
Diode (AM-OLED) needs current device.The trial of extension conventional method is related to being modified the non-of the prior art on glass
Crystal silicon.Amorphous silicon is added to entire base panel, is usually greater than two meters in side, then using large-scale excimer laser
(large excimer lasers) is recrystallized in the focusing of panel upper tracer.Laser carries out impulse modulation so as to only
Melt silicon face and non-fusible glass, since glass melting temperature is lower than silicon.This technology causes the formation of polysilicon, and
It is not to form monocrystalline silicon.
Any type of noncrystal or polycrystalline transistor, including without silicon and organic assembly, mobility (the
Mobility) much smaller than the mobility of the transistor of monocrystalline silicon.Electron mobility in amorphous silicon is about 1cm2/ Vs, with
Compared to for poly- silicon about 100cm2/ Vs, and be about 1500cm for high quality monocrystalline silicon2/V·s.Therefore in these devices
In, it is beneficial with monocrystalline silicon substitution amorphous silicon.
The curved surface that diode is placed in silicon ball body is had been demonstrated challenging.Previous in technology, use
Photoetching has been made in the trial of spherome surface definition structure, but this needs off-gauge optical device and success rate is limited.Make electricity
Contact is connected to nonplanar surface and is also required to non-standard techniques.This complexity comprising in the fabrication process prevents any
Substantial progress.
Summary of the invention
According to an embodiment, a kind of method for making semiconductor bottom plate is provided, comprising: in the perforation of supporting member
(depositing) semiconductor particle is set, so that a part of semiconductor particle is prominent from the supporting member；To semiconductor
Another part application suction of particle keeps the semiconductor particle to be located in the perforation；It is applied on supporting member top
(applying) sealing material layer (a layer of encapsulant material) is so that the semiconductor particle is described
Partially (the portion of the semi-conducting particles) is covered by sealing material layer；Remove support structure
Part is to appear the component (an assembly) of semiconductor particle and sealing material layer；And planarization (planarizing) is partly led
Described another part of body particle.
According to a related embodiment, described another part is (lies in one of) one of below: one is parallel to
The plane of sealing material layer and a plane coplanar with sealing material layer.
According to another related embodiment, planarization includes chemically mechanical polishing (CMP, chemical-mechanical
planarization)。
It include at least one below using the sealing material layer according to another related embodiment: spraying
(spraying) on the sealing material to the supporting member, casting (pouring) described sealing material to the support structure
On part, it is unfolded on (spreading) described sealing material to the supporting member, rolling (rolling) described sealing material is extremely
On the supporting member, on punching press (pressing) described sealing material to the supporting member, with the sealing material electrostatic
It coats (electrostatically coating) described supporting member and vacuum forming (vacuum forming) is described close
On closure material layer to the supporting member.
According to another related embodiment, sealing material layer includes at least one: liquid (a fluid), powder and
Thin slice.
According to another related embodiment, sealing material layer includes at least one: glass, plastics and photocuring cement
(optically curable cement)。
According to another related embodiment, this method further comprises, before removal operation, in the sealing material
A substrate material layer (a layer of substrate material) is applied on the bed of material.According to an embodiment, the component
(the assembly) further comprises the substrate material layer.According to an embodiment, the substrate material layer include at least with
It is one of lower: glass, flexible glass (flex-glass) and plastics.
According to another related embodiment, this method further comprises that planarization is moved back except the sealing material layer.
According to an embodiment, the system of production semiconductor bottom plate is provided, comprising: there is the supporting member of perforation, institute
Stating size in perforation is that can receive semiconductor particle so that a part of semiconductor particle is prominent from supporting member；One suction dress
It sets, is operably coupled to the supporting member, for applying suction to another part of semiconductor particle to maintain described half
Conductive particle is located in the perforation；One applicator, for applying the sealing material layer on the supporting member, so that half
The part of conductive particle is covered by sealing material；And a planarizer, for planarizing another portion of semiconductor particle
Point.
Embodiment there is provided a kind of methods for making semiconductor bottom plate according to another, comprising: provides one in suction
The lower substrate (a substrate) with perforation；(depositing) semiconductor particle is set in perforation so that semiconductor grain
A part of son is prominent from the substrate, which is retained in perforation by suction；Substrate is adhered to
(adhering) forms the component (an assembly) of the substrate and the semiconductor particle to semiconductor particle；And
Planarize the part of the semiconductor particle.
According to a relevant embodiment, the substrate is provided to a supporting member, the supporting member configuration is to apply
Suction is to the perforation.
According to a relevant embodiment, the part of the planarization is one of below: one is parallel to the component
The plane of the substrate and one with the plane of the substrate co-planar of the component.
According to a relevant embodiment, planarization includes chemically mechanical polishing (CMP).
According to a relevant embodiment, it includes at least one that substrate, which is adhered to the semiconductor particle: being worn
Applied adhesives at hole；The applied adhesives at semiconductor particle；Heat substrate；Cured substrate；And fusion (fusing) is partly led
In an oxide layer to substrate on body particle.
According to a relevant embodiment, this method further comprises that the component is removed from supporting member.
According to a relevant embodiment, the supporting member includes a plane institution movement, a conveyer belt (a conveyor)
Or an one of roller (a drum).
According to a relevant embodiment, the semiconductor particle includes silicon ball.
According to a relevant embodiment, the substrate includes at least one: glass, flexible glass (flex-
) and plastics glass.
According to another relevant embodiment, the method further includes planarization and moves back except the substrate.
According to another embodiment there is provided a kind of system for making semiconductor bottom plate, include: a support surface, configuration
To provide the perforation of suction a to substrate；One setting (depositing) device, partly leads for being arranged in perforation under suction
Body particle, the semiconductor particle are retained in the perforation by suction so that a part of the semiconductor particle is from the lining
It is prominent in bottom；One for adhering to the device of the substrate to the semiconductor particle, to form the substrate and the semiconductor
The component of particle；And a planarizer, for planarizing the part of the semiconductor particle.
Detailed description of the invention
For be best understood from various embodiments described herein and it is clearer show they how to put into practice, only
Attached drawing makes reference by way of example and as follows:
Fig. 1 depicts the adherency of semiconductor spheres array on substrate predefined according to first group of non-limiting embodiments
The sectional view of the ball is permanently fixed on position；
Fig. 2 depicts the photo that single-crystal silicon sphere array is arranged on non-silicon substrate according to first group of non-limiting embodiments；
Fig. 3 a depicts the Spherical Semiconductor particle being set on a gridding substrate according to first group of non-limiting embodiments
Sectional view, which, which has, is arranged in conformal coating (a conformal on the spheroidal particle top
coating)；
Fig. 3 b is depicted after semiconductor spheres particle shown in Fig. 3 a is flattened according to first group of non-limiting embodiments
Sectional view；
Fig. 4 a to 4f is depicted according to first group of non-limiting embodiments and is formed contact and contact to sphere in plane surface
The method of outer surface is for for example providing solar battery array；
Fig. 5 a depicts the complementation being formed on a planarization semiconductor particle according to first group of non-limiting embodiments
The partial cutaway view of NMOS and PMOS circuit, the planarization semiconductor particle are doped with p-type material when being formed；
Fig. 5 b depicts the single transistor device manufactured in individually planarization sphere according to first group of non-limiting embodiments
The sectional view of part；
Fig. 5 c according to first group of non-limiting embodiments, depict shown in a planarization spheroidal particle have gate brilliant
The symbol of body pipe (gated transistors) indicates the isometric side view of the circuit of (symbolic representation)
(an isometric view)；
Fig. 5 d depicts the spheroidal particle of Fig. 5 b that can be manufactured as this kind of particle according to first group of non-limiting embodiments
One of them in array；
Fig. 6 a to 6d is according to the cross-sectional view of the particle of first group of non-limiting embodiments, wherein showing perpendicular to described flat
The depth capacity on the surface of smoothization；
Fig. 7 a to 7c depicts the method for production semiconductor bottom plate according to second group of non-limiting embodiments；
Fig. 8 a to 8c depicts a kind of support structure for making semiconductor bottom plate according to second group of non-limiting embodiments
Part；
Fig. 9 depicts a kind of supporting member for making semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 10 depicts a kind of semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 11 a and 11b depicts a kind of method for making semiconductor bottom plate according to second group of non-limiting embodiments, described
Semiconductor bottom plate includes substrate material layer (a layer of substrate material)；
Figure 11 c to 11e depicts a kind of method for making semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 12 depicts a kind of flow chart of method for making semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 13 depicts a kind of system for making semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 14 a to 14d depicts a kind of method for making semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 15 is depicted a kind of for making the supporting member of semiconductor bottom plate according to second group of non-limiting embodiments；
Figure 16 is depicted a kind of for making the process of the method for semiconductor bottom plate according to second group of non-limiting embodiments
Figure；
Figure 17 depicts a kind of system for making semiconductor bottom plate according to second group of non-limiting embodiments.
Specific embodiment
Method and system described herein for production semiconductor bottom plate (being also referred to herein as " semiconductor devices ").Root
According to first group of embodiment, the semiconductor particle of multiple planarizations is located on the predefined position of a substrate to be formed and be suitable for plane electricity
The subrange of sub- device assembly, planar electronic device are assemblied in the upside of planarized surface region, inside or below.According to
Second group of embodiment, semiconductor particle are placed in the backing material of the semiconductor bottom plate, utilize wearing in backing material
Perforation in hole or the component supported as removable or removal, constructs the semiconductor bottom plate.
According to the first subset of second group of embodiment, semiconductor particle is arranged in the perforation of a supporting member so that described
A part of semiconductor particle is prominent from supporting member.Semiconductor particle application suction is kept it in the perforation,
And the protrusion of the semiconductor particle is covered using sealing material layer on supporting member.Then the supporting member
It is removed from the semiconductor particle and the sealing material layer, together forms semiconductor particle and sealing material layer at this time
Component.The part of the semiconductor particle carries out being planarized to form semiconductor bottom plate.
According to the second of second group of embodiment group of subset, the substrate under suction with perforation, and semiconductor grain are provided
Son is arranged in the perforation of substrate, so that a part of semiconductor particle is protruded from substrate, and is partly led by suction holding
Body particle is in perforation.Substrate is adhered to the component that substrate and semiconductor particle are formed on semiconductor particle, and semiconductor grain
The part of son carries out planarization process.
It should be appreciated that for the purpose of present disclosure, " at least one in X, Y and Z " and " one or more of X, Y and Z "
Expression can be construed to only X, only Y, only Z or two or more X, Y and Z any combination (such as: XYZ,
XYY、YZ、ZZ)。
As described above, being advantageous such as flat-panel monitor using monocrystalline silicon replacement polysilicon in various equipment.According to one
A little embodiments, the predeterminated position in an amorphous silicon substrate manufacture multiple plaine single crystal silicon areas, manufacture for electronic device.Example
Such as, monocrystalline silicon wafer crystal (wafers of single crystal silicon) is for giant display to be too expensive and size mistake
Small: compared with the side of existing LCD display is more than 2 meters, Silicon Wafer representative diameter is 300mm.By comparing, monocrystalline silicon
Almost spherical particle, sphere or spheroidal particle have been made as size less than or equal to 2mm, this belongs to compared with single pixel size
It is large-scale.Inventor Witter, which is equal to, submits the entitled U.S. for producing the technique of crystallization disc sphere special on April 30th, 1985
Benefit 4637855 is included herein by reference, and which depict the production of crystallization sphere.
In addition, being connected to the electrical contact of non-planar surfaces about production, the curved surface of silicon ball body is doped with n-type doping
To form n-type silicon around a p-type silicon area, p-type silicon area contains most of spherome surface for agent.It is related to photovoltaic device neck
Some embodiments in domain, wherein plane surface and following region can be adulterated with such as n-type dopant and following area can be with
P-type dopant is adulterated to form solar battery.Article (the Crystal that Satoshi OMAE et al. is delivered
Characterization of Spherical Silicon Solar Cell by X-ray Diffraction,Satoshi
OMAE,Takashi MINEMOTO,Mikio MUROZONO,Hideyuki T AKAKURA and Yoshihiro HAMAKA
W A,Japanese Journal of Applied Physics Vol.45,No.SA,2006,pp.3933-3937#
2006.The Japan Society of Applied Physics) in describe a kind of silicon ball body photovoltaic cell.
Above-mentioned first technology is overcome in at least partly embodiment of method described herein, system and device
Limitation, by easily utilize planarization particle flat surfaces on surface area and region (the surface
Area and region) production electronic device.The structured flat site of the tool wherein formed provides appropriate reliable side
Formula provides the electrical contact for being connected to device different piece.
In addition, at least some embodiments are compared with the similar circuit using LCD technology, by allowing to consume less energy
Circuit is established in source makes technology have smaller carbon footprint.
For example, some embodiments are able to produce large-scale oled panel, this oled panel is more efficient than LCD panel.
OLED pixel is issued in required color, these colors are only red, green or blue, therefore while generating other colors does not have energy unrestrained
Take, other colors subsequently generated are generated the waste (waste) of form of heat by filtering.In addition, OLED emitter can be with
It is made on the top of bottom plate electronics (the backplane electronics), therefore emitting area can not block pixel
Light emitting region in the case of reach maximization.By placing bottom plate electronics outside optical path, the design can be in speed and low-power consumption side
Face optimization, rather than since optical path needs are compromised.
It is noted that be formed in or located immediately at these planarization surface under electronic device include but is not limited to:
Transistor, diode, capacitor, nonlinear resistor, temperature sensor, electric wire connecting junction, through-hole, the through-hole can be by described in doping
Planarization sphere is laid over planarization surface such as OLED or AMOLED or photodetector and is formed.In addition, implementing
Example allows a function element, such as transistor, is formed on the flat surfaces of single sphere.
Turning now to Fig. 1, is depicted and be adhered on substrate pre- according to the non-limiting embodiments of first group of embodiment
Fixed position is permanently fixed the cross-sectional view of the semiconductor spheres volume array of the sphere.Substrate 10 can be plastics, glass, semiconductor
Material or any stabilizing material suitable for support electronic circuit.The upper surface of substrate 10, substrate 10 is arranged in adhesion layer 12
With grid 14, grid 14 has scheduled notch (gaps) between grid elements, which is arranged size rationally to accommodate half
Conductor sphere 16,16 diameter of semiconductor sphere are less than 15mm and preferably smaller than 2mm.Term " semiconductor sphere " used below,
Including sphere, orbicule and semiconductor type ball object, may be lacked since the flaw (defects) during formation sphere has
It falls into (imperfections).The energy when determining that spherical semiconductor material is set to where convenient for circuit designers of arrangement shown in Fig. 1
There are more controls, and therefore, semiconductor devices is in the setting position of the flat surfaces of sphere 16 in sphere planarization process
After make.Although shown grid has identical spacing between grill openings, there is non-homogeneous spacing in any desired mode
Grid can also be used to put sphere.It is fixed if electronic device is manufactured on flat surfaces before substrate in placement sphere
It will be extremely difficult to sphere.Therefore the fixation first of semiconductor sphere 16 is mounted on substrate 10, and then planarization is to appear ball
The high quality semiconductor material region in internal portion, the region are suitable for production silicon device (silicon electronics)；Citing comes
It says, cmos device can take shape in flatness layer by adulterating ball material in flatness layer and lower section.Spheroidal particle has carried out in detail
Description and particularly suitable for positioning and planarizing, however many other shapes of particle can also be applied, as long as particle can be convenient ground
Be positioned and secured to substrate, as long as and particle can planarize in order to provide plane or flat surface for making electronics device
Part.
Typically for most of electronic devices for being based on crystal grain (chip-based), the grained region not used reduce to
Minimum is so as to device density height.Density height makes the unused substrate area wasted due to not set activating appts smaller.
In display and imager, device area passes through nonelectronic demand classification.As a result, as display becomes much larger,
Device density becomes lower.In a certain situation, several square meters are covered with low quality silicon to make some devices, or PC is compared in covering
The hundreds of millions of devices of CPU in millions of a devices mode, be no longer ideal.According to method described herein,
System and device, the silicon of high quality are only arranged when needed, therefore a small portion of its total display area for covering giant display
Point.This technology inflection point can be due to upcoming transboundary (the impending crossover) for OLED display
And it generates.OLED is current device, and the amorphous silicon on glass can not achieve required electric current and speed.
The photovoltaic panel of manufacture large area, the name such as 30 days December nineteen eighty-three with Carson et al. are had been used for before silicon ball body
Entitled " using the photoelectrical solar array of silicon particle " (the Photovoltaic Solar of United States Patent (USP) 4614835 that justice is submitted
Arrays Using Silicon Microparticles) it is described, it is combined incorporated herein by mode.For photovoltaic applications,
Spherome surface forms workspace (the active area).Silicon ball body can be made by inexpensive powder silicon, and obtained weight
The silicon dioxide surface layer of crystallization can more effectively receive (getter) impurity.It is pure that integral material can be improved in melt back circulation
Degree.Even if electron mobility is still the manyfold of amorphous silicon in the case where polycrystalline particle.
According to some embodiments, it can be found that for electronic device, it is preferable to use the section of semiconductor particle such as sphere
Flat surface making devices, rather than curved outer surface.Even curface allows the photoetching technique using standard, thus
Allow to make transistor, electric wire connecting junction etc..Such as the silicon ball body that diameter is 20 microns, the maximum region A for element manufacturing is provided
=π x r2=about 314 square microns.Many raster widths can be made in the transistor of 1 micron of order of magnitude in this region
Make.For large area display, for each pixel only have a small amount of transistor be it is required, and pixel size not with display
Size is proportional；Fine definition (HD) is standard resolution (such as 1920 × 1080 pixels).In addition, one piece of high quality is smooth
Region, single crystal silicon can service more than one pixel, can also provide additional function, such as from survey and display performance monitoring
And correction, such as equipped with photodetector or temperature sensor.
The utilization in the particle such as smooth section of the planarization sphere of truncation is planarized, permitting deformation lithographic fabrication techniques
It uses.Further, by planarization process, the defect on the surface of sphere or class spherical surface is appeared in sphere or class spherical surface
Etching or polishing are removed with appearing interior zone.Advantageously, it is purified in self-contained process due to sphere, high quality monocrystalline silicon material
High-temperature process realization can be used in material, is not suitable for being arranged amorphous silicon on a glass substrate because glass substrate is low
In the temperature melting of standard silicon treatment temperature.When cross section appears, ball or other shapes of planarization particle is truncated can be
It is adulterated under or over its planarization surface or multiple doping is to form n-type and p-type rings of material or trap；Doping can also be subsequent
During carry out.This will allow the production of cmos device as shown in Figure 5.Although passing through ion implanting in preferred mode
Doped region, but adulterating can also be by the spin coating dopant realization on planarization surface.Outer surface can be as highly doped or gold
Categoryization can be connected with being formed by the substrate of any position connection of the top surface edge or spherical surface on spherical surface
(substrate contact), as the effective back side.Term used in this specification " connection " can be physical cord,
Or metalized contact areas such as conductive contact pads, thus pin or conducting wire or device can be in electrical contact.
According to some embodiments of first group of embodiment, known bits of the spherical silicon particle on substrate such as non-silicon substrate are installed
It sets.Silicon ball body on positioning substrate can be completed by any technology in several technologies.According to the certain of first group of embodiment
Embodiment, substrate are formed by multiple Sphere orientation positions.Metal or dielectric grid first can be permanently or temporarily arranged
On substrate or usable standard photolithography techniques.Optional grid point, pit or other modes of attachment can be used for positioning ball.
It should select to match the adhesion material with fusing point or adhesive at room temperature that subsequent electrical part is handled.As setting or laying
Another alternative of grid, substrate can make on substrate hole, Kong Zhong by using standard photolithography techniques with straight forming
For adhesive to be arranged to fix semiconductor sphere.
According to some embodiments of first group of embodiment, silicon particle, which is used to form single layer in substrate surface, to be substituted for being formed
The non-semiconductor sphere of exposure mask (a mask), the non-semiconductor sphere are described in Knappenberger et al. respectively at 2001 8
The United States Patent (USP) 6464890 and 6679998 that the moon 29 and August are submitted on the 23rd, combines incorporated herein by mode.As long as particle is
Predefined size, then subsequent processing can be provided for planarization process silicon particle for example in the silicon particle of required position.
An illustrative technology is shown in Fig. 1, wherein metal grate (a metal grid) 14 and an adhesion layer 12 1
It rises and uses.Sufficient amount of sphere 16 is subsequently placed at surface, so that the sphere around grid is moved in the use of mechanical oscillation,
Lead to being filled up completely for grid notch.Mechanical oscillation cause silicon ball body 16 in the volume of substrate, wall and capping composition to backhaul
Dynamic (move around).In a short period of time, sphere 16, which moves back and forth, reaches a certain level so that it encounters available grid
A possibility that position, is consistent, as long as sphere is still available.Fig. 2 shows that one this is made in band raster glass substrate
Device microphoto.In this case study on implementation, glass spheres and 20 microns a diameter of are used.Existed using mechanical oscillation
Move back and forth glass spheres on grid.Then it is moved with help from grid top surface on grid using high voltage (V≤12kV)
Dynamic sphere.Some extra spheres and dust it can be seen that but these clean room environment can be reduced or eliminated and/or
It is removed in subsequent processing step.
For large area, sphere be may be provided on the intensive line on surface, then in entire substrate surface with wave
Vibration.
Optionally, it can be used external electrode application electric field to move the particle on substrate, such as " Mechanics of a
process to assemble microspheres on a patterned electrode,"Ting Zhua,Zhigang
Suob,Adam Winkleman and George M.Whitesides,APPLIED PHYSICS LETTERS88,144101
(2006) description in, below as a reference 1.In this approach, using being placed in dielectric substrate (the dielectric
Substrate lower electrode and grid) below creates potential as opposite electrode (the counter electrode).Grid
Hole in lattice creates a potential well, and sphere can fall into potential well.Electric-force gradient around hole, which is enough to generate (create), acts on grain
Resulting net force on son.For sufficiently large effect place (kV), particle can move into hole.Vibration can need to make when starting
With to move back and forth sphere so that it meets the potential well.
In another way, it can be used using the similar treatment process in laser printing.In laser printer,
The charge that friction generates is applied to carbon powder particles.Then the carbon powder particles charged are applied in (toner cartridge (drum)) of static electrification
On substrate.Carbon powder particles in laser printing are subsequently transferred to the substrate of static electrification, usually paper.Laser in laser printing
For portraying pattern (write the pattern) on electrification toner cartridge, but since pattern will not change in production environment, swash
Light can be by grid instead.In first generation laser printer, carbon powder particles size is about 16 microns, the sphere essence phase with Fig. 2
Together.By applying voltage on the electrode below dielectric substrate to attract electrification sphere, and comparative electrode is set to grid, sphere
Selectively it is attracted to hole.This method is considered as describing the reinforcement of method in bibliography 1.
According to the other embodiments of first group of embodiment, spherical array is then shifted from the first substrate, movement
(acting) similar laser prints toner cartridge, until another non-patterned substrate (un-patterned substrate), the non-figure
The substrate of case is similar with the paper of electrification movement (acting), is analogized with described laser printing completely.Optionally, from
The spherical array transfer of one substrate to the second substrate is also achievable, for example, if in the second, adhesive of non-patterned substrate
Or the adhesive for being applied to sphere has more high melting temperature, bigger adhesion strength or electrostatic attraction.Although the example in Fig. 1
Device has used adhesion layer, and the grid (the substrate or grid under layer) under substrate or layer can be heat
Soften layer, such as the thermoplastic layer at raised temperature, so that sphere is adhesively attached to its position, and works as substrate and be cooled to extraneous ring
It is retained in when border on its position.Adhesive can be the thin layer being applied on substrate.Relatively small sphere means for viscous
The lesser thickness degree of mixture can get significant contact area.
Since silicon has fusion temperature more higher than glass, glass substrate be can be used directly, and such as be heated sufficiently to softening glass
Glass can permit sphere with this, either using silica dioxide coating or the sphere of removing oxidation, be adhered directly on glass,
The component of higher post-processing temperature can be born by providing one.This can be by such as using the electrostatic attraction in laser printing by particle battle array
Column are transferred to not patterned glass (un-patterned from a patterned substrate (a patterned substrate)
Glass it) realizes.Through directly fixed particle on glass, the window (the window) for higher temperature processing is expansible
To the temperature spot at the exposed place of semiconductor ball interior section.Same printing process can be used for other substrates.
After sphere 16 is located on suitable position, a conformal coating (a conformal coating) 18 is applied
And (a modification) such as chemically mechanical polishing/planarization process (CMP) then is corrected using standard, planar technology
It is flattened, as shown in fig. 3a, wherein SiO2Coating 18 be shown as covering spheroidal particle 16 and grid 14.Fig. 3 b is shown
After planarization and on the sphere 16 being truncated in the form of hemisphere before making devices sphere 16 identical array.Using
Standard, planar technology in production of integrated circuits can be utilized.Planarization can be carried out repeatedly in treatment process, this is because with
Multilayer sequence be arranged, the pattern can be more than (the topography can exceed that is supported by the process
That supported by the process), therefore applying conformal dielectric coating (a conformal dielectric
Coating planarization process) is carried out afterwards；And it is carried out at planarization after applying conductive coating (a conductive coating)
Reason.Interlayer connection is by the aperture on lithographic definition position (lithographically defined locations) or leads to
Setting between hole and layer is conductively connected (depositing conductive connections) or plug is formed.This is
Particularly advantageous.In the case where planarization metal layer, which will form the interconnection needed by needle drawing (patterned)
(interconnects).In the embodiments described, planarization process is executed to appear the inner section of semiconductor particle,
Relative to the first technology for the planarization for not appearing all lower surface elements, first technical description is in United States Patent (USP) 4470874, topic
Metal layer system, which is connected, for multilayer planarizes (Planarization of multi-level interconnected
Metallization system), it is filed in December nineteen eighty-three 15, is incorporated herein by reference to document form.
Although silicon ball random orientation is placed, the mobile anisotropy of silicon is small, so the device that manufacture obtains will be than those
There is better performance using the device that amorphous silicon or polysilicon make.However, if using be it is of less demanding and, for example,
High-speed equipment is not needed, then polysilicon or nonspherical particle also can be used.
The semiconductor particle of other forms can also be used.For example, if for specific application performance requirement properly,
Can be used powdered silicon, no matter monocrystalline silicon or polysilicon.In addition, repeatedly placing circulation can be used for placing different size or not
With the particle of material property, such as doping or crystalline or atom class, such as III-V, such as GaAs, such as it is used as the four of light source
First alloy or SiGe, for realizing the different function of resulting devices.
Standard photolithography techniques can be used in the silicon face making devices and production connecting line (interconnects) appeared
Or the element that other device functions need.The embodiment of described method, system and device allows nearly conventional CMOS devices
(nearly conventional CMOS devices) production；Also, it is conducive to utilize other techniques.According to some implementations
Example, used technique is without limitation.For example, N-shaped and p-type silicon particle can be arranged in different steps, to use respectively solely
Vertical silicon particle obtains n- trap or p- trap.In conventional CMOS, n- trap as shown in Figure 5 a must be in the lining of generally p-type
It is manufactured in bottom.Turning now to Fig. 5 b, shown in one manufactured in spheroidal particle similar to the device of Fig. 5 a, which is doped with
It is used to form the p-type material of p-type sphere.In the figure, hemispherical semiconductor devices 50 is shown, wherein planarization 56 shape of sphere
At the semiconductor devices (a gated semiconductor transistor device) of gate transistor, with source electrode
(S), drain (D) and grid (G) and contact zone B, the contact zone B shape when the device is located in dopant well as shown in the figure
At Substrate bias.In this case, individual devices are formed in the semiconductor spheres body of planarization process.Each extended from device
Line to the pole B, S, D and G is electrical connection.The quantity of the device independent within/on monocrystal particle can be manufactured very
The size of planarization regions is depended in big degree.For example, if device has 1 μm of grid length and 1 μm of through-hole, entire device
It may be the device of 5 μm of 5 μ m.However, the sphere with 20 μ m diameters will have greater than 300 μm2Surface area, this can hold
Receive several devices.For example, 2 × 2 pixel arrays or the single pixel with adjunct circuit, such as the circuit for life control
It is built-in.The considerations of sphere size, factor can be cost, stability and yield (yield).Device shown in Fig. 5 a can be
It is any or all for example in fig 3b shown in make on planarization sphere.
The symbol of transistor 55a, 55b indicate that (A symbolic representation) is shown in Fig. 5 c and 5d.Institute
The single lattice of description can also form independent circuit, encapsulate and run as independent device, substitute the class made on Silicon Wafer
Like device.Further doping is carried out to obtain NMOS and PMOS device in same sphere.In fig. 5 c such as transistor 55a, 55b
Controllable function device array can make.Although not shown in the array 58 of planarization sphere 56 (having connecting line 57),
One device array can also make in the same process.That is, doping will be completed at the same time whole transistors.Passivation
Layer 59 is directly applied on planarization sphere top after element manufacturing.Passivation layer 59 is placed on the active device (the at it
Active devices) on before it is shown.Although the advantage of described method and system is that the array of disposable type is equal
It can make, it is desirable to dividing the array is the smaller functional unit that can be placed in desired locations.Existing cutting silicon wafer
Round device can be used in this case.
The electronic building brick (electronic assembly) of generation is then used as various kinds of equipment such as display or imager
Elemental device.
According to some embodiments, non-glass substrates, such as plastics, polyester film (Mylar), polyimides or other application
Suitable material can also be used, and not only reduce production cost, also realize elasticity and plasticity (flexible and simultaneously
Moldable) device.Since the size of semiconductor particle reduces, minimum bending radius is also reduced.For silicon particle, than lining
Base thickness degree is smaller, and mechanical performance is heavily dependent on the non-element silicon on device, and therefore can obtain elasticity or can
Modeling or both combines.Device can also be made as the mechanical performance variation of entire device, and wherein mechanical stiffness is designated as at this
The function (a function of position) of position in device.
According to some embodiments, big substrate can cut to form small device, and similarly Silicon Wafer is cut into preferably
The device of size；It is smaller for the device counter substrate.The prior art can be applied, and cost and performance allow making for non-silicon substrate
With.Such as in multiple silicon devices, the region which is occupied by contact pad and connecting line can have identical with device area
Sequence (on the same order).In other application, it can be reinforced by using the substrate with larger thermal coefficient
Device performance.The spherical back face of particle provides biggish surface herein, can be dispersed by the surface heat.
So far method, system and the device of mentioned description can also be used similar production method for making solar energy
Battery.Turning now to Fig. 4 a to Fig. 4 f, it is shown that production solar battery process is wherein doped with p-type material shown in Fig. 4 a
Sphere 16 be located in the notch of band raster 14 and be fixed to their light-transmissive substrates 10 of support.Sphere and grid apply in fig. 4b
SiO2Layer 43 and the application metal layer 45 in Fig. 4 c.The structure is flattened in figure 4d, and the sphere has planarization
Top surface 47.Hole and conductive plug construction (vias and conducting plug formation) are provided in figure 4e
48.Meanwhile not showing in figure 4e, the flat site immediately below flat surfaces and n-type material are adulterated, next in Fig. 4 f
In step, connecting line 46 and 49 is formed so that all connecting lines are all located in flat upper surfaces, for connecting p and n material.On this
Portion planarization surface is actually formed the photovoltaic panel back side.
In some embodiments of first group of embodiment, term " planarization particle " or " particle with flat surfaces " etc.
It is same as the particle with entire flat surfaces longest dimension 15mm and at least 1 μm depth (d) perpendicular to the platform surface.
Preferably these particles are sphere, globoid or imperfect sphere or orbicule.However other shapes of particle also at first group and
In the range of second group of embodiment.Fig. 6 a to Fig. 6 d illustrates various shapes of particle 60 and shows the vertically smooth table with particle
The depth (d) in face.
Now directly pay attention to Fig. 7 a to Fig. 7 c, depicts one according to the non-limiting embodiments of a subset of second group of embodiment
The method that kind makes semiconductor bottom plate.Semiconductor particle 70a, 70b, 70c, 70d, 70e and 70f are also referred to herein as partly led
Body particle 70 and it is portrayed as sphere, is also referred to herein as supporting member 72 in perforation 71a, 71b, 71c, 71d, 71e, 71f-
It is arranged in perforation 71-.Similar with first group of embodiment, semiconductor particle 70 can worn by the mechanical oscillation of supporting member 72
It is arranged in hole 71.Semiconductor particle 70 can also be by respectively placing semiconductor particle 70a, 70b, 70c, 70d, 70e and 70f
In perforation 71a, 71b, 71c, 71d, 71e and 71f setting in perforation 71.However, the list and not exhaustive, any in perforation 71
The suitable method of middle setting semiconductor particle 70 is expectable.
Although Fig. 7 a to 7c depicts a large amount of semiconductor particle, according to some examples, single semiconductor particle setting
In the single perforation of supporting member.Further, although semiconductor particle 70 includes such as the sphere in first group of embodiment half
The shape of each and form of conductive particle 70 may include various grain shapes.The example of various shapes of semiconductor particle 70
Describe in Fig. 6 a into 6d.In first group of embodiment, if for the performance requirement of specific application being suitable, semiconductor grain
Son 70 may include a variety of materials, such as silica, powder silicon, no matter monocrystalline or polycrystalline.For example, semiconductor particle 70 may include
Silicon ball.According to embodiment, semiconductor particle has same size and/or shape.According to some embodiments, semiconductor particle
70 include various shape and/or size.Such as semiconductor particle 70a may include triangle (such as Fig. 6 c description), semiconductor particle
70c may include irregular shape (such as Fig. 6 d description) and remaining semiconductor particle 70b, 70d, 70e and 70f may include various types
Number sphere or globoid.
Supporting member 72 is used as the support construction of production semiconductor bottom plate.Supporting member 72 may include all kinds of shape, structures
And size.According to some embodiments, supporting member 72 includes hollow cylinder (cylinder) or roller (drum), and one is basic
One in upper solid cylindrical body (cylinder) or roller (drum), a plane institution movement, a bent member and a transmission member
It is a.Some example of shape of supporting member are depicted according to non-limiting embodiments in Fig. 8 a and 8b, wherein analogous element passes through
The number similar or similar with Fig. 7 a to Fig. 7 c is labeled, although with " 8 " beginning rather than " 7 ".For example, supporting member 82a,
82b corresponds to the supporting member 72 manufactured according to other non-limiting embodiments.In Fig. 8 a into 8c, supporting member 82a includes
One bent member, supporting member 82b includes a hollow cylinder (cylinder) and supporting member 82c includes a transmission with holes
Band.It should be noted that 82a, 82b and 82c offer are merely to illustrate, the other structures of described supporting member are also contemplated by.
Supporting member 72 may include a variety of materials.For example, supporting member may include one of steel and porcelain material.For half
The application of conductor substrate, particular production condition and " heat balance " or the temperature limiting of material for being used to form semiconductor bottom plate can
Influence the material of (inform) supporting member 72.
Perforation 71 is portrayed as the hole (through-thickness holes) in whole thickness in figures 7a to 7c.However,
Any perforation that suction can be made to be applied to other parts 74 is expectable.It therefore, can be with according to some embodiments perforation 71
Only penetrate the depth that supporting member 72 to one is less than penetration thickness (through-thickness).For example, as depicted in fig. 9
, perforation 91 can be attached together to pressure gradient-force 95 (described below) in each perforation by conduit (duct) 99
In 91a, 91b, 91c, 91d, 91e and 91f via conduit 99 generate, wherein analogous element be labeled as with Fig. 7 a to Fig. 7 c it is similar or
Similar number, however start with " 9 " beginning rather than with " 7 ".
Further, the quantity of the perforation 71 of entire supporting member 72 and arrangement are variable.According to some embodiments,
Perforation 71 includes single column (such as perforation 71a).According to some embodiments, between perforation 71 is uniform in entire supporting member 72
Every.According to some embodiments, perforation 71 anisotropically arranges in entire supporting member 72.According to some embodiments, wear
Hole 71 is located at scheduled position in entire supporting member 72.For example, if the semiconductor bottom plate is for making display
Device, perforation 71 will be set to the position of transistor or other electrical connections connection semiconductor particles 70.
According to some embodiments, perforation 71 has different size and shape.Perforation 71 is arranged in any suitable manner
Column are suitable for applying, make and/or transport semiconductor bottom plate.According to some embodiments, multiple devices (multiple
Devices it) can be made by identical semiconductor bottom plate.In this kind of embodiment, semiconductor bottom plate can be divided into several representatives
The each individually subregion of device or region.If device is that different components (such as different sizes, auxiliary penetrate requirement
(emission requirements), power requirement etc.), each subregion or region may need different size, ingredient and/or
The semiconductor particle of shape.Therefore, in these embodiments, perforation 71 can have different arrangements in each region
And/or size.Semiconductor bottom plate is separated by each subregion or region therewith, such as passes through the semiconductor bottom cutting (cutting up)
Plate makes for further individual devices.
Perforation 71 be dimensioned to acceptable semiconductor particle 70 so as to a part 73 (for semiconductor particle 70a, 70b,
70c, 70d, 70e are respectively part 73a, 73b, 73c, 73d, 73e and 73f) it is prominent from supporting member 72.According to some implementations
Size (such as production is sufficiently thin) is arranged so that the more than one part of semiconductor particle 71 passes through in mode, supporting member 72
Perforation 71 is prominent from supporting member 72.For example, according to some embodiments, compared to semiconductor particle 70, supporting member 72
The sufficiently thin protrusion from supporting member 72 so as at least part of part 73 and at least part of other parts 74.Part 73
From the amount outstanding of supporting member 72, such as distance (d), it is likely to be dependent on the application of semiconductor bottom plate, utilizes the device of semiconductor bottom plate
The structure and/or design requirement of part.Further, size is arranged so that semiconductor particle 70 does not penetrate perforation 71 in perforation 71.
Suction is applied to another part 74 (semiconductor particle 70a, 70b, 70c, 70d, 70e and 70f of semiconductor particle 70
Respective another part 74a, 74b, 74c, 74d, 74e and 74f) with maintain semiconductor particle 70 perforation 71 in.It should be noted that this
In " suction " that describes be pressure gradient-force 75 (being also herein pressure gradient-force 75a, 75b, 75c, 75d, 75e and 75f),
The pressure gradient-force results from around the region of another part 74 in perforation 71 and is in fluid communication with perforation 71 another interregional
Pressure difference.For example, another region can be the low-pressure chamber in vacuum plant, (coupled) is effectively connected to supporting member
72 and/or perforation 71.As discribed in Fig. 7 a and 7b, pressure gradient-force 75 attracts or forces semiconductor particle 70 towards going forward side by side
Enter perforation 71, this facilitate prevent semiconductor particle 70 fall off or remove respective perforation 71a, 71b, 71c, 71d, 71e and
71f.It should be noted that perforation 71 is configured to apply suction on another part 74, allow various arrangements.As will be appreciated, another
Part 74 includes a region or position for semiconductor particle 70, this depends on application, can be the position for electrical connection.?
It should be understood that perforation 81a, the 81b and perforation 81c that perforates also configure with perforation 71 similar in Fig. 8 a into 8c.
As discribed in Fig. 7 b, sealing material layer 76 is applied on supporting member 72 so as to the part of semiconductor particle 70
73 are covered by sealing material layer 76.Another part 74 of semiconductor particle 70 not (is largely shielded from) with it is close
The connection of closure material layer 76 and/or adherency.In semiconductor bottom plate, sealing material layer 76 supports semiconductor particle 70 and is connected thereto
(such as being fitted to each other (in cooperation with each other)) together.According to some embodiments, sealing material
The bed of material 76 can be light transmission or opaque.According to some embodiments, sealing material layer 76 divides for different translucency
And/or subregion or the region of ingredient.As above statement, according to some embodiments, multiple devices can be by same semiconductor bottom
Plate makes and is divided into several subregions or region for each device.In this embodiment, the property of sealing material layer 76 can
According to this regional change, including ingredient, translucency and/or thickness.
Sealing material layer 76 can take many forms.According to some embodiments, sealing material layer 76 includes fluid (a
fluid).According to some embodiments, sealing material layer 76 includes one kind of powder, thin slice or film.According to some embodiments,
Sealing material layer 76 includes one of fluid (a fluid), powder and thin slice or a variety of.For example, sealing material layer 76 can wrap
Containing gel slice.According to the application of semiconductor bottom plate, the desirable properties and ingredient of sealing material layer 76, it may be necessary to by sealing material
76 fluidisation of the bed of material.Include sealing material a kind of in powder and thin slice after sealing material layer 76 applies according to some embodiments
The bed of material 76 carries out fluidisation.According to some embodiments, fluidisation includes fusing sealing material layer 76 and polymer sealing material layer
76 one kind.For example, fusing sealing material layer 76 includes heating supporting member 72.
Sealing material layer may also comprise various substances (a variety of substances).According to some embodiments,
Sealing material layer 76 includes one of glass, plastics and photocuring cement.
The form and ingredient (The form and composition) of sealing material layer 76 can be according to semiconductor bottom plates
Desired characteristic and change.Such as it may be desirable to a kind of semiconductor bottom plate of elasticity in order to transporting.It, should according to some embodiments
Semiconductor bottom plate is sufficiently flexible to rollable.In rolled form, each per surface of semiconductor bottom plate and typical rigid face
Plate is compared and occupies smaller space, therefore is more easily transported.It, can be by making opposing seal material according to some embodiments
It the relatively thin sealing material layer 76 of other sizes (such as length and width) of layer 76 and/or selects a kind of to promote flexible object
For example flexible polymer of matter (a flexible polymer), to make sealing material layer 76 to improve in semiconductor bottom plate
Flexibility.
According to some embodiments, sealing material layer 76 is processed to promote the adherency with semiconductor particle 70.For example, can
Apply the sealing material layer of glue or epoxy on sealing material layer 76, at 73 position of part including semiconductor particle 70
76 thin slice.Alternatively, or in addition, semiconductor particle 70 is processed to promote adherency or engagement with sealing material layer 76.Example
Such as, glue or epoxy can be applied at least part of the part of semiconductor particle 70 73.
Although sealing material layer 76 can be made of multi-layer sealed glue material referring to " one " layer is set as.For example, sealing material
The bed of material 76 can gradually carry out building until reaching the expection thickness of sealing material layer 76 by applying relatively thin sealing material layer
And form.In another non-limiting embodiments, in order to reach expected characteristic, sealing material layer 76 may include multi-layer sealed glue
Material, wherein every layer is made of different substance or state.
The application of sealing material layer 76 can be there are many form.According to some embodiments, applies sealing material layer 76 and wrap
Containing following first, spray (spraying) sealing material on supporting member 72, it is close that (pouring) is toppled on supporting member 72
(spreading) sealing material is unfolded in closure material on supporting member 72, and (rolling) sealing is rolled on supporting member 72
Material suppresses (pressing) sealing material, with sealing material electrostatic coating on supporting member 72
(electrostatically coating) supporting member 72 and the vacuum forming sealing material on supporting member.
If Fig. 7 c is discribed, supporting member 72 is detached from or is removed to expose semiconductor particle and sealing material layer 76
Component (an assembly) 77." disengaging " may include separating supporting member 72 or vice versa (from supporting member from component 77
72 separation assemblies 77).For convenient for being detached from, before applying sealing material layer 76, the object for promoting to be detached from is can be used in supporting member
Matter or ingredient (being alternatively referred to as " release agent " herein) processing.For example, supporting member 72 can gathering with non-stick coating such as Du Pont
Tetrafluoroethene(E.I.du Pont de Nemours) coating.According to some embodiments, supporting member 72 can be with
It is removed with form of chips, is removed not as full wafer.For example, if semiconductor bottom plate is used to make multiple devices, some
In related embodiment, supporting member can be in a manner of being connected to multiple subregions of component 77 of semiconductor bottom plate or region
It is removed or is detached from, this is related with what is utilized.Fall off mode and/or pressure gradient-force 75 based on supporting member 72 it is strong
Degree, the suction for generating pressure gradient-force 75 can remove before the disengaging of supporting member 72.
Further, as Fig. 7 c is discribed, since another part 74 is not contacted and/or is adhered to sealing material layer, because
This does not need to remove sealing material from semiconductor particle 70 to expose at least part of semiconductor particle 70 for further
Processing.According to some prior art approach, semiconductor particle is coated completely by sealing material and/or substrate material
(completely enveloped), it is therefore desirable to using photoetching or other technologies carefully remove enough sealing materials and/
Or substrate material to be to appear semiconductor particle, while not damaging any semiconductor particle.The method of described embodiment and
Therefore system avoids this additional step, so that cost of manufacture reduces compared with the first method in this field.
Figure 10 is directly paid close attention to, which depict at least part of another part 74 of semiconductor particle 70 to be flattened with shape
At the component 77 after semiconductor bottom plate 78.The removal part-of the another part 74 removed by planarization is labeled as 74 '-number
Amount may depend on the application of semiconductor bottom plate 78, electrical connection (the electrical including that can be formed on semiconductor particle 70
connections).A variety of planarizations are available.According to some embodiments, planarization process is thrown comprising chemical machinery
Light (CMP).According to some embodiments, planarization process includes polishing and/or grinded semiconductor particle 70.According to some implementations
Mode, semiconductor particle 70 further pass through radium-shine recrystallization (laser recrystallization) after planarization process
It is handled.
As depicted by figure 10, it is held in the plane that the planarization of semiconductor particle 70 can be parallel to sealing material layer 76 one
Row (performed), the plane marker are plane 79.It should be noted that after being detached from supporting member 72, the sealing material of component 77
Layer 76 is usually plane or flat.According to some embodiments, plane 79 and sealing material layer 76 are in same plane (example
Such as coplanar (co-planar)).For example, plane 79 can be located at identical plane with the surface 72 ' or 72 " of sealing material layer 76.
It is desirable that plane 79, which is in the technology of 76 same level of sealing material layer (such as surface 72 ") based on making devices on the semiconductor,
's.For example, photoetching generally uses light shield (masks) to appear the photosensitive material region in sealing material layer surface.Photosensitive material or
The region that the subsequent exploitation (Subsequent development) of photoresist (photoresist) appears sealing material layer is used for
It is further processed.This photoetching treatment is generally used for semiconductor machining and usually requires a flat surface, wherein flatness
(planarity) the energy power limit of tool is photo-etched at image forming surface (an image), regardless of sealing material layer
How is pattern.Planarization is still required even with replacement technology such as ink jet printing.
According to some embodiments, semiconductor particle 70 carries out planarization process along two planes, and the first plane is parallel
In or coplanar be parallel to surface 72 " so that semiconductor particle 70 is flat on both sides or surface in surface 72 ' and the second plane
Change.The semiconductor surface that semiconductor particle 70 appears semiconductor particle 70 on two surfaces is planarized, on both sides to be used for device
Part, connecting line and electrical via production are formed on the both sides of device.For example, electronic device can be placed in semiconductor particle 70
A planarization surface on, while activate contact pad (active contact pads) (such as with ESD protect and drive
The contact pad of transistor) it is arranged on another planarization surface of semiconductor particle 70, wherein two planarization surfaces pass through
It is made in (the remaining surrounding layer of of sealing material layer 76 in semiconductor or around reservation
Encapsulant material 76) in electrical via connection.Obtained integral device is more compact, due to being normally used for
The region of connecting line pad now can be used as circuit (circuitry).
Further, electrical equipment (the electrical devices) is cleavable and form one single chip
The small cube of (individual die).Connection pad is not necessarily wire bond pads, but can be used for chip attachment (die-
Attach), ball bond (ball bonds) or other standards method are directly to mount to printed circuit board (PCB).
According to a related embodiment, single core can be cut to form using the electrical equipment that semiconductor bottom plate 78 is formed
The small cube of piece, and after mounting to PCB or other carriers, the sealing material layer 76 of reservation can be by any convenient method such as
The sealing material layer 76 that dissolution or fusing retain removes therewith, leaves the present lesser device for installing and being electrically connected.
According to some embodiments, electrical small cube (the electrical dices) or semiconductor bottom plate can be with heaps
It puts.
In some cases, one is preferably formed with structural rigidity rather than only has the semiconductor bottom of sealing material layer 76
Plate.1a and 11b refering to fig. 1, wherein similar element is indicated by the like numerals in Fig. 7 a to Fig. 7 c, according to some embodiments,
Substrate material layer 111 is applied on sealing material layer 76.Substrate material layer 111 constitutes (composition) and/or phase by it
Further structural support and rigidity are provided for double of conductor substrate of thickness 113 (as shown in figure 11b) of sealing material 76.
Substrate material layer 111 can take many forms.For example, substrate material layer 111 may include fluid (a fluid), consolidate
Body thin slice and powder.
According to some embodiments, the application of substrate material layer 111 prior to removing (releasing) or removes supporting member
72 to appear component 112, and then the component includes semiconductor particle 70, sealing material layer 76 and substrate material layer 111.According to one
A little embodiments, applying substrate material layer 111 includes following first, suppressing (pressing) substrate material on sealing material layer 76
Material, topples over (pouring) substrate material, smooth (flowing) substrate material on sealing material layer 76 on sealing material layer 76
Material sprays (spraying) substrate material on sealing material layer 76 and rolls (rolling) lining on sealing material layer 76
Bottom material layer 111.According to some embodiments, substrate material layer 111 includes following first, glass, flexible glass (flex-
) and plastics glass.
In order to reinforce, solidify and/or promote the bonding between semiconductor particle 70 and sealing material layer 76, in some embodiment party
In formula, sealing material layer 76 is solidified.Likewise, in order to reinforce, solidify and/or promote sealing material layer 76 and substrate material
Bonding between layer 111, one or more sealing material layers 76 and substrate material layer 111 are solidified.Further, in order to promote
Bonding between sealing material layer 76 and substrate material layer 111 applies adhesive to the one or more sealing material layer 76 and lining
Bottom material layer 111.According to sealing material layer 76 and the ingredient (composition) and performance of substrate material layer 111, curing process
It may include such as heating, expose under ultraviolet light and/or sealing material layer 76 and/or the application of substrate material layer 111 be suitble to
Chemical assistant.
Figure 11 c to 11e directly is gone to, which depict the production according to the semiconductor bottom plates of non-limiting embodiments, and wherein
It is indicated to the similar or analogous element that Fig. 7 a describes into 11b using similar or like numerals.
Semiconductor particle 70 be arranged in the perforation 171 of supporting member 172 so as to a part of the semiconductor particle 70 from
It is prominent in supporting member 172.Suction 175 or pressure gradient-force 175 are applied to the other part of semiconductor particle 70 to keep half
Conductive particle 70 is located in perforation 171.According to some embodiments, semiconductor particle 70 is being transported or is being moved to for adhering to
Or it is preloaded on supporting member 172 before being fixed at the position of sealing material layer 176.According to some embodiments, apply
Adhesive is on the protrusion of semiconductor particle 70.
Sealing material layer 176 is applied in substrate material layer 111.Sealing material layer may include as tacky in being partially baked to
Spin-coating glass (spin-on glass) or ultraviolet curing cement (UV curable cement).According to some embodiments,
Substrate material layer 181 is replaced using another component, for sealing material layer to be positioned and supported during making semiconductor bottom plate
176.According to those embodiments, which is detached from (released) or is removed after forming component (assembly) 177 and (retouched
It states as follows).
As discribed in Figure 11 d and 11e, the supporting member 172 of semiconductor particle 70 is carried, sealing material is compressed on
It (is specified by direction arrow 180) on the bed of material 176.Supporting member 172 is then detached from or is removed from component 177
(released or removed), component 177 include semiconductor particle 70, sealing material layer 176 and substrate material layer 181.?
In described embodiment, suction 175 or pressure gradient-force 175 are removed so that supporting member 172 is detached from from component 177.
According to some embodiments, sealing material layer 176 is cured and/or is toasted to solidify and help sealing material layer 176 and be attached on
On semiconductor particle 70 and/or in substrate material layer 181.The semiconductor particle 70 of component 177 then as described herein into
Row planarization process.
Figure 12 directly is gone to, describes the method 1200 for making semiconductor substrate according to non-limiting embodiments.For
Assisted interpretation methods 1200, it is assumed that method 1200 is executed by using element described in Fig. 7 a, 7b, 7c, 10 and 11a to 11e.
Further, 1200 following discussion of method will cause to further understand described element.It is, however, to be understood that Fig. 7 a,
The element of 7b, 7c, 10 and 11a to 11e and/or method 1200 be it is transformable, do not need the description one as being respectively self-bonded herein
Sample accurately executes, and these variations are within scope of embodiments herein.
It should be emphasized that method 1200 need not be as shown exact sequence execute, unless otherwise indicated；Similarly various frames
Figure can be executed parallel rather than be executed in order；Therefore the element of the method 1200 referred here to is as " block diagram " rather than " walks
Suddenly ".
At block diagram (block) 1205, semiconductor particle 70 is arranged in the perforation 71 of supporting member 72 so as to part 73
It is prominent from supporting member 72.At block diagram 1210, apply suction to another part 74 of semiconductor particle 70 to keep partly leading
Body particle 70 is in perforation 71.According to some embodiments, scanning and/or check supporting member 72 with ensure semiconductor particle 70a,
70b, 70c, 70d, 70e and 70f occupy perforation 71a, 71b, 71c, 71d, 71e and 71f respectively.At block diagram 1215, supporting
Apply sealing material layer 76 on component 72 so that part 73 is covered by sealing material layer 76.
According to some embodiments, preferably by 76 fluidisation of sealing material layer.Therefore, at the block diagram 1220 of method 1200,
Sealing material layer 76 is fluidized.According to some embodiments, fluidisation sealing material layer 76 includes following first, fusing sealing material
The bed of material 76 and polymer sealing material layer 76.However, according to some embodiments, sealing material layer 76 has included fluid, therefore block diagram
1220 are not required to execute.
At block diagram 1225, sealing material layer 76 solidifies, for as promoted hardening, solidification and/or promoting semiconductor particle
Bonding between 70 and sealing material layer 76.
At block diagram 1230, the application of substrate material layer 111 is covered on sealing material layer 76.With 76 class of sealing material layer
Seemingly, substrate material layer 111 can solidify at 1235 to form component 112.Component 112 includes semiconductor particle 70, sealing material
Layer 76 and substrate material layer 111.
At block diagram 1240, component 112 is in the mode similar with the component 77 described above that falls off from supporting member 72
It is detached from.
At block diagram 1245, another part 74 of the semiconductor particle 70 of component 112 with the above planarization component 77
The similar mode of semiconductor particle 70 carries out planarization process.
Directly pay attention to Figure 13, which depict the systems 1300 for being used to make semiconductor bottom plate according to non-limiting embodiments.
Supplemented by assistant solution, system 1300 just production semiconductor bottom plate 78 be described.System 1300 is retouched according to stage (A) and stage (B)
It states.The stage (A) of system 1300 include with perforation 1301 supporting member 1302, perforate 1301 size be set as accommodate partly lead
Body particle 70 is prominent from supporting member 1302 so as to part 73.The embodiment according to shown in Figure 13, supporting member 1302 wrap
Containing a punched-type transmission device (a perforated conveyor).According to embodiment depicted in figure 13, semiconductor particle
70 are placed on supporting member 1302 by siphon pipe 1303, which is connected to a hopper (not shown).
Suction unit 1304 is operably coupled to supporting member 1302 and to apply suction another to semiconductor particle 70
Part 74 is to maintain semiconductor particle 70 in perforation 1301.According to some embodiments, suction unit 1304 includes vacuum plant.
The stage (A) of system 1300 further includes applicator (an applicator), is used in supporting member 1302
Upper application (applying) sealing material layer 76, so that the part 73 of semiconductor particle 70 is covered by sealing material layer 76.According to
Some embodiments, the applicator for applying sealing material layer 76 include following first, sprayer (a sprayer), roller (a
) and suppressor (a press) roller.As described in Figure 13, for applying applying for sealing material layer 76 in system 1300
Adding device includes sprayer 1305.
According to some embodiments, supporting member 1302 is heated to assist solidifying sealing material layer 76.
System 1300 further include one for by the component 77 of semiconductor particle 70 and sealing material layer 76 from support structure
The release unit (a releasing apparatus) being detached from part 1302.The embodiment according to described in Figure 13, release unit
Comprising lifter 1306 (lifter), with component 77 crosses supporting member 1302 towards lifter 1306 can be lightly from branch
Support component 1302 is raised component 77.
In the stage (B) of system 1300, a planarizer planarizes another part 74 of semiconductor particle 70.According to figure
Embodiment described in 13, component 77 cross conveyer belt (conveyor) 1308 under planarizer grinder 1307, and
Form semiconductor bottom plate 78.
Directly notice that Figure 14 a to 14d describes according to the second subset of second group of embodiment according to non-limiting embodiments
Method for making semiconductor bottom plate, and wherein similar element uses the numeral mark similar with Fig. 7 a to 13.Substrate
140 have perforation 141a, 141b, 141c, 141d, 141e and 141f, also referred herein as perforation 141.Perforation 141 is similar to Fig. 7 a
It is being aspirated to embodiment described in 13, this can be regarded as by 142 (also referred herein as pressure gradient-force of pressure gradient-force
142a, 142b, 142c, 142d, 142e and 142f) it generates.Term " suction " and " pressure gradient-force " can be interchanged here to be made
With.Pressure gradient-force 142 or suction 142 region as defined by perforation 141 and the area of low pressure with the fluid communication of perforation 141
Between pressure difference production.For example, the area of low pressure can be the low-pressure chamber in vacuum plant, it is operably coupled to lining
Bottom 140 and/or perforation 141.
In semiconductor bottom plate, the support of substrate 140 simultaneously links together the (such as (in that is bonded to each other with semiconductor particle 70
cooperation with each other)).According to some embodiments, substrate 140 can be light transmission or opaque.According to one
A little embodiments, substrate 140 are divided into several subregions or region with different translucency and/or ingredient.As described above, according to one
A little embodiments, multiple devices it is available with semiconductor bottom plate (the same semi-conducting backplane) production and
It is divided into subregion or the region of individual devices.In this type of embodiment, the property (characteristics) of substrate 140 also root
According to these regional changes, including ingredient, translucency and/or thickness.
Diversified forms can be used in substrate 140, such as the thin slice of substrate material.Backing sheet 140 can be by spraying or depositing
(depositing) substrate material is formed on a roller or conveyer belt in the mode on the surface of roller or conveyer belt.If needed
It wants, substrate material can be melted or polymerize.Substrate 140 also includes several substances (substances).According to some embodiments, lining
Bottom 140 includes following first, glass, plastics, flexible glass and plastics (flex-glass and plastic).For example, substrate
140 may include a flexible glass thin slice.
The form and ingredient of substrate 140 can be changed based on the desired characteristic of semiconductor bottom plate.Desirable one flexible half
Conductor substrate is easily to transport.For example, semiconductor bottom plate is sufficiently flexible to be rolled-up according to some embodiments.It is rolling
Under form, the every cell surface region of semiconductor bottom plate can occupy less space compared to conventional rigid panel, therefore be easier to transport
It is defeated.It, can be by making the substrate relatively thin with respect to the size (such as length and width) of other substrates 140 according to some embodiments
140 and/or selection promote flexible substrate, such as flexible polymer production substrate 140 to promote in semiconductor bottom plate
Flexibility.According to some embodiments, substrate 140 includes flexible glass flake, and thickness is about 100 μm.According to some implementations
Example, as a part of subsequent processing, one or more substrates 140 and semiconductor bottom plate 147 are fabricated to reel.
According to some embodiments, semiconductor bottom plate 147 forms the part of display, and the display is inside curved surface
On formed.According to these embodiments, substrate 140 can be the sufficiently flexible thin slice that can be deformed in process, so as to
Relaxation becomes bending (such as molded non-planar) to substrate 140 later.According to some embodiments, semiconductor bottom plate 147 and appended
Electronic device, be such as lithographically formed using flatening process.Therefore, it according to some embodiments, is made on one big sphere aobvious
During showing device, semiconductor bottom plate 147 and substrate 140 are manufactured as a plane projection of the sphere, then around the ball packet
Wrap up in or be processed into the shape of the ball.
As discribed in Figure 14 b, the part 145 in perforation 141 so as to semiconductor particle is arranged in semiconductor particle 70
(also referred to as part 145a, 145b, 145c, 145d, 145e, 145f and 145g) is prominent from substrate 140.According to some implementations
Example, semiconductor particle 70 can be arranged in perforation 141 by the mechanical oscillation of substrate 140.Semiconductor particle can also be by dividing
Do not place each semiconductor particle 70a, 70b, 70c, 70d, 70e and 70f respective perforation 141a, 141b, 141c, 141d,
It is arranged in perforation 141 in 141e and 141f.However, the list and not exhaustive, any suitable setting half in perforation 141
The method of conductive particle 70 is contemplated that.
Perforation 141 is sized to receive semiconductor particle 70, and semiconductor particle is made not pass through perforation 141.Described
Embodiment in, substrate 140 be sized to semiconductor particle 70 part 145 and part 146 it is prominent from substrate 140.According to one
Only have one in a little embodiments, part 145 and part 146 to protrude from substrate 140.
Part 145 and/or part 146 may depend on semiconductor from the amount outstanding of substrate 140, such as apart from (d) or (e)
The application of bottom plate, using the semiconductor bottom plate device design structure and/or design requirement.
Further, can change across the quantity of the perforation 141 of substrate 140 and arrangement.According to some embodiment party
Formula, perforation 141 include a single perforation (such as perforation 141a).According to some embodiments, perforation 141 is on entire substrate 140
Uniform intervals.According to some embodiments, the uneven arrangement on entire substrate 140 of perforation 141.According to some embodiments, perforation
141 are arranged in the pre-position of entire substrate 140.For example, perforating if semiconductor bottom plate will be used to make display
141 are placed on the transistor connecting with semiconductor particle 70 or other electronics junctions.
Perforation 141 can manufacture on substrate 140 or intrinsic for substrate 140.According to some embodiments, perforation 141 can lead to
It crosses cutting or punching substrate 140 is mechanically formed.According to some embodiments, perforation 141 is as formulating substrate 140
A part of casting process is formed.According to some embodiments, perforation 141 is formed by chemical etching.According to some embodiments, wear
Hole 141 includes hole or pit (pits) intrinsic in substrate 140.
According to some embodiments, perforation 141 has all size and shape.Perforation 141 is with any suitable application, production
And/or the mode of transport semiconductor bottom plate arranges.According to some embodiments, multiple devices are made by same semiconductor bottom plate.?
In this kind of embodiment, semiconductor bottom plate can be divided into several subregions for representing each independent device or region.If device is not
Same device (such as different sizes, emission requirements (emission requirements), power requirement (power
Requirements) etc.), each subregion or region may need the semiconductor particle of different size, structure and/or shape.Cause
This, in these embodiments, perforation 141 can be arranged differently in each region.Semiconductor bottom plate may be according to each point later
Area or region are for example by cutting semiconductor bottom plate, further to make respective device.
Semiconductor particle 70 is retained in perforation 141 by pressure gradient-force 142.As described in Figure 14 a and 14b, gas
Pressure gradient force 142 attracts or forces semiconductor particle 70 toward and into perforation 141, this help to prevent semiconductor particle 70 from
It falls off or removes in respective perforation 141a, 141b, 141c, 141d, 141e and 141f.
Substrate 140 is adhered to the component 143 that substrate 140 and semiconductor particle 70 are formed on semiconductor particle 70 (in Figure 14 c
Describe).Any mode for being suitble to that semiconductor particle 70 is attached on substrate 140 at 141 positions of perforating is expectable.According to one
A little embodiments, it includes following one or more on semiconductor particle 70 that substrate 140, which is adhered to: being applied in perforation 141
(applying) adhesive；Apply (applying) adhesive on semiconductor particle 70；Heat substrate 140；And cured substrate
140.According to some embodiments, one or more of substrate 140 and semiconductor particle 70 are processed to promote to be bonded to partly to lead
Body particle 70.For example, adhesive such as glue or epoxy resin be applied to perforation 141 and inner wall and one of semiconductor particle 70
Or it is multiple.As another example, substrate 140 can be heated to soften substrate 140 around semiconductor particle 70.
As described in Figure 14 d, at least part of the part 145 of semiconductor particle 70 is flattened processing to form half
Conductor substrate 147.By the removal partial amount of another part 145 that planarization removes, 145 ' are denoted as, semiconductor is likely to be dependent on
The application of bottom plate, including that can make to the electrical connection of semiconductor particle 70.Various planarizations are available.According to some realities
Example is applied, planarization includes chemically mechanical polishing (CMP).According to some embodiments, planarization includes polishing or grinded semiconductor grain
Son 70.According to some embodiments, semiconductor particle is further processed by laser recrystalliza after planarization.
According to some embodiments, the part of planarization is located at following first, being parallel to the plane and substrate 140 of substrate 140
Plane face in (such as coplanar).For example, semiconductor particle carries out at planarization along plane 144 as discribed in Figure 14 d
Reason, the plane 144 are at least parallel with one of the surface 140 ' and 140 " of substrate 140.According to some embodiments, semiconductor particle edge
Two planes carry out planarization process, the first plane is parallel to or coplanar with surface 140 ', and the second plane is parallel to or and table
Face 140 " is coplanar.Semiconductor particle 70 is planarized in two sides, partly leading for semiconductor particle 70 is appeared on two surfaces of substrate 140
Body surface face, allows device, and connection and electrical via hole (electrical vias) are manufactured in device two sides.For example, electronic device can
Be placed on a planarization surface of semiconductor particle 70, at the same activate contact pad (such as with ESD protect and drive crystal
The contact pad of pipe) it is arranged on another planarization surface of semiconductor particle, this two planarization surface is partly led by being produced on
In body or be centered around around substrate 140 electrical via hole connection.Obtained entire device is more compact, this is because being commonly used in
The region for connecting pad, is currently used for electronic circuit (circuitry).
Further, electrical part can be cut into small pieces to form one single chip (individual die).Contact pad need not
For wire bond pads, but it can be used for chip attachment, ball bond or other directly attachments to the mark on printed circuit board (PCB)
Quasi- method.
According to one in relation to embodiment, fritter is segmented into using the electrical part of semiconductor bottom plate 147 and forms independent chip,
And after mounting to PCB or other carriers, substrate 140 can be then removed by any convenient mode, such as dissolution or molten
Change substrate, leaves now lesser, mounted and electrical connection device.
According to some embodiments, electrical chip or semiconductor bottom plate can be stacked.
As described in Figure 15, wherein similar component is with labelled notation similar in Fig. 7 a to 14, it is possible to provide substrate 140 to
Supporting member 152.Supporting member 152 is configured to apply suction 142 to the perforation 141 of substrate 140, is operably connected via one
The vacuum plant of perforation 153 into supporting member 152.When supporting member 152 rotates, semiconductor particle 70 passes through siphon pipe
151 settings enter perforation 141, and siphon pipe 151 is bound to a hopper (not shown).
Supporting member 152 is used as the support construction of substrate 140 and provides suction 142 to perforation 142 to maintain semiconductor grain
Son 70 is in perforation 141.With supporting member 72,82a, 82b, 82c, 92 and 1302 are similar, and supporting member 152 may include various shapes
Shape, construction and size.According to some embodiments, supporting member 152 includes following first, hollow cylinder or roller, essentially solid
Cylinder or roller, plane institution movement, curved surface member and transmission member.According to some embodiments, supporting member 152 include it is following it
One: supporting member 72,82a, 82b, 82c, 92 and 1302.
Supporting member 152 may include a variety of materials.For example, supporting member may include one of steel and ceramics.Partly lead
The application of body bottom plate, special facture condition and " heat budget " are used to form the temperature limiting of material of semiconductor bottom plate and very may be used
It can influence the material of (inform) supporting member 152.
For example, supporting member 152, which can be heated to melted substrate 140, makes substrate 140 be adhered to half according to some embodiments
Component 143 is formed on conductive particle 70.In this type of embodiment, supporting member 152 may include a heat conducting element.
According to some embodiments, the perforation 153 in perforation 141 and supporting member 152 in substrate 140 is not aligned with each other
Or offset relative to each other (are offset with respect to each other).According to some embodiments, perforation
153 include ditch (channels) or slot.According to some embodiments, perforation 153 is sized to than the perforation 141 in substrate 140 more
Greatly.For example, in some embodiments, substrate 140 is sufficiently thick with the self-supporting suspension (suspension above perforation 153
Over) so that substrate 140 substantially will not be bent or be deformed due to suction 142.As depicted in figure 15, according to some implementations
Example, perforation 153 are sized to smaller than the perforation 141 in substrate 140.Any of supporting member 152 can make supporting member 152
The configuration for providing the perforation 141 of suction 142 to substrate 140 is expectable.
Component 143 comprising substrate 140 and semiconductor particle 70 can be detached from from supporting member 152.It closes as described
In being detached from supporting member 72, " disengaging " may include supporting member 152 being separated from component 143 or in contrast (from support structure
Separation assembly 143 on part 152).For example, as depicted in figure 15, lifter 154 can be used for when component 143 is towards lifter
154 gently rise component 143 when crossing is detached from from supporting member 152.
According to some embodiments, supporting member 152 can be removed with form of chips (in pieces), not as full wafer.
For example, in some related embodiments, supporting member 152 can be divided into several if semiconductor bottom plate is for making multiple devices
The subregion of component 143 or region are detached from, this is related using form with semiconductor bottom plate.According to the disengaging of supporting member 152
The dynamics of form and/or suction or pressure gradient-force 142, suction 142 can remove before discharging supporting member 152.According to
Fritter can be scratched or are divided into some embodiments, component 143 according to those subregions or region, this can be carried out in situ.
For convenience of disengaging, before providing substrate 140 to supporting member 152, supporting member 152, which can be used, promotes disengaging
Substance or ingredient (also referred herein as " release agent ") processing.For example, supporting member 152 can be coated by inviscid coating, example
Such as the polytetrafluoroethylene (PTFE) of Du Pont(E.I.du Pont de Nemours)。
Further, in some embodiments, heat treatment can be used that supporting member 152 is such as heated or cooled, to utilize group
The different rates that thermally expand between part 143 and supporting member 152 separate them.
As in first group of embodiment with regard to described in Fig. 7 a to 13, second group of embodiment mentions relative to prior technique
Many benefits are supplied.In some first technical methods, semiconductor particle is fully lined bottom encirclement, and therefore needs using photoetching
Or other technologies carefully remove enough substrates to appear semiconductor particle, and do not damage any semiconductor particle.It is described
The embodiment of method and system by ensure semiconductor particle at least part be not adhere on substrate or by substrate cover and keep away
This additional step is exempted from.Therefore, method and system described in second group of embodiment can make to make relative to prior technique
Make cost reduction.
Directly pay attention to Figure 16, depicts the method 1600 of production semiconductor bottom plate according to non-limiting embodiments.For auxiliary
Illustration method 1600, it is assumed that method 1600 is executed using element described in Figure 14 a to 15.Further, method 1600 is subsequent
Discussion will lead to described element is further understood from.It should be understood, however, that the element and/or method of Figure 14 a to 15
1600 be variable, it is not necessary to completely with it is as described herein consistent together with the mode being bonded to each other, and it is this kind of variation herein
Within the scope of embodiment.
It is emphasized that method 1600 need not be executed accurately in the indicated order, unless otherwise stated；Similarly various block diagrams can
It is executed in order with executing parallel；Because the element of the method 1600 can see " block diagram " as rather than " step " herein.
At block diagram 1605, the substrate 140 with the perforation 141 under suction 142 is provided.As described above, according to some
Embodiment, substrate 140 can be provided to supporting member 152, and the configuration of supporting member 152 is to provide suction 142 to perforation 141.
At block diagram 1610, the setting of semiconductor particle 70 is in perforation 141 so as to part 145 (alternatively, part 146)
It is prominent from substrate 140.Semiconductor particle 70 is retained in perforation 141 by suction 142.According to some embodiments, 140 quilt of substrate
Scan and/or check to ensure that semiconductor particle 70a, 70b, 70c, 70d, 70e and 70f occupy respectively perforation 141a, 141b,
141c, 141d, 141e and 141f.
At block diagram 1615, substrate 140 is adhered on semiconductor particle 70 to form substrate 140 and semiconductor particle 70
Component 143.According to some embodiments, adhering to substrate 140 to semiconductor particle 70 includes at least following first, applying
(applying) adhesive extremely perforation 141；Apply (applying) adhesive to semiconductor particle 70；Heat substrate 140；Solidification
Substrate 140；And oxide layer on semiconductor particle 70 is merged to substrate 140.
At block diagram 1620, the part 145 (alternatively or additionally, part 146) of semiconductor particle 70 carries out flat
Change.
Directly pay attention to Figure 17, depict the system 1700 of production semiconductor bottom plate according to non-limiting embodiments, wherein coming
Similar element from Fig. 7 a to 15 is endowed similar label.To help to understand, system 1700 just makes semiconductor bottom plate 147
It is described.
(work) is carried out from left to right, there is the substrate 140 of perforation 141 to be supplied to supporting member, supporting member includes more
Hole conveyer belt (perforated conveyor) 1702.Perforated conveyor belt 1702 is operatively coupled to vacuum plant 1703, matches
It sets to provide suction 142 to perforation 141.
According to the embodiment described in Figure 17, semiconductor particle 70 is arranged on substrate 140 through siphon pipe 1302, siphon pipe
It is bound to a hopper (not shown).The setting of semiconductor particle 70 retains in perforation 141 and by suction 142, so that part 146
It is prominent from substrate.According to some embodiments, then semiconductor particle 70 is arranged on substrate 140 from suction in a container or heap,
And enter perforation 141.
System 1700 further includes a device, for adhering to substrate 140 to semiconductor particle 70 with formed substrate 140 and
The component 143 of semiconductor particle 70.As depicted in figure 17, system 1700 includes that heating lamp 1704 makes to heat substrate 1740
Substrate 140 is melted and is adhered on semiconductor particle.According to some embodiments, adhere on substrate 140 to semiconductor particle 70
Device includes a sprayer (a sprayer).For example, according to some embodiments, with a substance spray substrate 140 to promote substrate
140 with the adherency of semiconductor particle 70.
System 1700 further includes a planarizer, grinder 1307, for planarizing the portion of semiconductor particle 70
Divide 145.According to the embodiment described in Figure 17, component 143 passes across conveyer belt 1702 below grinder 1307, to be formed
Semiconductor bottom plate 147.
System 1700 further includes a release unit, for being detached from component 143 at supporting member, conveyer belt 1702.
According to the embodiment described in Figure 17, release unit includes lifter (lifter) 1705, when semiconductor bottom plate 147 is towards lifting
When device 1705 passes through supporting member 1702, lifter lightly rises semiconductor bottom plate 147 and leaves supporting member 1702.
Method, system and device described herein can provide a simple, expansible and cost-effective mode to make half
Conductor substrate.These semiconductor bottom plates can be used for needing in the various applications of semiconductor support, such as display and solar-electricity
Pond plate.Described method, system and device can be particularly advantageous relative to the biggish ground of semiconductor size in size of devices.
It, can according to method and system described in some embodiments as a kind of expansible mode for making semiconductor bottom plate
For making the semiconductor bottom plate including single pixel to the semiconductor bottom plate comprising thousands of pixels.Further, as described above,
Some embodiments can make multiple, different device (multiple, disparate from identical semiconductor bottom plate
Devices), by modification semiconductor particle in entire sealing material layer or one or more drop points of substrate layer
(placement) and the ingredient of sealing material layer and/or substrate layer and or the subregion designed according to determining device or region
Substrate.The semiconductor bottom plate of production can then be divided into fritter or be distributed according to those subregions and region.This to make
There is flexibility and adaptability, which results in the reductions of cost of manufacture in journey.
Further, as described above, the method and system can make to cut semiconductor bottom plate for other purposes as transported
It is possibly realized.For example, the ingredient and form of sealing material layer can formulate (created) to promote the flexible of semiconductor bottom plate
Property.According to some embodiments, this flexibility may make semiconductor bottom plate to be stored and/or transported with rolled form.With it is large-scale,
The semiconductor bottom plate of hard is compared, the semiconductor bottom plate of curling be likely to occupy lesser space and do not need particularly to store or
Transport device.Therefore, embodiment can reduce storage and transportation cost.
Further, for second group of embodiment, since semiconductor particle passes through supporting member (such as supporting member 72)
Or substrate (such as substrate 140) is positioned, there is no need to formal matrix (a formal matrix) or grid (grid) Lai Dingwei
The semiconductor particle.
As above statement, for second group of embodiment, due to semiconductor particle and is not completely embedded into or is supported material (example
Such as sealing material layer 76, substrate 140) it surrounds, therefore some this materials need not be removed to appear a part of semiconductor particle
For further making.This can also reduce cost of manufacture.Further, since at least part of semiconductor particle is from partly leading
It is prominent at body bottom plate, therefore backing material is not necessarily and sees semiconductor particle and be set as transparent material.
Those skilled in the art still have more alternative embodiments and modification possible for expected, and above example only shows one
Or multiple embodiments.Therefore, protection scope is only limited by claim appended below.
Claims (22)
1. a kind of method for making semiconductor bottom plate characterized by comprising
Semiconductor particle is set in the perforation of supporting member, so that a part of semiconductor particle is prominent from supporting member；
Apply another part of suction to the semiconductor particle, to keep the semiconductor particle in the perforation；
Sealing material layer is set on the supporting member, so that described a part of the semiconductor particle is by the sealing material
Bed of material covering；
The supporting member is removed to appear the component of the semiconductor particle and the sealing material layer；And
Planarize described another part of the semiconductor particle.
2. the method according to claim 1, wherein described another part is positioned at following first, one is parallel to institute
State the plane and a plane coplanar with the sealing material layer of sealing material layer.
3. the method according to claim 1, wherein planarization includes chemically mechanical polishing CMP.
4. the method according to claim 1, wherein be arranged the sealing material layer include it is at least following first,
The sealing material is sprayed on the supporting member, topples over the sealing material on the supporting member, is unfolded described close
Closure material rolls the sealing material on the supporting member on the supporting member, suppresses the sealing material in institute
It states on supporting member, sealing material layer described in the supporting member described in the sealing material electrostatic coating and vacuum forming is in institute
It states on supporting member.
5. the method according to claim 1, wherein the sealing material layer includes at least following first, fluid,
Powder and thin slice.
6. the method according to claim 1, wherein the sealing material layer includes at least following first, glass,
Plastics and photocuring cement.
7. the method according to claim 1, wherein the method further includes:
Before removing operation, apply substrate material layer on the sealing material layer.
8. the method according to the description of claim 7 is characterized in that the component further includes the substrate material layer.
9. the method according to the description of claim 7 is characterized in that the substrate material layer includes at least following first, glass,
And plastics.
10. the method according to the description of claim 7 is characterized in that the substrate material layer includes: flexible glass.
11. the method according to claim 1, wherein the method further includes: remove institute after planarization
State sealing material layer.
12. the method according to claim 1, wherein wherein the planarization includes planarizing the semiconductor
Described another part of the semiconductor particle in the component of particle and the sealing material layer.
13. a kind of system for making semiconductor bottom plate characterized by comprising
Supporting member with perforation, wherein the perforation size is set as can receive semiconductor particle, so that the semiconductor grain
A part of son is prominent from the supporting member；
Suction unit is operably coupled to the supporting member, for applying suction in another portion of the semiconductor particle
Divide to keep the semiconductor particle in perforation；
Applicator, for applying sealing material layer in the supporting member, so that described a part of the semiconductor particle
It is covered by the sealing material layer；And
Planarizer, for removing the supporting member to expose the group of the semiconductor particle and the sealing material layer
Another part of the semiconductor particle is planarized after part.
14. a kind of method for making semiconductor bottom plate characterized by comprising
One substrate with perforation is provided；
The supporting member for being configured to apply suction to the perforation is provided, the supporting member includes one in conveyer belt and roller
It is a or multiple；
Semiconductor particle is provided；
Semiconductor particle is placed on substrate；
Substrate described in mechanical oscillation and the semiconductor particle are to be arranged semiconductor particle in the perforation, so that described partly lead
A part of body particle is prominent from the substrate, and the semiconductor particle is maintained in the perforation by the suction；
After mechanical oscillation, the substrate is adhered to the semiconductor particle to form the substrate and the semiconductor particle
Component；And
After adhesion, described a part of the semiconductor particle is planarized.
15. according to the method for claim 14, which is characterized in that the flattened section is located at following first, one is parallel
In the plane of the substrate of the component and one with the plane of the substrate co-planar of the component.
16. according to the method for claim 14, which is characterized in that the planarization process includes chemically mechanical polishing CMP.
17. according to the method for claim 14, which is characterized in that adhering to the substrate to the semiconductor particle includes extremely
First, applying adhesive to the perforation below few；Apply adhesive to the semiconductor particle；Heat the substrate；Solidification
The substrate；And the oxide layer on the fusion semiconductor particle is to the substrate.
18. according to the method for claim 14, which is characterized in that the method further includes: from the supporting member
It is upper to remove the component.
19. according to the method for claim 14, which is characterized in that the semiconductor particle includes silicon ball.
20. according to the method for claim 14, which is characterized in that the substrate includes at least following first, glass and modeling
Material.
21. according to the method for claim 14, which is characterized in that the substrate includes: flexible glass.
22. according to the method for claim 14, which is characterized in that the method further includes: planarization is moved back except institute
State substrate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/019131 | 2013-09-05 | ||
| US14/019,131 US9209019B2 (en) | 2013-09-05 | 2013-09-05 | Method and system for manufacturing a semi-conducting backplane |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104576404A CN104576404A (en) | 2015-04-29 |
| CN104576404B true CN104576404B (en) | 2019-08-09 |
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| CN201410452718.4A Active CN104576404B (en) | 2013-09-05 | 2014-09-05 | A kind of method and system making semiconductor bottom plate |
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|---|---|
| US (1) | US9209019B2 (en) |
| EP (1) | EP2846354B1 (en) |
| JP (1) | JP6362480B2 (en) |
| CN (1) | CN104576404B (en) |
| HK (1) | HK1207207A1 (en) |
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| WO2015065320A1 (en) | 2013-10-28 | 2015-05-07 | Hewlett-Packard Development Company, L.P. | Encapsulating a bonded wire with low profile encapsulation |
| US9818903B2 (en) * | 2014-04-30 | 2017-11-14 | Sunpower Corporation | Bonds for solar cell metallization |
| EP2953158A3 (en) * | 2014-06-04 | 2016-02-17 | Diftek Lasers, Inc. | Method of fabricating crystalline island on substrate |
| US9843024B2 (en) * | 2014-12-03 | 2017-12-12 | Universal Display Corporation | Methods for fabricating OLEDs |
| EP3244453A1 (en) * | 2015-10-09 | 2017-11-15 | Diftek Lasers, Inc. | An electronic device and method of making thereof |
| US10312310B2 (en) | 2016-01-19 | 2019-06-04 | Diftek Lasers, Inc. | OLED display and method of fabrication thereof |
| US10199255B2 (en) * | 2016-03-10 | 2019-02-05 | Infineon Technologioes AG | Method for providing a planarizable workpiece support, a workpiece planarization arrangement, and a chuck |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104576404A (en) | 2015-04-29 |
| EP2846354B1 (en) | 2019-05-22 |
| EP2846354A2 (en) | 2015-03-11 |
| EP2846354A3 (en) | 2015-08-12 |
| US20150064883A1 (en) | 2015-03-05 |
| HK1207207A1 (en) | 2016-01-22 |
| JP2015053481A (en) | 2015-03-19 |
| US9209019B2 (en) | 2015-12-08 |
| JP6362480B2 (en) | 2018-07-25 |
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