CN104576369A - Method for manufacturing semiconductor apparatus - Google Patents
Method for manufacturing semiconductor apparatus Download PDFInfo
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- CN104576369A CN104576369A CN201310470995.3A CN201310470995A CN104576369A CN 104576369 A CN104576369 A CN 104576369A CN 201310470995 A CN201310470995 A CN 201310470995A CN 104576369 A CN104576369 A CN 104576369A
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- fin
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Abstract
The invention relates to a method for manufacturing a semiconductor apparatus. The method comprises the following steps: providing a semiconductor substrate; forming a sacrifice material layer on the semiconductor substrate; patterning the sacrifice material layer to form a plurality of virtual patterns, wherein the spacing distance among part of virtual patterns is greater than the width of a fin to be formed but less than 2 time of width of the fin to be formed; forming side walls on two sides of each virtual pattern; removing the virtual patterns and retaining the side walls on two sides of each virtual pattern so as to form a virtual fin; etching the semiconductor substrate by taking the virtual fin as a mask so as to form the fin. The width of the fin can be adjusted within the range of one or two side walls, so that horizontal adjusting space of a SRAM (static random access memory) memory unit in a transistor apparatus is increased, the static noise margin of the SARM is improved, the apparatus performance fluctuation caused by width change of the fin is reduced, mismatching of the apparatus is improved and the yield window is enhanced, and therefore, the reduction of the memory unit area is further facilitated.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly, the present invention relates to the manufacture method of a kind of FinFET (FinFET).
Background technology
The device development of a small amount of interconnection that integrated circuit (IC) has made from single silicon becomes millions of device.Current I C provides and far exceedes former conceptive performance and complexity.In order to realize the improvement of complexity and current densities (namely can be packaged into the device count on given chip area), the size of minimum device feature, also referred to as device " geometry ", become less along with the technological evolvement of each generation IC.Be less than the feature of 1/4th microns to make semiconductor device with span now.
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly realized with the speed improving it by the characteristic size constantly reducing integrated circuit (IC)-components.At present, because in pursuit high device density, high-performance and low cost, semi-conductor industry has had advanced to nanometer technology process node, the manufacture of semiconductor device is subject to the restriction of the various physics limit of device.For 22nm and more advanced semiconductor technology, along with the conflict constantly reduced from device performance and physics limit of cmos device characteristic size impels three dimensional design as the development of FinFET (FinFET).Relative to existing planar transistor, described FinFET has more superior performance in raceway groove control and reduction short-channel effect etc.; Planar gate is arranged at above described raceway groove, and gate loop is arranged around described fin (fin) described in FinFET, and therefore can carry out the electrostatic field control gate dielectric layer from three faces, the performance in electric field controls is also more outstanding.
In the semiconductor technology of existing making FinFET, adopt double-deck figure (SADP) technique of autoregistration to form fin, so the width of fin is determined by the sidewall thickness deposited, the technique of this making FinFET can only obtain a kind of width of fin, as Figure 1A-1E is depicted as the process generalized section preparing FinFET according to prior art, in figure ia, form pad oxide 101, pad nitride layer 102, hard mask layer 103 on a semiconductor substrate 100 successively and there is the sacrificial material layer 104 of dummy pattern; As shown in Figure 1B, sacrificial material layer 104 forms side wall layer 105; As shown in Figure 1 C, side wall layer 105 described in patterning, to form virtual fin 106, removes sacrificial material layer 104; As shown in figure ip, form the mask layer 107 of patterning on a semiconductor substrate, to define FinFET region; As referring to figure 1e, unnecessary virtual fin (comprising the virtual fin unwanted with the cut-out of Y-direction that the place to go of X-direction is unnecessary) is removed according to mask layer 107, to form the virtual fin 108 of the final fin structure of definition, form fin with virtual fin 108 for mask is used for subsequent etching.Interval S between the dummy pattern of described sacrificial material layer 104 is width and fin pitch width 201 sum of two fins 200, as shown in Figure 2.Planar MOSFET (mos field effect transistor) can realize the continuously adjustabe of channel width by the transistor of design different in width, thus be easy to adjusting device performance and reach expection, but, be difficult to realize for FinFET, FinFET can only by changing parallel fin (Fin) quantity to realize discrete channel width.Especially, for highdensity SRAM(static random access memory) being faced with this transistor width can not continuously adjustable Tough questions, the important method that tradition improves high density SRAM performance (reading ability, write capability, data holding ability and static noise margin (SNM) etc.) be that optimization pull-up (pull up) transistor, drop-down (pull down) transistor and pass gate(access) channel width of transistor.
At present, in order to meet the development of semiconductor technology, propose on the hard mask layer of patterning, add another mask layer method to form the dummy fins chip architecture of different in width, another mask layer added defines the dummy fins chip architecture of other width for avoiding the region below it to be etched away as barrier layer in follow-up etching process on hard mask layer, and this method can form the FinFET with any fin width.But, this method increasing complexity and the process costs of technique, especially for regulating fin width within the scope of sidewall to two sidewall, needing the high-grade mask plate that cost is very high, and particularly important to SRAM device adjustment within the scope of this.In current FinFET processing procedure, pull-up (pull up) transistor of SRAM memory cell, drop-down (pull down) transistor and pass gate(access) transistor adopts the fin in parallel of varying number to realize, but this method adjustment is interval smaller, be unfavorable for the performance optimization of SRAM, and the interval between fin in parallel limits reducing further of cellar area.Also someone proposes and carries out eat-backing thus realizing the adjustment of channel width in the vertical direction in various degree by increasing the STI of a mask light shield to pull-up (pull up) transistor, drop-down (pull down) transistor and pass gate crystalline substance (access) body pipe place, but this method also increases process complexity and extra cost.
Therefore, propose the manufacture method that a kind of formation has the FinFET of different fin width, there is high-performance and the semiconductor device with excellent isolation structure to obtain.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to effectively solve the problem, the present invention proposes a kind of method making semiconductor device, comprising: Semiconductor substrate is provided; Form sacrificial material layer on the semiconductor substrate; Sacrificial material layer described in patterning, to form multiple dummy pattern, the interval width wherein between partial virtual pattern is greater than the width planning the fin formed and is less than or equal to 2 times that plan the fin width formed; Sidewall is formed in the both sides of described dummy pattern; Remove described dummy pattern and retain the described sidewall being positioned at described dummy pattern both sides, to form virtual fin; With described virtual fin for Semiconductor substrate described in mask etch, to form described fin.
Preferably, the step of the described virtual fin of removal part after being also included in the described virtual fin of formation.
Preferably, photoresist layer is adopted to remove the described virtual fin of part as mask.
Preferably, described photoresist layer is used for defining FinFET region.
Preferably, described Semiconductor substrate is body silicon or SOI substrate.
Preferably, be also formed with hard mask layer between described Semiconductor substrate and described sacrificial material layer, the material of described hard mask layer is nitride.
Preferably, atom layer deposition process is adopted to form described sidewall.
The present invention proposes the manufacture method that a kind of formation has the FinFET of different fin width, a SADP technique is adopted not adopt any additional mask layers to obtain the fin of different in width, the width of fin can regulate within the scope of sidewall to two sidewall, the width increasing fin can obtain larger PN junction area and the width of active area resistance, within the scope of sidewall to two sidewall continuously adjustable fin width condition under, contribute to increasing SRAM memory cell in the adjustment space of transistor device level, improve the static noise margin (SNM) of SRAM, reduce fin width and change the device performance fluctuation caused, improve the mismatch of device and promote yield window (yield window), be conducive to reducing memory cell area further.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1E is the process generalized section preparing FinFET according to prior art;
Fig. 2 is the schematic diagram at the dummy pattern interval of preparing FinFET according to prior art;
Fig. 3 A-3E is the correlated process generalized section preparing FinFET according to an embodiment of the invention;
Fig. 4 is the schematic diagram at the dummy pattern interval of preparing FinFET according to an embodiment of the invention;
Fig. 5 is the process chart preparing FinFET according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, to illustrate the method for the present invention.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
Below in conjunction with Fig. 3 A-3E, the preparation method of semiconductor device of the present invention is described in detail.As shown in Figure 3A, provide Semiconductor substrate 300, in the substrate 300 of described semiconductor, be formed with trap;
Described Semiconductor substrate can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator, preferred body silicon and SOI substrate.In addition, Semiconductor substrate can be defined active area.
In described Semiconductor substrate, be formed with trap, described in an embodiment of the present invention, substrate selects P type substrate, and particularly, the P type substrate that those skilled in the art select this area conventional, then forms N trap and P trap over the substrate.
In an embodiment of the present invention, described Semiconductor substrate 300 is body silicon substrate.Described Semiconductor substrate 300 comprises FinFET regional peace face device area.Semiconductor substrate 300 is formed pad oxide skin(coating) 301, and the thickness range of pad oxide skin(coating) is 10 dust to 100 dusts.
Pad oxide skin(coating) 301 is formed pad nitride 302, the thickness range of nitride layer is 100 dust to 1500 dusts, the material preferred nitrogen SiClx of nitride layer, the material of sacrificial material layer can be not limited to nitride for other any applicable material, chemical vapour deposition technique (CVD) can be adopted, as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (LTCVD), plasma activated chemical vapour deposition (PECVD), also such as sputter and physical vapour deposition (PVD) (PVD) etc. can be used to form nitride layer.
Pad nitride layer 302 forms hard mask layer 303, the material of hard mask layer 303 can for nitride, nitrogen oxide, be rich in the oxide of silicon, fluorine-containing silicon dioxide (FSG), the material that the silica of carbon doping etc. are such as similar, as the hard mask layer in subsequent etching process.Hard mask layer can use and include but not limited to: the method for process for chemical vapor deposition of materials with via and physical vapor deposition methods is formed.The wherein preferred silicon dioxide of the material of hard mask layer, the thickness of hard mask layer is 100 dust to 1000 dusts.
Hard mask layer 303 is formed sacrificial material layer 304, the material of sacrificial material layer 304 can for APF, amorphous silicon (amorphous Silicon), polysilicon, nitride, nitrogen oxide, be rich in the oxide of silicon, fluorine-containing silicon dioxide (FSG), the material that the silica of carbon doping etc. are such as similar, sacrificial material layer 304 is APF(Advanced Patterning Film preferably) layer, the material of described APF layer is amorphous carbon, as the hard mask layer in subsequent etching process.Hard mask layer can use and include but not limited to: the method for process for chemical vapor deposition of materials with via and physical vapor deposition methods is formed.
As an embodiment of the present invention, sacrificial material layer 304 forms the photoresist layer of dielectric antireflective coatings (DARC), bottom antireflective coating (BARC) and patterning successively.
Then by lithography mask version by the Graphic transitions of dummy pattern in sacrificial material layer 304, using photoresist layer as mask etching sacrificial material layer 304, to form the sacrificial material layer 304 with multiple dummy pattern, interval width wherein between partial virtual pattern is greater than the width planning the fin formed and is less than or equal to 2 times that plan the fin width formed, and removes described photoresist layer.Wherein the thickness of sacrificial material layer 304 is 50 dust to 200 dusts.
Then, the sacrificial material layer 304 with dummy pattern forms side wall layer 305, concrete, sidewall is formed in the both sides of the dummy pattern of sacrificial material layer 304, by the interval between adjustment dummy pattern to form the fin of different in width, side wall layer wherein can be adopted to fill interval between described dummy pattern, and as shown in Figure 3 B, described sidewall can be a kind of in silica, silicon nitride, silicon oxynitride or their combinations are formed.As an optimal enforcement mode of the present embodiment, described side-wall material be silica or silicon nitride or other are suitable materials, the deposition technique by low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition (PECVD) and ald (ALD) or other advanced person is formed.Preferred employing ald (ALD).
Then, as shown in Figure 3 C, hard mask layer 303 forms virtual fin 306.Virtual fin 306 is for defining width, the length and position etc. of fin.In an embodiment of the present invention, adopt the sacrificial material layer 304 that the mask plate of a patterning removes patterning and the side wall layer be positioned in sacrificial material layer 304, then, the mask plate of another patterning is adopted to remove the end of side wall layer, be equivalent to remove the side wall layer covered on hard mask layer 303, final reservation is arranged in the sidewall of the dummy pattern both sides of sacrificial material layer 304.
In an embodiment of the present invention, with the mask plate of patterning for mask, passing into CF
4and CHF
3etching condition under, described hard mask layer and side wall layer are etched, in this step described etching pressure: 50-150mTorr; Power: 300-800W; Time: 5-15s; Wherein gas flow: CF
4, 10-30sccm; CHF
3, 10-30sccm, it should be noted that above-mentioned engraving method is only exemplary, does not limit to and the method, and those skilled in the art can also select other conventional methods.
As shown in Figure 3 D, virtual fin 306 and hard mask layer 303 form the hard mask layer 307 of patterning, hard membrane layer 307 is for scheduling FinFET region, the preferred photoresist of material of hard mask layer 307.
Hard mask layer can comprise any one of several mask materials usually, includes but not limited to: hard mask material and photoresist mask material.Preferably, mask layer comprises photoresist mask material.Photoresist mask material can comprise the Other substrate materials be selected from the group comprising positive-tone photo glue material, negative photo glue material and mixing Other substrate materials.Usually, hard mask mask layer comprises and has thickness from about 500 to the positive-tone photo glue material of about 5000 dusts or negative photo glue material.
In an embodiment of the present invention, hard mask layer 307 is photoresist layer, adopts photoetching process after the steps such as exposure imaging, form the photoresist layer 307 of patterning.The photoresist layer 307 of patterning is for defining FinFET region.
As shown in FIGURE 3 E, with hard mask layer 307 for mask removes virtual fin unnecessary in virtual fin 306, to form the virtual fin 308 of final definition fin structure, virtual fin 308 is for defining the width of the fin in FinFET region, length and position etc.With virtual fin 308 for mask etches described hard mask layer 303, pad nitride layer 302, pad oxide 301 and Semiconductor substrate 300, successively to form fin structure in described Semiconductor substrate 300.
Both can adopt dry ecthing method that wet etch method also can be adopted to remove oxide skin(coating).Dry ecthing method can adopt the anisotropic etch process based on carbon fluoride gas.Wet etch method can adopt hydrofluoric acid solution, the hydrofluoric acid solution (diluted hydrofluoric acid (DHF)) of such as buffer oxide etch agent (buffer oxide etchant (BOE)) or dilution.Conventional dry etching technics, the such as combination in any of reactive ion etching, ion beam etching, plasma etching, laser ablation or these methods.Single lithographic method can be used, or also can use more than one lithographic method.
In of the present invention one particularly execution mode, using plasma etches, and etching gas can adopt the gas based on fluorine gas.Concrete, adopt lower radio-frequency (RF) energy also can produce low pressure and highdensity plasma gas to realize the dry etching of polysilicon.The etching gas adopted is based on fluorine-containing gas, and the flow of etching gas is: 100 ~ 200 cc/min (sccm); Reative cell internal pressure can be 30 ~ 50mTorr, and the time of etching is 10 ~ 15 seconds, and power is 50 ~ 100W, and bias power is 0W.
The method of making semiconductor device of the present invention can be applied to body FinFET(bulk FinFET) semiconductor device and silicon-on-insulator (SOI) FinFET semiconductor device.A SADP technique is adopted not adopt any additional mask layers to obtain the fin of different in width, the width of fin can regulate within the scope of sidewall to two sidewall, the width increasing fin can obtain larger PN junction area and the width of active area resistance, within the scope of sidewall to two sidewall continuously adjustable fin width condition under, contribute to increasing SRAM memory cell in the adjustment space of transistor device level, improve the static noise margin (SNM) of SRAM, reduce fin width and change the device performance fluctuation caused, improve the mismatch of device and promote yield window (yield window), be conducive to reducing memory cell area further.Wider fin width contributes to the area utilization efficiency improving diode, bipolar junction transistor.Adjustable fin width helps increases SRAM memory cell in the adjustment space of transistor device level, access by optimizing pull-up (pull up) transistor, drop-down (pull down) transistor and pass gate() channel width of transistor, this will improve SRAM static noise margin and yields, contribute to reducing further of bit location region (the bit cell) of SRAM simultaneously.
As shown in Figure 4, based on the final fin width 400 formed in FinFET region, have the sacrificial material layer 401 of dummy pattern, the interval S in sacrificial material layer 401 between dummy pattern is the final fin width formed.When adopting atom layer deposition process deposition to form sidewall, the sidewall of formation will be filled in the interval S of dummy pattern completely, to increase the width of formed fin 402.Interval width S wherein in sacrificial material layer 401 between part dummy pattern is greater than the width planning the fin formed and is less than or equal to 2 times that plan the fin width formed.
Fig. 5 is the preparation method of semiconductor device described in embodiment of the invention flow chart, comprises the following steps particularly:
Step 501 provides Semiconductor substrate, and form pad oxide, pad nitride layer, hard mask layer and sacrificial material layer on a semiconductor substrate successively, sacrificial material layer described in patterning, to form multiple dummy pattern in sacrificial material layer;
Step 502 forms side wall layer in the sacrificial material layer of patterning;
Step 503, patterned side parietal layer, to form sidewall in the both sides of dummy pattern, is removed described dummy pattern and is retained the described sidewall being positioned at described dummy pattern both sides, to form virtual fin;
Step 504 adopts photoresist layer as the described virtual fin of mask removal part;
The described Semiconductor substrate that step 505 is mask etching part with remaining virtual fin, to form fin in described Semiconductor substrate.
The present invention proposes the manufacture method that a kind of formation has the FinFET of different fin width, a SADP technique is adopted not adopt any additional mask layers to obtain the fin of different in width, the width of fin can regulate within the scope of sidewall to two sidewall, the width increasing fin can obtain larger PN junction area and the width of active area resistance, within the scope of sidewall to two sidewall continuously adjustable fin width condition under, contribute to increasing SRAM memory cell in the adjustment space of transistor device level, improve the static noise margin (SNM) of SRAM, reduce fin width and change the device performance fluctuation caused, improve the mismatch of device and promote yield window (yield window), be conducive to reducing memory cell area further.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.
Claims (7)
1. make a method for semiconductor device, comprising:
Semiconductor substrate is provided;
Form sacrificial material layer on the semiconductor substrate;
Sacrificial material layer described in patterning, to form multiple dummy pattern, the interval width wherein between partial virtual pattern is greater than the width planning the fin formed and is less than or equal to 2 times that plan the fin width formed;
Sidewall is formed in the both sides of described dummy pattern;
Remove described dummy pattern and retain the described sidewall being positioned at described dummy pattern both sides, to form virtual fin;
With described virtual fin for Semiconductor substrate described in mask etch, to form described fin.
2. the method as requested described in 1, is characterized in that, is also included in the step of the described virtual fin of removal part after forming described virtual fin.
3. the method as requested described in 2, is characterized in that, adopts photoresist layer to remove the described virtual fin of part as mask.
4. the method as requested described in 3, is characterized in that, described photoresist layer is used for defining FinFET region.
5. the method as requested described in 1, is characterized in that, described Semiconductor substrate is body silicon or SOI substrate.
6. the method as requested described in 1, is characterized in that, is also formed with hard mask layer between described Semiconductor substrate and described sacrificial material layer, and the material of described hard mask layer is nitride.
7. the method as requested described in 1, is characterized in that, adopts atom layer deposition process to form described sidewall.
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| CN201310470995.3A CN104576369A (en) | 2013-10-10 | 2013-10-10 | Method for manufacturing semiconductor apparatus |
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| CN201310470995.3A CN104576369A (en) | 2013-10-10 | 2013-10-10 | Method for manufacturing semiconductor apparatus |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148451A (en) * | 2017-06-27 | 2019-01-04 | 联华电子股份有限公司 | SRAM cell array and forming method thereof |
| CN109671778A (en) * | 2017-10-16 | 2019-04-23 | 中芯国际集成电路制造(上海)有限公司 | Fin semiconductor devices and forming method thereof |
| CN111095481A (en) * | 2017-09-03 | 2020-05-01 | 应用材料公司 | Conformal halogen doping in 3D structures using conformal dopant film deposition |
| CN113488474A (en) * | 2021-07-15 | 2021-10-08 | 广东省大湾区集成电路与系统应用研究院 | High-density static random access memory bit cell structure and process method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006351975A (en) * | 2005-06-20 | 2006-12-28 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US20070161251A1 (en) * | 2005-03-15 | 2007-07-12 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
| US20070249170A1 (en) * | 2006-04-25 | 2007-10-25 | David Kewley | Process for improving critical dimension uniformity of integrated circuit arrays |
| US20090093121A1 (en) * | 2007-10-04 | 2009-04-09 | Hynix Semiconductor Inc. | Method for Fabricating a Fine Pattern |
| JP2011009296A (en) * | 2009-06-23 | 2011-01-13 | Panasonic Corp | Semiconductor device and method for manufacturing the same |
-
2013
- 2013-10-10 CN CN201310470995.3A patent/CN104576369A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070161251A1 (en) * | 2005-03-15 | 2007-07-12 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
| JP2006351975A (en) * | 2005-06-20 | 2006-12-28 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US20070249170A1 (en) * | 2006-04-25 | 2007-10-25 | David Kewley | Process for improving critical dimension uniformity of integrated circuit arrays |
| US20090093121A1 (en) * | 2007-10-04 | 2009-04-09 | Hynix Semiconductor Inc. | Method for Fabricating a Fine Pattern |
| JP2011009296A (en) * | 2009-06-23 | 2011-01-13 | Panasonic Corp | Semiconductor device and method for manufacturing the same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109148451A (en) * | 2017-06-27 | 2019-01-04 | 联华电子股份有限公司 | SRAM cell array and forming method thereof |
| CN109148451B (en) * | 2017-06-27 | 2021-09-07 | 联华电子股份有限公司 | Static random access memory unit array and forming method thereof |
| CN111095481A (en) * | 2017-09-03 | 2020-05-01 | 应用材料公司 | Conformal halogen doping in 3D structures using conformal dopant film deposition |
| CN111095481B (en) * | 2017-09-03 | 2024-01-02 | 应用材料公司 | Conformal halogen doping in 3D structures using conformal dopant films deposition |
| CN109671778A (en) * | 2017-10-16 | 2019-04-23 | 中芯国际集成电路制造(上海)有限公司 | Fin semiconductor devices and forming method thereof |
| CN109671778B (en) * | 2017-10-16 | 2022-01-11 | 中芯国际集成电路制造(上海)有限公司 | Fin type semiconductor device and forming method thereof |
| CN113488474A (en) * | 2021-07-15 | 2021-10-08 | 广东省大湾区集成电路与系统应用研究院 | High-density static random access memory bit cell structure and process method thereof |
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Application publication date: 20150429 |