CN104573157A - Method and device for checking printed circuit - Google Patents
Method and device for checking printed circuit Download PDFInfo
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- CN104573157A CN104573157A CN201310507650.0A CN201310507650A CN104573157A CN 104573157 A CN104573157 A CN 104573157A CN 201310507650 A CN201310507650 A CN 201310507650A CN 104573157 A CN104573157 A CN 104573157A
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Abstract
The invention relates to a method and a device for checking a printed circuit. The method comprises the following steps of firstly, obtaining the layout of the circuit, wherein the layout records at least one circuit element and at least one clock signal line, the circuit element is correspondingly provided with a welding pad, and the welding pad corresponds to a first range on the layout of the circuit; then, setting a preset distance, expanding the first range into a second range on the layout of the circuit according to the preset distance; finally, judging whether the clock signal line passes through the second range or not; when the clock signal line passes through the second range, modifying the layout of the circuit, so as to prevent the clock signal line from passing through the second range. The method and the device for checking the printed circuit have the advantages that the route of the clock signal is automatically checked and modified, and the interference by the signals of other circuit elements is reduced. The device comprises a layout module, a setting module and a checking module, wherein the setting module is coupled with the layout module, and the checking module is coupled with the layout module and the setting module.
Description
Technical field
The present invention relates to the inspection that printed circuit board (PCB) (printed circuit board) designs, particularly a kind of inspection method about clock pulse (clock) signal wire and device.
Background technology
Clock signal on printed circuit board (PCB) has synchronous function.When clock signal input arrives, the change output state that relevant trigger side is complied with, makes the circuit component of rear class be able to synchronous operation.Clock signal itself is very responsive, need to avoid the signal disturbing by other circuit components in circuit layout, but existing electric design automation (electronic design automation, be called for short EDA) put forth effort on the Design of Signal reducing circuit-board processes problem and mistake, the ELIMINATION OF ITS INTERFERENCE not to clock signal more.If with artificial visual inspection, then spacious day is time-consuming again, easily flows and dredges in hundred close one.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of P.e.c. inspection method and a kind of P.e.c. testing fixture, can self-verifying revise clock signal cabling, reduces the signal disturbing from other circuit components.
To achieve these goals, the invention provides a kind of P.e.c. inspection method, wherein, comprise following steps:
Obtain a circuit layout, this circuit layout records at least one circuit component and at least one clock signal line, the corresponding at least one weld pad of this circuit component, and this weld pad is to should upper one first scope of circuit layout;
Set a preset pitch;
According to this preset pitch, be upper one second scope of this circuit layout by the expansion of this first scope; And
Judge whether this clock signal line passes through this second scope.
Above-mentioned P.e.c. inspection method, wherein, when this clock signal line is through this second scope, revises this circuit layout, makes this clock signal line without this second scope.
Above-mentioned P.e.c. inspection method, wherein, also comprises:
This circuit layout at least part of after display update.
Above-mentioned P.e.c. inspection method, wherein, when this clock signal line is through this second scope, records the position of this clock signal line in this second scope.
Above-mentioned P.e.c. inspection method, wherein, also comprises:
This circuit layout of part of display this position contiguous.
In order to realize above-mentioned purpose better, present invention also offers a kind of P.e.c. testing fixture, wherein, comprising:
One layout modules, in order to provide a circuit layout, this circuit layout records at least one circuit component and at least one clock signal line, the corresponding at least one weld pad of this circuit component, and this weld pad is to should upper one first scope of circuit layout;
One setting module, couples this layout modules, in order to set a preset pitch, and according to this preset pitch, is upper one second scope of this circuit layout by the expansion of this first scope; And
One checking module, couples this layout modules and this setting module, in order to judge whether this clock signal line passes through this second scope.
Above-mentioned P.e.c. testing fixture, wherein, when this clock signal line is through this second scope, this checking module, also in order to revise this circuit layout, makes this clock signal line without this second scope.
Above-mentioned P.e.c. testing fixture, wherein, this layout modules is also in order to this circuit layout at least part of after display update.
Above-mentioned P.e.c. testing fixture, wherein, when this clock signal line is through this second scope, this checking module is also in order to record the position of this clock signal line in this second scope.
Above-mentioned P.e.c. testing fixture, wherein, this layout modules is also in order to show this circuit layout of part of this position contiguous.
Technique effect of the present invention is:
P.e.c. inspection method of the present invention and device operate in a circuit layout, can self-verifying revise clock signal cabling, reduce the signal disturbing from other circuit components.When clock pulse signal wire is through the second scope, the present invention also can record clock signal line certain position in the second scope, for subsequent treatment.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Accompanying drawing explanation
Fig. 1 is the high-order block diagram according to P.e.c. testing fixture in one embodiment of the invention;
Fig. 2 is the process flow diagram according to P.e.c. inspection method in another embodiment of the present invention.
Wherein, Reference numeral
1 P.e.c. testing fixture
11 layout modules
13 setting modules
15 checking modules
S21-S27 step
Embodiment
Below in conjunction with accompanying drawing, structural principle of the present invention and principle of work are described in detail:
Below detailed features of the present invention and advantage is described in embodiments in detail, its content is enough to make those skilled in the art understand technology contents of the present invention and implement according to this, and according to the content disclosed in this instructions, claim and accompanying drawing, those skilled in the art can understand the object and advantage that the present invention is correlated with easily.Following embodiment is further description viewpoint of the present invention, but non-to limit category of the present invention anyways.
Refer to Fig. 1.Fig. 1 is the high-order block diagram according to P.e.c. testing fixture in one embodiment of the invention.As shown in Figure 1, P.e.c. testing fixture 1 comprises layout modules 11, setting module 13 and checking module 15.Setting module 13 couples layout modules 11; Checking module 15 couples layout modules 11 and selects module 13.Layout modules 11 is for storing, providing and show a circuit layout.Circuit layout can be one or more file in electric design automation, at least records a circuit component and a clock signal line.Through the weldering of at least one weld pad on circuit boards, weld pad occupies one piece of region of circuit board to circuit component, the first scope namely in circuit layout.The area of the first scope and the size of weld pad.
Setting module 13 is for receiving and setting a preset pitch.P.e.c. testing fixture 1 can provide user's inputting interface to receive this preset pitch.Generally speaking, if draw circle in circuit layout centered by certain circuit component, then make this circuit component (and weld pad) institute band signal decay to radius engineering can being ignored degree outside circle and namely can be preset pitch.First scope also according to preset pitch, is expanded for the second scope in circuit layout by setting module 13.Suppose that the first scope is rectangle and has long l and wide w, make preset pitch be d, then the second scope can be for example in circuit layout centered by the first scope, the comparatively large rectangle of long l+2d, wide w+2d.
Checking module 15 is in order to judge that whether aforementioned clock signal line is through the second scope.When clock pulse signal wire is through the second scope, checking module 15 can attempt amendment aforementioned circuit layout, mobile clock signal line make without the second scope.Or checking module 15 can record clock signal line certain position in the second scope, for subsequent treatment.The clock signal line after moving just can be made not again by other circuit component signal disturbing owing to circuit board must there be enough idle spaces, modification circuits layout might not be feasible.Aforesaid position can be clock signal line enter or go out the second scope pass through a little, also can be certain point that clock signal line forms on line segment in the second scope.
Refer to Fig. 2.Fig. 2 is the process flow diagram according to P.e.c. inspection method in one embodiment of the invention.As shown in Figure 2, in step S21, layout modules 11 obtains circuit layout, and this circuit layout records at least one circuit component and at least one clock signal line, circuit component at least one weld pad corresponding, first scope of weld pad then in corresponding circuits layout.In step S23, setting module 13 sets a preset pitch, and expands the first scope for the second scope in circuit layout according to preset pitch.In step S25, checking module 15 judges that whether clock signal line is through the second scope.
In one embodiment, layout modules 11 can show the contiguous partial circuit layout of described circuit component after step S21.In one embodiment, layout modules 11 can before checking module 15 moves clock signal line modification circuits layout, when or show the partial circuit layout of contiguous institute check circuit element afterwards, comprise display first scope and/or the second scope.In one embodiment, when checking module 15 only records certain position in the second scope of clock signal line and indicates this clock pulse signal wire to have a disturbed risk, layout modules 11 also can show the partial circuit layout of this position contiguous.
In sum, P.e.c. inspection method of the present invention and device can self-verifying circuit component (and weld pad) clock signals around, necessary and feasible time move clock signal cabling to reduce the signal disturbing from other circuit components.When clock pulse signal wire is through the second scope, the present invention also can record clock signal line certain position in the second scope, for subsequent treatment.
Certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection domain that all should belong to the claim appended by the present invention.
Claims (10)
1. a P.e.c. inspection method, is characterized in that, comprises following steps:
Obtain a circuit layout, this circuit layout records at least one circuit component and at least one clock signal line, the corresponding at least one weld pad of this circuit component, and this weld pad is to should upper one first scope of circuit layout;
Set a preset pitch;
According to this preset pitch, be upper one second scope of this circuit layout by the expansion of this first scope; And
Judge whether this clock signal line passes through this second scope.
2. P.e.c. inspection method as claimed in claim 1, is characterized in that, when this clock signal line is through this second scope, revises this circuit layout, makes this clock signal line without this second scope.
3. P.e.c. inspection method as claimed in claim 2, is characterized in that, also comprise:
This circuit layout at least part of after display update.
4. P.e.c. inspection method as claimed in claim 1, is characterized in that, when this clock signal line is through this second scope, records the position of this clock signal line in this second scope.
5. P.e.c. inspection method as claimed in claim 4, is characterized in that, also comprise:
This circuit layout of part of display this position contiguous.
6. a P.e.c. testing fixture, is characterized in that, comprises:
One layout modules, in order to provide a circuit layout, this circuit layout records at least one circuit component and at least one clock signal line, the corresponding at least one weld pad of this circuit component, and this weld pad is to should upper one first scope of circuit layout;
One setting module, couples this layout modules, in order to set a preset pitch, and according to this preset pitch, is upper one second scope of this circuit layout by the expansion of this first scope; And
One checking module, couples this layout modules and this setting module, in order to judge whether this clock signal line passes through this second scope.
7. P.e.c. testing fixture as claimed in claim 6, is characterized in that, when this clock signal line is through this second scope, this checking module, also in order to revise this circuit layout, makes this clock signal line without this second scope.
8. P.e.c. testing fixture as claimed in claim 7, it is characterized in that, this layout modules is also in order to this circuit layout at least part of after display update.
9. P.e.c. testing fixture as claimed in claim 6, is characterized in that, when this clock signal line is through this second scope, this checking module is also in order to record the position of this clock signal line in this second scope.
10. P.e.c. testing fixture as claimed in claim 9, is characterized in that, this layout modules is also in order to show this circuit layout of part of this position contiguous.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310507650.0A CN104573157A (en) | 2013-10-24 | 2013-10-24 | Method and device for checking printed circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310507650.0A CN104573157A (en) | 2013-10-24 | 2013-10-24 | Method and device for checking printed circuit |
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| Publication Number | Publication Date |
|---|---|
| CN104573157A true CN104573157A (en) | 2015-04-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310507650.0A Pending CN104573157A (en) | 2013-10-24 | 2013-10-24 | Method and device for checking printed circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110941941A (en) * | 2018-09-21 | 2020-03-31 | 和硕联合科技股份有限公司 | Inspection system and inspection method for circuit design |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2006018379A (en) * | 2004-06-30 | 2006-01-19 | Toshiba Corp | Information processor and information display method |
| CN1858750A (en) * | 2005-11-08 | 2006-11-08 | 华为技术有限公司 | Method for controlling conductor length between through hole and welding disk of printed circuit board |
| KR20110044501A (en) * | 2009-10-23 | 2011-04-29 | 삼성전자주식회사 | Semiconductor module with improved layout margin and layout method of signal lines therefor |
| CN102595773A (en) * | 2012-02-21 | 2012-07-18 | 华为终端有限公司 | Method and device for detecting design of PCB (Printed Circuit Board) and PCB |
-
2013
- 2013-10-24 CN CN201310507650.0A patent/CN104573157A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006018379A (en) * | 2004-06-30 | 2006-01-19 | Toshiba Corp | Information processor and information display method |
| CN1858750A (en) * | 2005-11-08 | 2006-11-08 | 华为技术有限公司 | Method for controlling conductor length between through hole and welding disk of printed circuit board |
| KR20110044501A (en) * | 2009-10-23 | 2011-04-29 | 삼성전자주식회사 | Semiconductor module with improved layout margin and layout method of signal lines therefor |
| CN102595773A (en) * | 2012-02-21 | 2012-07-18 | 华为终端有限公司 | Method and device for detecting design of PCB (Printed Circuit Board) and PCB |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110941941A (en) * | 2018-09-21 | 2020-03-31 | 和硕联合科技股份有限公司 | Inspection system and inspection method for circuit design |
| CN110941941B (en) * | 2018-09-21 | 2023-03-28 | 和硕联合科技股份有限公司 | Inspection system and inspection method for circuit design |
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Application publication date: 20150429 |
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