CN104572198A - Service restoration method and device - Google Patents
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Abstract
An embodiment of the invention relates to a service restoration method and device. The method includes the steps: storing the internal state of a chip, internal configuration data of the chip and partial configuration data of DRAM (dynamic random access memory) when receiving a system resetting and restarting request; configuring the DRAM from a first state to a second state; transmitting a refresh command to the DRAM from an external controller in the first state to maintain the data storage state of the DRAM unchanged; controlling the DRAM to execute a refresh operation by the DRAM in the second state to maintain the data storage state of the DRAM unchanged; resetting and restarting a system; configuring the DRAM from the second state to the first state; restoring services by the aid of the stored internal state of the chip, the stored internal configuration data of the chip and the stored partial configuration data of the DRAM. The partial configuration data of the DRAM are needed in the initialization process of the DRAM. Service restoration time can be effectively shortened, and service interruption time is shortened.
Description
Technical field
The embodiment of the present invention relates to a kind of service restoration method and device.
Background technology
In existing facility communication system or computer system, the configuration data that a large amount of system cloud gray model is correlated with is stored in the dynamic RAM (English full name is Dynamic RandomAccess Memory, and english abbreviation is DRAM) of System on Chip/SoC outside.These configuration datas normally run system and play vital effect, if configuration data is lost, system business will there will be interruption.
But when running into the system failure or system needs to upgrade, often need to carry out reset to equipment and restart, the configuration data be at this moment stored in described DRAM will all be lost.Along with the increase of communication facilities bandwidth sum processing power, the amount of configuration data stored in DRAM is also increasing.Therefore, how fast recovery configuring data, minimizing service outage duration become the problem that is needed badly solution.
There are two kinds of methods recovery configuring data when device reset is restarted in prior art, a kind of is preserve in a hard disk, the whole configuration datas in DRAM again from configuration data described in disk recovery after device reset before device reset is restarted; One does not preserve configuration data before device reset is restarted, but re-issue related configuration data to carry out business recovery by master controller after device reset.All there is the defect that the allocation data recovering time is long, service outage duration is long in these two kinds of methods, particularly when the amount of configuration data stored in DRAM is more, the time of allocation data recovering needs tens seconds even time of a few minutes.Therefore, need a kind of method and apparatus of the fast quick-recovery business when system reboot badly, to solve the problem that the allocation data recovering time is long, service outage duration is long that prior art exists.
Summary of the invention
Embodiments provide a kind of service restoration method and device, effectively can reduce allocation data recovering time during system reboot, effectively improve system service recovery speed, reduce service outage duration.
For this reason, the embodiment of the present invention provides following technical scheme:
According to the first aspect of the embodiment of the present invention, provide a kind of service restoration method, described method comprises:
When receiving system reset Restart Request, preserve the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM, the partial configuration data in described DRAM are the data needing to use in described DRAM initialization procedure;
Configure described DRAM and switch to the second state from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition;
Reset reboot operation is carried out to system;
Configure described DRAM and switch to described first state from described second state;
The partial configuration data in the described chip internal state of preserving, described chip internal configuration data and described DRAM are utilized to carry out business recovery.
In the first possible implementation of first aspect, the partial configuration data in described preservation chip internal state, described chip internal configuration data and dynamic RAM DRAM comprise:
Preserve on one or more to described DRAM, hard disk or host computer system of partial configuration data in chip internal state, described chip internal configuration data and dynamic RAM DRAM.
In the implementation that the second of first aspect is possible, described DRAM carries out being in described second state in reset reboot operation process in described system.
In the third possible implementation of first aspect, described peripheral control unit is specially dram controller, and the described DRAM of described configuration switches to the second state to comprise from the first state:
Judge whether described system is in quick reforestation practices;
If so, then control described DRAM by described dram controller and switch to described second state from described first state.
In the 4th kind of possible implementation of first aspect, described peripheral control unit is specially dram controller, and described method also comprises:
Determine the current operation mode of described dram controller; The mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and wherein, it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation;
The described DRAM of described configuration switches to described first state to comprise from described second state:
When the current operation mode determining described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.
In conjunction with the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation of first aspect, described method also comprises:
When the current operation mode determining described dram controller is described second mode of operation, initialization operation is carried out to described DRAM, total space self-test operations is carried out to the data in described DRAM.
According to the second aspect of the embodiment of the present invention, provide a kind of business recovery device, described device comprises:
Storage unit, for when receiving system reset Restart Request, preserve the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM, the partial configuration data in described DRAM are the data needing to use in described DRAM initialization procedure;
First dispensing unit, switches to the second state for configuring described DRAM from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition;
Unit is restarted in reset, for carrying out reset reboot operation to system;
Second dispensing unit, switches to described first state for configuring described DRAM from described second state;
Recovery unit, the partial configuration data in the described chip internal state, chip internal configuration data and the described DRAM that preserve for utilizing described storage unit carry out business recovery.
In the first possible implementation of second aspect, described storage unit specifically for:
Preserve on one or more to described DRAM, hard disk and host computer system of partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
In the implementation that the second of second aspect is possible, described DRAM carries out being in described second state in reset reboot operation process in described system.
In the third possible implementation of second aspect, described peripheral control unit is specially dram controller, and described first dispensing unit comprises:
Judging unit, for judging whether described system is in quick reforestation practices;
Switch unit, for when the judged result of described judging unit is for being, controls described DRAM by described dram controller and switching to described second state from described first state.
In the 4th kind of possible implementation of second aspect, described peripheral control unit is specially dram controller, and described device also comprises:
Determining unit, for determining the current operation mode of described dram controller; The mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and wherein, it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation;
Described second dispensing unit specifically for:
When the current operation mode that described determining unit determines described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.
In conjunction with the 4th kind of possible implementation of second aspect, in the 5th kind of possible implementation of second aspect, described device also comprises:
Initial self-test unit, during for determining that when described determining unit the current operation mode of described dram controller is described second mode of operation, carrying out initialization operation to described DRAM, carrying out total space self-test operations to the data in described DRAM.
The service restoration method that the embodiment of the present invention provides and device, before system reset is restarted, preserve chip internal state, chip internal configuration data and a small amount of DRAM configuration data, and configure described DRAM and switch to the second state from the first state, wherein, described DRAM be in said second condition self-refresh state can maintain self preserve data do not lose; After system reset is restarted, a small amount of chip internal state of preservation, chip internal configuration data and a small amount of DRAM configuration data only need be utilized to carry out business recovery, thus substantially reduce the release time of configuration data, effectively improve system service recovery speed, reduce service outage duration.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the application, for those of ordinary skill in the art, other accompanying drawing can also be obtained according to these accompanying drawings.
A kind of service restoration method schematic flow sheet that Fig. 1 provides for the embodiment of the present invention;
The another kind of service restoration method schematic flow sheet that Fig. 2 provides for the embodiment of the present invention;
The dram controller control flow schematic diagram that Fig. 3 provides for the embodiment of the present invention;
The service restoration method effect schematic diagram that Fig. 4 provides for prior art;
Fig. 5 is the service restoration method effect schematic diagram under a kind of application scenarios of the embodiment of the present invention;
A kind of business recovery device schematic diagram that Fig. 6 provides for the embodiment of the present invention;
The another kind of business recovery device schematic diagram that Fig. 7 provides for the embodiment of the present invention.
Embodiment
In prior art, when facility communication system or computer system reset and restart, cannot ensure that the legacy data be stored in DRAM is not destroyed, no matter be the mode of preserving DRAM configuration data in a hard disk, or issued the mode of DRAM configuration data by master controller, all there is the defect that the allocation data recovering time is long, service outage duration is long.
Based on this, embodiments provide a kind of service restoration method and device, effectively can reduce allocation data recovering time during system reboot, effectively improve system service recovery speed, reduce service outage duration.The service restoration method of the embodiment of the present invention and device can be applied to facility communication system or computer system.
Technical scheme in the present invention is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
The term used in embodiments of the present invention is only for the object describing specific embodiment, and not intended to be limiting the present invention." one ", " described " and " being somebody's turn to do " of the singulative used in the embodiment of the present invention and appended claims is also intended to comprise most form, unless context clearly represents other implications.It is also understood that term "and/or" used herein refer to and comprise one or more project of listing be associated any or all may combine." system " of the embodiment of the present invention can be all devices comprising central processor CPU and DRAM, and such as, " system " of the embodiment of the present invention can be computer system or communication facilities.
See Fig. 1, be a kind of service restoration method schematic flow sheet that the embodiment of the present invention provides, shown method comprises:
S101, when receiving system reset Restart Request, preserves the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
When specific implementation of the present invention, the situation that system sends reset Restart Request includes but not limited to: time when soft failure (English full name is Single Event Upset, because be abbreviated as SEU) fault occurs, when generation systems fault or when having upgrade request when system.Described system reset Restart Request can be that some business boards send, or described system reset Restart Request can be multiple business board or described system reset Restart Request can be that business chip sends, described system reset Restart Request also can be that the host chip at master controller place sends.When described system reset Restart Request is by business board or business chip transmission, when restarting device reset, often only restart breaking down or having the business board of upgrade request or business chip to carry out reset, host chip does not often need to carry out reset and restarts.
Described DRAM is chip exterior storer, runs relevant configuration data for storage system, and described configuration data includes but not limited to the transmitting of switch, stream table, routing table etc., and the present invention does not limit this.It should be noted that, business chip and host chip all can be configured with respective DRAM, and when receiving reset Restart Request, the data of preservation are the data that the chip corresponding with sending reset Restart Request is associated.Specifically can comprise state and the configuration data of chip internal, and, at least part of configuration data in the DRAM of chip exterior.At least part of configuration data of described DRAM is the data needing to use in described DRAM initialization procedure.Usually, need to carry out read-write operation to partial data in DRAM initialization procedure, the state of partial data can be destroyed thus, change its state.Therefore, need, to needing the address date used to preserve in DRAM initialization procedure, to maintain its state before business recovery.Like this, even if after system reset is thereafter restarted, in DRAM initialization procedure, these data are destroyed due to read-write operation, the state before the described a small amount of configuration data preserved in advance also can be utilized the configuration restore of DRAM to be restarted to system reset.For a large amount of configuration datas that DRAM stores, the quantity of the partial configuration data of preserving in advance is a considerably less part, therefore shared space and the time spent all little, when system carries out business recovery, need recover this part configuration data due to quantity few, therefore also only need less release time, substantially reduce service recovery time, decrease service outage duration.
Wherein, at least part of configuration data preserved in chip internal state, chip internal configuration data and dynamic RAM DRAM comprises: preserve on one or more to described DRAM, hard disk or host computer system of at least part of configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
Wherein, described DRAM carries out being in the second state in reset reboot operation process in described system.
It should be noted that, due to when specific implementation of the present invention, before system reset is restarted, under described DRAM is configured to be in the second state, it is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition.That is, described DRAM is configured to self-refresh (Self Refresh) state, in this condition, self controls described DRAM by described DRAM and perform refresh operation.According to the difference that DRAM realizes, refresh command can being sent by dram chip self to described DRAM and perform refresh operation with timing, also by arranging the mode of timer, refresh operation can be performed by DRAM timing.The present invention does not limit concrete implementation.Perform refresh operation because DRAM can control self, the state data memory in described DRAM therefore can be kept constant, that is keep the data stored in described DRAM not lose.Therefore, at least part of configuration data in described chip internal state, chip internal configuration data and described DRAM can be kept in described DRAM.
In addition, due to preserve chip internal state, partial configuration data in chip internal configuration data and DRAM data volume very little, on therefore can also to be kept in hard disk or host computer system one or more.Particularly, can save the data in the internal memory of host computer system, the internal memory of host computer system can be the internal memory of host chip, also can be the outside DRAM that host chip is corresponding.Due to generally, host computer system is not carried out reset and is restarted in operation system reset restarting process, therefore saves the data in host computer system and can ensure that data are not lost yet.When the system of restarting when needing to carry out resetting is host computer system, at this moment, described data can be kept in the DRAM of host computer system chip exterior, and configure described DRAM and be in the second state and self-refresh state to ensure that data are not lost, certainly, also described data can be preserved in a hard disk.The mode of specific implementation can be very flexibly, and those skilled in the art can be arranged as required.
S102, configures described DRAM and switches to the second state from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition.
It should be noted that, due to the feature of DRAM self, data can only be kept the very short time by it, do not lose to keep storing data, DRAM uses capacitance stores, so must refresh (refresh) once every a period of time, if storage unit is not refreshed, the information stored will be lost, such as will obliterated data when shutting down or device reset is restarted.Wherein, the process that DRAM electric capacity is periodically refreshed, also can be considered as carrying out in the process of precharge to electric capacity, to ensure that electric capacity keeps the data stored with enough electricity.Generally, DRAM is in external refresh state, sends refresh command by peripheral control unit to described DRAM, controls described DRAM and performs refresh operation, constant with the state data memory maintained in described DRAM, that is the data keeping DRAM to store are not lost.Described peripheral control unit can comprise dram controller, or other external units.In prior art, due to system reset restart time, DRAM and dram controller do not carry out initialization, can not ensure to send enough refresh commands to ensure that DRAM data are not lost to DRAM, therefore, in prior art, often there is the situation that when device reset is restarted, DRAM data are all lost.The present invention is just for this defect, propose, before system reset is restarted, DRAM is switched to the second state from the first state, that is switch to self-refresh state from external refresh state, control described DRAM by DRAM self and perform refresh operation regularly to refresh, therefore the state data memory in described DRAM can be kept constant, that is keep the data stored in described DRAM not lose.
During specific implementation, when receiving system reboot request, described DRAM can be configured by dram controller and switching to described second state, in system reboot process from described first state, DRAM is in the second state and self-refresh state, and its inner configuration data preserved can not be lost.
Further, when receiving system reboot request, also first can judge whether system is in quick reforestation practices, if so, then controlling described DRAM by described dram controller and switching to described second state from described first state.If not, then do not perform blocked operation, at this moment in follow-up reset restarting process, DRAM will carry out initialization operation according to normal normal process.
S103, carries out reset reboot operation to system.
In this step, device reset is restarted, and carries out corresponding fault recovery or updating operation.At this moment, the not power down of guarantee system is needed.The specific implementation of this step similarly to the prior art, does not repeat them here.
S104, configures described DRAM and switches to described first state from described second state.
Configuration DRAM switches to the first state from the second state, namely switches to external refresh state from self-refresh state.At this moment, the initialization operation to DRAM interface can be completed.In initialization procedure, only limited address read-write operation is carried out to DRAM.Correspondingly, carry out the partial configuration data in the DRAM in the corresponding step S101 of data of address read-write operation, preserved in advance at S101, even if therefore carry out read-write in initial procedure, data are destroyed, also can not be affected follow-up business recovery operation.When to DRAM initialization operation, avoid carrying out total space self-test operations to the data in described DRAM.Like this, namely can ensure that in DRAM internal memory, most data is not destroyed.
In another kind of implementation, described peripheral control unit is specially dram controller, can also comprise: the current operation mode determining described dram controller before execution S104.Wherein, the mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation.That is, dram controller in a first operation mode, will send refresh command to DRAM and not lose with the storage data maintained in described DRAM.Dram controller in a first operation mode, does not carry out reset operation to dram chip, to ensure that dram chip content is not destroyed, does not also carry out total space self-inspection to DRAM, to ensure data inside chips not by considerable damage simultaneously.Wherein, described dram controller controls described DRAM and exits self-refresh state in initialization procedure, and configure described DRAM associated configuration register, interface Training self-inspection is carried out to limited address, described in whole operating process, dram controller needs to send enough refresh commands to described DRAM and does not lose to maintain DRAM storage data.Consider from system reliability angle, only read-write operation is carried out to a small amount of address of described DRAM, to check the reliability of DRAM interface.In the second operation mode, namely conventional normal mode of operation, its dram chip initialize flow specified in accordance with standard operates described dram controller, sends reset command, and carry out total space self-inspection to the data in described DRAM to described DRAM.Particularly, described dram controller carries out the initialized main process of DRAM in the second operation mode and comprises: reset DRAM, configuration relevant DRAM associative mode register, interface TRAining, and carries out total space self-inspection.At this operation control, dram controller does not need timing to send refresh command to DRAM, and therefore DRAM is in initialization procedure, will change its state data memory.
When the current operation mode determining described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.Also just say, when determining that dram controller is the first mode of operation, control command will be sent to described DRAM, and controlling described DRAM and switch to external refresh state from self-refresh state.At this moment, start DRAM interface initialization operation, in the process, reset operation is not carried out to DRAM, and ensure to send enough refresh commands to DRAM, for ensureing that DRAM data are not lost.After DRAM interface initialization completes, only read-write operation is carried out to a small amount of address of DRAM, for verifying the reliability of DRAM interface.Meanwhile, total space self-inspection is not carried out to DRAM, greatly will save the time of DRAM date restoring thus, realize the fast quick-recovery of DRAM configuration.It should be noted that, system first starting up time, conveniently flow process has carried out total space self-inspection to DRAM, therefore ensure that the reliability of DRAM interface and configuration data, therefore, when reset is restarted, only read-write operation is carried out to a small amount of DRAM address, and total space self-inspection is not carried out to DRAM, also can ensure the reliability of system.What is more important, thus can the destroyed risk of less data, greatly can also shorten the time of system service recovery.
S105, utilizes the partial configuration data in described chip internal state, chip internal configuration data and the described DRAM preserved to carry out business recovery.
Utilize the partial configuration data in chip internal state, chip internal configuration data and the described DRAM preserved in S101, the configuration restore of completion system, system configuration is returned to the state before restarting that resets, system business function keeps following the state consistency before resetting.
During due to specific implementation of the present invention, DRAM is set to the second state and self-refresh state can ensure that most of data that DRAM stores are not lost before reset is restarted, except needing the data used and may be destroyed in DRAM initialization procedure, the data and system in DRAM is consistent before resetting and restarting.At this moment, recycle the partial configuration data in the DRAM preserved in advance that is need to use and this part destroyed data of the date restoring DRAM that may destroy at initialization procedure, therefore can realize business recovery rapidly, reduce service outage duration.
See Fig. 2, be the another kind of service restoration method schematic flow sheet that the embodiment of the present invention provides, described method comprises:
S201, when receiving system reset Restart Request, preserves at least part of configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
S202, after having preserved corresponding data, system closing corresponding service interface, interrupting service.
S203, system configuration DRAM are switched to the second state and self-refresh state, and DRAM can maintain storage data in said second condition and not lose.
S204, carries out reset reboot operation to equipment, carries out fault recovery or system upgrade operation.
S205, system configuration DRAM are switched to the first state from the second state, complete DRAM interface initialization.
In this performing step, configuration DRAM is exited data self-refresh state by system, enters normal mode of operation, namely enters external refresh pattern, sends refresh command by external memory storage to it, and completes the initialization of DRAM memory interface.In initialization procedure, only limited address read-write operation is carried out to DRAM internal memory, total space Scanning Detction is not carried out to DRAM internal memory, be not destroyed to keep most data in DRAM internal memory.
S206, the date restoring chip internal state utilizing S201 to preserve, chip internal configuration data and a small amount of DRAM configuration data, the configuration restore of completion system, business function keeps following the state consistency before resetting.
S207, opens business interface, and appliance services is recovered.
It should be noted that, during embodiment of the present invention specific implementation, by specific dram controller operating process, the switching of DRAM state can be carried out to ensure that DRAM is restarted internal data and do not lost.Be described below in conjunction with the control flow of flow process shown in Fig. 3 to the dram controller that the embodiment of the present invention provides.
See Fig. 3, it is the dram controller control flow schematic diagram that the embodiment of the present invention provides.
S301, when there being system reboot request, judges whether current system is in quick reforestation practices.If so, S302 is entered; If not, S303 is entered.
S302, controls dram chip and enters self-refresh state, enter S303.
S303, system reset is restarted, and when determining to need to carry out initialization to DRAM, judges whether described dram controller is in the first mode of operation; If so, S304 is entered; If not, S306 is entered.Wherein, dram controller is " exiting self-refresh start-up mode " in a first operation mode, timing will send enough refresh commands to DRAM, ensure that DRAM data are not lost.
S304, controls dram chip and exits self-refresh state, enter S305.
S305, DRAM interface initialization.In the process, reset operation is not carried out to DRAM, do not carry out total space self-inspection, ensure to send enough refresh commands to DRAM, with the fast quick-recovery of completion system configuration.Then, S307 is entered.
S306, DRAM interface initialization, carries out reset operation to DRAM, and carries out total space self-inspection, and system cache configuration refreshes.
S307, system is normally run.
It should be noted that, in one implementation, when judging current system not for quick reforestation practices in S301, S303 judges that the step whether dram controller is in the first mode of operation is not required, also when S301 judges current system not for quick reforestation practices, and directly S306 can be performed when system has during DRAM initial reguirements.Above example is only exemplary illustration, is not considered as limitation of the present invention, and those skilled in the art can change above-described embodiment or be out of shape, and all belong to protection scope of the present invention.
The present invention needs to need when restarting system, flogic system fault to restart the application scenarios etc. that system or system needs upgrading needs are restarted when can be applied to SEU fault.In system without backup protection, needing the application scenarios of system reboot, when being cached with the communication facilities of a large amount of configuration datas in Installed System Memory, the fast quick-recovery business of equipment can be realized by the embodiment of the present invention, lifting means fault recovery speed.See the service restoration method effect schematic diagram that Fig. 4 provides for prior art; Fig. 5 is the service restoration method effect schematic diagram under a kind of application scenarios of the embodiment of the present invention.As can be seen from Figure 4, in prior art, from system reset to system service recovery, its time will be greater than 300S.And apply method of the present invention, from system reset to system service recovery, the time will foreshorten to 1S.
The method that the embodiment of the present invention provides may be used for including but not limited to that FPGA, NP, cpu chip use the communication facilities of outside DRAM cache configuration data.Use the scheme in the present invention, the configuration restore time can be reduced, realize fast quick-recovery business.
See Fig. 6, it is a kind of business recovery device 600 schematic diagram that the embodiment of the present invention provides.Shown device may be used for the method realized shown in Fig. 1 to Fig. 3.Wherein, described device 600 comprises:
Storage unit 601, for when receiving system reset Restart Request, preserve the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM, the partial configuration data in described DRAM are the data needing to use in described DRAM initialization procedure.
First dispensing unit 602, switches to the second state for configuring described DRAM from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition.
Unit 603 is restarted in reset, for carrying out reset reboot operation to system.
Second dispensing unit 604, switches to described first state for configuring described DRAM from described second state.
Recovery unit 605, at least part of configuration data in the described chip internal state, chip internal configuration data and the described DRAM that preserve for utilizing described storage unit carries out business recovery.
Further, described storage unit specifically for:
Preserve on one or more to described DRAM, hard disk or host computer system of partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
Wherein, described DRAM carries out being in described second state in reset reboot operation process in described system.
Further, described peripheral control unit is specially dram controller, and described first dispensing unit comprises:
Judging unit, for judging whether described system is in quick reforestation practices;
Switch unit, for when the judged result of described judging unit is for being, controls described DRAM by described dram controller and switching to described second state from described first state.
Further, described peripheral control unit is specially dram controller, and described device also comprises:
Determining unit, for determining the current operation mode of described dram controller; The mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and wherein, it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation;
Described second dispensing unit specifically for:
When the current operation mode that described determining unit determines described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.
Further, described device also comprises:
Initial self-test unit, during for determining that when described determining unit the current operation mode of described dram controller is described second mode of operation, carrying out initialization operation to described DRAM, carrying out total space self-test operations to the data in described DRAM.
See Fig. 7, it is another kind of business recovery device 700 schematic diagram that the embodiment of the present invention provides.Shown device may be used for the method realized shown in Fig. 1 to Fig. 3.Schematic diagram shown in Figure 7, shown business recovery device 700 can comprise at least one processor 701, at least one network interface 702 or other communication interface, storer 703, with at least one communication bus 704, for realizing the connection communication between these devices.The executable module of processor 701 for storing in execute store 703, such as computer program.This processor 701 can be CPU, storer 703 may comprise high-speed random access memory (RandomAccess Memory, RAM), also non-labile storer (non-volatilememory) may also be comprised, such as at least one magnetic disk memory.Realize the communication connection between this system gateway and at least one other network element by least one network interface, can internet be used, wide area network, local network, Metropolitan Area Network (MAN) etc.
Described storer 703 is for storing batch processing instruction, and described processor 701 performs following operation for the programmed instruction calling the storage of described storer 703:
When receiving system reset Restart Request, preserve the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM, the partial configuration data in described DRAM are the data needing to use in described DRAM initialization procedure;
Configure described DRAM and switch to the second state from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition;
Reset reboot operation is carried out to system;
Configure described DRAM and switch to described first state from described second state;
The partial configuration data in the described chip internal state of preserving, described chip internal configuration data and described DRAM are utilized to carry out business recovery.
Wherein, described processor 701 also for: preserve one or more to described DRAM, hard disk or host computer system of at least part of configuration data in chip internal state, described chip internal configuration data and dynamic RAM DRAM.Wherein, described DRAM carries out being in described second state in reset reboot operation process in described system.
Wherein, described processor 701 also for: judge whether described system is in quick reforestation practices;
If so, then control described DRAM by dram controller and switch to described second state from described first state.
Wherein, described processor 701 is also for the current operation mode determining dram controller; The mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and wherein, it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation;
When the current operation mode determining described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.
Wherein, described processor 701 also for: when the current operation mode determining described dram controller is described second mode of operation, initialization operation is carried out to described DRAM, total space self-test operations is carried out to the data in described DRAM.
The device 700 for business recovery that the embodiment of the present invention provides, by before system reset is restarted, preserve chip internal state, chip internal configuration data and a small amount of DRAM configuration data, and configure described DRAM and switch to the second state from the first state, wherein, described DRAM be in said second condition self-refresh state can maintain self preserve data do not lose; After system reset is restarted, a small amount of chip internal state of preservation, chip internal configuration data and a small amount of DRAM configuration data only need be utilized to carry out business recovery, thus substantially reduce the release time of configuration data, effectively improve system service recovery speed, reduce service outage duration.
Comparatively simple to the introduction of device embodiment above, can refer to embodiment of the method and realize each device embodiment of the present invention.
The present invention program can describe in the general context of computer executable instructions, such as program element.Usually, program element comprises the routine, program, object, assembly, data structure etc. that perform particular task or realize particular abstract data type.Also can put into practice the present invention program in a distributed computing environment, in these distributed computing environment, be executed the task by the remote processing devices be connected by communication network.In a distributed computing environment, program element can be arranged in the local and remote computer-readable storage medium comprising memory device.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually see, what each embodiment stressed is the difference with other embodiment.Especially, for device embodiment, because it is substantially similar to embodiment of the method, so describe fairly simple, relevant part illustrates see the part of embodiment of the method.Device embodiment described above is only schematic, the wherein said unit illustrated as separating component or can may not be and physically separates, parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of module wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement.
Being described in detail the embodiment of the present invention above, applying embodiment herein to invention has been elaboration, the explanation of above embodiment just understands method and apparatus of the present invention for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. a service restoration method, is characterized in that, described method comprises:
When receiving system reset Restart Request, preserve the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM, the partial configuration data in described DRAM are the data needing to use in described DRAM initialization procedure;
Configure described DRAM and switch to the second state from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition;
Reset reboot operation is carried out to system;
Configure described DRAM and switch to described first state from described second state;
The partial configuration data in the described chip internal state of preserving, described chip internal configuration data and described DRAM are utilized to carry out business recovery.
2. method according to claim 1, is characterized in that, the partial configuration data in described preservation chip internal state, chip internal configuration data and dynamic RAM DRAM comprise:
Preserve on one or more to described DRAM, hard disk and host computer system of partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
3. method according to claim 2, is characterized in that, described DRAM carries out being in described second state in reset reboot operation process in described system.
4. method according to claim 1, is characterized in that, described peripheral control unit is specially dram controller, and the described DRAM of described configuration switches to the second state to comprise from the first state:
Judge whether described system is in quick reforestation practices;
If so, then control described DRAM by described dram controller and switch to described second state from described first state.
5. method according to claim 1, is characterized in that, described peripheral control unit is specially dram controller, and described method also comprises:
Determine the current operation mode of described dram controller; The mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and wherein, it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation;
The described DRAM of described configuration switches to described first state to comprise from described second state:
When the current operation mode determining described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.
6. method according to claim 5, is characterized in that, described method also comprises:
When the current operation mode determining described dram controller is described second mode of operation, initialization operation is carried out to described DRAM, total space self-test operations is carried out to the data in described DRAM.
7. a business recovery device, is characterized in that, described device comprises:
Storage unit, for when receiving system reset Restart Request, preserve the partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM, the partial configuration data in described DRAM are the data needing to use in described DRAM initialization procedure;
First dispensing unit, switches to the second state for configuring described DRAM from the first state; Wherein, described DRAM is constant with the state data memory maintained in described DRAM to described DRAM transmission refresh command by peripheral control unit in said first condition; It is constant with the state data memory maintained in described DRAM that described DRAM self controls described DRAM execution refresh operation by described DRAM in said second condition;
Unit is restarted in reset, for carrying out reset reboot operation to system;
Second dispensing unit, switches to described first state for configuring described DRAM from described second state;
Recovery unit, the partial configuration data in the described chip internal state, chip internal configuration data and the described DRAM that preserve for utilizing described storage unit carry out business recovery.
8. device according to claim 7, is characterized in that, described storage unit specifically for:
Preserve on one or more to described DRAM, hard disk and host computer system of partial configuration data in chip internal state, chip internal configuration data and dynamic RAM DRAM.
9. device according to claim 8, is characterized in that, described DRAM carries out being in described second state in reset reboot operation process in described system.
10. device according to claim 7, is characterized in that, described peripheral control unit is specially dram controller, and described first dispensing unit comprises:
Judging unit, for judging whether described system is in quick reforestation practices;
Switch unit, for when the judged result of described judging unit is for being, controls described DRAM by described dram controller and switching to described second state from described first state.
11. devices according to claim 7, it is characterized in that, described peripheral control unit is specially dram controller, described device also comprises:
Determining unit, for determining the current operation mode of described dram controller; The mode of operation of described dram controller comprises the first mode of operation and the second mode of operation, and wherein, it is constant with the state data memory maintained in described DRAM that described dram controller sends refresh command to described DRAM in this first operative mode; Described dram controller sends reset command to change the state data memory of described DRAM to described DRAM under described second mode of operation;
Described second dispensing unit specifically for:
When the current operation mode that described determining unit determines described dram controller is described first mode of operation, control described DRAM by described dram controller and switch to described first state from described second state, initialization operation is carried out to described DRAM, avoids carrying out total space self-test operations to the data in described DRAM.
12. devices according to claim 11, is characterized in that, described device also comprises:
Initial self-test unit, during for determining that when described determining unit the current operation mode of described dram controller is described second mode of operation, carrying out initialization operation to described DRAM, carrying out total space self-test operations to the data in described DRAM.
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| CN110633166A (en) * | 2018-06-22 | 2019-12-31 | 迈普通信技术股份有限公司 | Reset device and reset method |
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| CN104572198B (en) | 2018-04-10 |
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