CN104571245A - Single-BE-node continuous output switch capacitance band gap reference circuit - Google Patents
Single-BE-node continuous output switch capacitance band gap reference circuit Download PDFInfo
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- CN104571245A CN104571245A CN201410780583.4A CN201410780583A CN104571245A CN 104571245 A CN104571245 A CN 104571245A CN 201410780583 A CN201410780583 A CN 201410780583A CN 104571245 A CN104571245 A CN 104571245A
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- circuit
- controllable switch
- potential storage
- storage circuit
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Abstract
The invention discloses a single-BE-node continuous output switch capacitance band gap reference circuit, and relates to the technical field of a device for regulating voltage or current. The reference circuit comprises a first current source group, a first controllable switch group Sa, a BE node generating circuit, a second controllable switch group Sb, a voltage storage circuit group a, controllable switches S0 to S6, a first voltage storage circuit, a voltage average storage circuit, a first addition circuit, a gain circuit K, a second voltage storage circuit, a second addition circuit and a third voltage storage circuit. The single-BE-node continuous output switch capacitance band gap reference circuit has the advantages that the output reference voltage of the circuit is more precise, the process flexibility and the stability are higher, resistance is not adopted, the compatibility with a standard digital CMOS (complementary metal oxide semiconductor) process can be realized, and the compatibility is high.
Description
Technical field
The present invention relates to the device technique field of regulation voltage or electric current, particularly relate to a kind of single BE and tie continuous output switch capacitor strap gap reference circuit.
Background technology
Reference circuit is one of most important module in all integrated circuit (IC) system, for other circuit modules provide voltage reference or the current reference of high precision and high stability, be widely used in Digital and analog integrated circuit, the circuit such as such as DC-DC modulator, linear voltage regulator, digital-to-analogue/analog to digital conversion circuit, flash memory, various driver, communications transmit, receiver.Wherein, band-gap reference, because structural principle is simple, realize convenient, function admirable, is most widely used, the overall performance of its characteristic direct relation system.
It is comparatively large that traditional band-gap reference circuit is subject to input offset voltage of operational amplifier impact, reducing quiescent dissipation simultaneously, generally adopting large proportion resistor, easily taking excessive chip area to reduce single channel electric current.Band-gap reference circuit based on switching capacity can solve the offset voltage problem of amplifier, but adopts the triode (or diode) of 8:1 even more vast scale, still can not avoid the problem that area is excessive.And the deviation of triode ratio brought due to manufacturing process error and the deviation of current mirror ratio also can bring impact to the output accuracy of benchmark.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of single BE and ties continuous output switch capacitor strap gap reference circuit, the output reference voltage of described circuit is more accurate, technological flexibility and stability higher, chip area is little, do not adopt resistance, can be compatible with Standard Digital CMOS, compatible strong.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of single BE ties continuous output switch capacitor strap gap reference circuit, it is characterized in that: described reference circuit comprises current source group I, the first gate-controlled switch group S
a, BE knot produce circuit, the second gate-controlled switch group S
b, potential storage circuit group a, controllable switch S
0-S
6, the first potential storage circuit, average voltage memory circuit, the first adding circuit, gain circuitry K, the second potential storage circuit, the second adding circuit and tertiary voltage memory circuit, power vd D is successively through current source group I, the first gate-controlled switch group S
atie with BE the emitter producing circuit to be connected, BE knot produces the emitter first via of circuit successively through controllable switch S
0, the first potential storage circuit, controllable switch S
2be connected with the input end that subtracts of the first adding circuit, BE knot produces all the other roads of emitter of circuit successively through the second gate-controlled switch group S
b, potential storage circuit group a, average voltage memory circuit, controllable switch S 1 be connected with the input end that adds of the first adding circuit, the output terminal of the first adding circuit is successively through gain circuitry K, controllable switch S
3, the second potential storage circuit, controllable switch S
5add input end be connected with one of the second adding circuit, the first potential storage circuit and controllable switch S
2node through controllable switch S
4add input end with another of the second adding circuit to be connected, the output terminal of the second adding circuit is through controllable switch S
6be connected with one end of tertiary voltage memory circuit, the other end of tertiary voltage memory circuit is the voltage output end of described reference circuit.
Further technical scheme is: described current source group I comprises several current sources I
n, described first gate-controlled switch group S
acomprise and described current source I
nthe controllable switch S that number is identical
an, described second gate-controlled switch group S
bcomprise and described current source I
nthe controllable switch S that number is identical
bn, described potential storage circuit group a comprises and described current source I
nthe potential storage circuit an that number is identical, current source I
1with controllable switch S
a1series connection, current source I
2with controllable switch S
a2series connection, the like, current source I
nwith controllable switch S
anseries connection, the current source I of series connection mutually
nand controllable switch S
anform some current source branch, above-mentioned some current source branch are parallel with one another; Controllable switch S
b1connect with potential storage circuit a1, controllable switch S
b2connect with potential storage circuit a2, the like, controllable switch S
bnconnect with potential storage circuit an, the controllable switch S of series connection mutually
bnform some store voltages branch roads with potential storage circuit an, above-mentioned some store voltages branch roads are parallel with one another, described n be more than or equal to 2 natural number.
Further technical scheme is: described reference circuit also comprises the 3rd gate-controlled switch group S between average voltage memory circuit and potential storage circuit group a
c, described 3rd gate-controlled switch group S
ccomprise and described current source I
nthe controllable switch S that number is identical
cn, described controllable switch S
b1successively with potential storage circuit a1, controllable switch S
c1series connection, described controllable switch S
b2successively with potential storage circuit a2, controllable switch S
c2series connection, the like, described controllable switch S
bnsuccessively with potential storage circuit an, controllable switch S
cnseries connection, the controllable switch S of series connection mutually
bn, potential storage circuit an, controllable switch S
cnform some store voltages branch roads, above-mentioned some store voltages branch roads are parallel with one another, described n be more than or equal to 2 natural number.
Further technical scheme is: described potential storage circuit is electric capacity.
The beneficial effect that produces of technique scheme is adopted to be: described reference circuit is tied to produce by gauge tap turn-on sequence controls BE and circuit flow through different electric current thus the use number producing different voltage and then minimizing triode or diode, by the average evaluation of multichannel, guarantee that more high-precision reference voltage exports, there is great technological flexibility and stability, the present invention does not adopt resistance, can be compatible with Standard Digital CMOS, compatible strong.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Fig. 1 is theory diagram of the present invention;
Fig. 2 is the schematic diagram of the embodiment of the present invention one;
Fig. 3 is the output waveform of the embodiment of the present invention one.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
The invention discloses a kind of single BE and tie continuous output switch capacitor strap gap reference circuit, described reference circuit comprises current source group I, the first gate-controlled switch group S
a, BE knot produce circuit, the second gate-controlled switch group S
b, potential storage circuit group a, controllable switch S
0-S
6, the first potential storage circuit (memory circuit 1 namely in Fig. 1), average voltage memory circuit, the first adding circuit, gain circuitry K, the second potential storage circuit (memory circuit 2 namely in Fig. 1), the 3rd gate-controlled switch group S
c, the second adding circuit and tertiary voltage memory circuit (memory circuit 3 namely in Fig. 1).
As shown in Figure 1, power vd D is successively through current source group I, the first gate-controlled switch group S for concrete annexation
atie with BE the emitter producing circuit to be connected, BE knot produces the emitter first via of circuit successively through controllable switch S
0, the first potential storage circuit, controllable switch S
2be connected with the input end that subtracts of the first adding circuit, BE knot produces all the other roads of emitter of circuit successively through the second gate-controlled switch group S
b, potential storage circuit group a, the 3rd gate-controlled switch group S
c, average voltage memory circuit, controllable switch S 1 be connected with the input end that adds of the first adding circuit, the output terminal of the first adding circuit is successively through gain circuitry K, controllable switch S
3, the second potential storage circuit, controllable switch S
5add input end be connected with one of the second adding circuit, the first potential storage circuit and controllable switch S
2node through controllable switch S
4add input end with another of the second adding circuit to be connected, the output terminal of the second adding circuit is through controllable switch S
6be connected with one end of tertiary voltage memory circuit, the other end of tertiary voltage memory circuit is the voltage output end of described reference circuit.
As shown in Figure 1, described current source group I comprises several current sources I
n, described first gate-controlled switch group S
acomprise and described current source I
nthe controllable switch S that number is identical
an, described second gate-controlled switch group S
bcomprise and described current source I
nthe controllable switch S that number is identical
bn, described 3rd gate-controlled switch group S
ccomprise and described current source I
nthe controllable switch S that number is identical
cn, described potential storage circuit group a comprises and described current source I
nthe identical potential storage circuit an(of number in the present invention n be more than or equal to 2 natural number).
Current source I
1with controllable switch S
a1series connection, current source I
2with controllable switch S
a2series connection, the like, current source I
nwith controllable switch S
anseries connection, the current source I of series connection mutually
nand controllable switch S
anform some current source branch, above-mentioned some current source branch are parallel with one another.Described controllable switch S
b1successively with potential storage circuit a1, controllable switch S
c1series connection, described controllable switch S
b2successively with potential storage circuit a2, controllable switch S
c2series connection, the like, described controllable switch S
bnsuccessively with potential storage circuit an, controllable switch S
cnseries connection, the controllable switch S of series connection mutually
bn, potential storage circuit an, controllable switch S
cnform some store voltages branch roads, above-mentioned some store voltages branch roads are parallel with one another.
Described first gate-controlled switch group S
ahave and open successively, open simultaneously and close n+2 kind situation simultaneously, described current source group I is by the first gate-controlled switch group S
aturn-on sequence is different, produces on circuit respectively produce n+2 kind voltage namely at BE knot:
v bE1-
v bEn,
v bEall, " 0 ".Described voltage
v bE1-
v bEnat described second gate-controlled switch group S
bin gate-controlled switch
s b1-
s bnrespectively stored in the potential storage circuit a1-an of potential storage circuit group a during conducting, after this described 3rd gate-controlled switch group S
cconducting simultaneously, average voltage memory circuit is to the voltage stored
v bE1-
v bEnask for mean deviation storage voltage
v beav.
Voltage
v beallat described gate-controlled switch
s 0during conducting, stored in the first potential storage circuit, complete at described average voltage memory circuit and store rear described gate-controlled switch
s 1and gate-controlled switch
s 2conducting simultaneously, gate-controlled switch
s 3and gate-controlled switch
s 4close, the first described adding circuit is to voltage
v bEalland voltage
v bEavcomplete subtraction, output voltage Δ
v bE=
v bEall-
v beav, described gain circuitry K is by voltage
Δ V bEamplify k doubly, output voltage
v a=
k*
Δ V bE, described gate-controlled switch
s 1and gate-controlled switch
s 2close, gate-controlled switch simultaneously
s 3and gate-controlled switch
s 4conducting, described output voltage
v abe stored in the second potential storage circuit, described controllable switch S
2with S
3turn off, gate-controlled switch simultaneously
s 2,
s 4,
s 5with
s 6conducting simultaneously, the second adding circuit is by voltage
v awith voltage
v bEallbe added, output voltage
v o=
v a+
v bEall=
k*
Δ V bE+
v bEall, described voltage
v obe stored in described tertiary voltage memory circuit, described tertiary voltage memory circuit stores and keeps output voltage
v rEF=
v o=
v a+
v bEall=
k*
Δ V bE+
v beall.
When described potential storage circuit is electric capacity, described reference circuit as shown in Figure 2.In fig. 2,8 current sources are selected altogether, its benchmark core is consistent with schematic diagram, in actual treatment part, owing to selecting electric capacity as potential storage circuit, enormously simplify particular circuit configurations, because the input and output of electric capacity are at same port, the second gate-controlled switch group and the 3rd gate-controlled switch group can merge into a switches set.Due to voltage automatic average and storage on electric capacity parallel with one another, the average voltage memory circuit therefore described in Fig. 1 also merges with potential storage circuit group a, and gate-controlled switch
s 1also combine also with the second gate-controlled switch.Meanwhile, adopt operational amplifier can carry out gain and level plus-minus in the lump, principle is also consistent with Fig. 1, but simplifies circuit structure.
The concrete course of work is: state 1, gate-controlled switch
s a1,
s 0,
s 3,
s b1,
s 2,
s 4conducting, electric capacity
c 1charging; State 2, gate-controlled switch
s a2,
s 0,
s 3,
s b2,
s 2,
s 4conducting, electric capacity
c 2charging; State 3, gate-controlled switch
s a3,
s 0,
s 3,
s b3,
s 2,
s 4conducting, electric capacity
c 3charging; State 4, gate-controlled switch
s a4,
s 0,
s 3,
s b4,
s 2,
s 4conducting, electric capacity
c 4charging; State 5, gate-controlled switch
s a5,
s 0,
s 3,
s b5,
s 2,
s 4conducting, electric capacity
c 5charging; State 6, gate-controlled switch
s a6,
s 0,
s 3,
s b6,
s 2,
s 4conducting, electric capacity
c 6charging; State 7, gate-controlled switch
s a7,
s 0,
s 3,
s b7,
s 2,
s 4conducting, electric capacity
c 7charging; State 8, gate-controlled switch
s a8,
s 0,
s 3,
s b8,
s 2,
s 4conducting, electric capacity
c 8charging; State 9, gate-controlled switch
s a1-
s a8,
s 1,
s 3,
s 4,
s b1-
s b8conducting, electric capacity
c 1-
c 8average voltage, the voltage in potential storage circuit group is
v bE (Σ I/n), electric capacity
c 0to ground voltage be
v bE (Σ I), electric capacity
c 0both end voltage is
Δ V bE=
v bE (Σ I)-
v bE (Σ I/n); State 10, gate-controlled switch
s a1-
s a8,
s 0,
s 2,
s 3conducting, electric capacity
c 9both end voltage be (
c 1/
c 9) [
Δ V bE]=(
c 1/
c 9) (
kT/
q) ln (8), the voltage in potential storage circuit group is
v bE (Σ I); State 11,
s a1-
s a8,
s 1,
s 3,
s 5conducting, electric capacity
c lon voltage
v rEF=
v bE (Σ I)+ (
c 0/
c 9) (
kT/
q) ln (8).
The output waveform of the reference circuit shown in Fig. 2 as shown in Figure 3.Circuit needs a period of time just can enter normal workspace output voltage reference signal.
The problem that the present invention not only solves triode, resistance takies larger area, is controlled by high-frequency combination, also significantly can reduce the capacitance used.Described reference circuit is tied to produce by gauge tap turn-on sequence control BE and circuit is flow through different electric current thus produces different voltage and then reduce the use number of triode or diode, by the average evaluation of multichannel, guarantee that more high-precision reference voltage exports, there is great technological flexibility and stability, the present invention does not adopt resistance, can be compatible with Standard Digital CMOS, compatible strong.
Claims (4)
1. single BE ties a continuous output switch capacitor strap gap reference circuit, it is characterized in that: described reference circuit comprises current source group I, the first gate-controlled switch group S
a, BE knot produce circuit, the second gate-controlled switch group S
b, potential storage circuit group a, controllable switch S
0-S
6, the first potential storage circuit, average voltage memory circuit, the first adding circuit, gain circuitry K, the second potential storage circuit, the second adding circuit and tertiary voltage memory circuit, power vd D is successively through current source group I, the first gate-controlled switch group S
atie with BE the emitter producing circuit to be connected, BE knot produces the emitter first via of circuit successively through controllable switch S
0, the first potential storage circuit, controllable switch S
2be connected with the input end that subtracts of the first adding circuit, BE knot produces all the other roads of emitter of circuit successively through the second gate-controlled switch group S
b, potential storage circuit group a, average voltage memory circuit, controllable switch S 1 be connected with the input end that adds of the first adding circuit, the output terminal of the first adding circuit is successively through gain circuitry K, controllable switch S
3, the second potential storage circuit, controllable switch S
5add input end be connected with one of the second adding circuit, the first potential storage circuit and controllable switch S
2node through controllable switch S
4add input end with another of the second adding circuit to be connected, the output terminal of the second adding circuit is through controllable switch S
6be connected with one end of tertiary voltage memory circuit, the other end of tertiary voltage memory circuit is the voltage output end of described reference circuit.
2. single BE according to claim 1 ties continuous output switch capacitor strap gap reference circuit, it is characterized in that: described current source group I comprises several current sources I
n, described first gate-controlled switch group S
acomprise and described current source I
nthe controllable switch S that number is identical
an, described second gate-controlled switch group S
bcomprise and described current source I
nthe controllable switch S that number is identical
bn, described potential storage circuit group a comprises and described current source I
nthe potential storage circuit an that number is identical, current source I
1with controllable switch S
a1series connection, current source I
2with controllable switch S
a2series connection, the like, current source I
nwith controllable switch S
anseries connection, the current source I of series connection mutually
nand controllable switch S
anform some current source branch, above-mentioned some current source branch are parallel with one another; Controllable switch S
b1connect with potential storage circuit a1, controllable switch S
b2connect with potential storage circuit a2, the like, controllable switch S
bnconnect with potential storage circuit an, the controllable switch S of series connection mutually
bnform some store voltages branch roads with potential storage circuit an, above-mentioned some store voltages branch roads are parallel with one another, described n be more than or equal to 2 natural number.
3. single BE according to claim 2 ties continuous output switch capacitor strap gap reference circuit, it is characterized in that: described reference circuit also comprises the 3rd gate-controlled switch group S between average voltage memory circuit and potential storage circuit group a
c, described 3rd gate-controlled switch group S
ccomprise and described current source I
nthe controllable switch S that number is identical
cn, described controllable switch S
b1successively with potential storage circuit a1, controllable switch S
c1series connection, described controllable switch S
b2successively with potential storage circuit a2, controllable switch S
c2series connection, the like, described controllable switch S
bnsuccessively with potential storage circuit an, controllable switch S
cnseries connection, the controllable switch S of series connection mutually
bn, potential storage circuit an, controllable switch S
cnform some store voltages branch roads, above-mentioned some store voltages branch roads are parallel with one another, described n be more than or equal to 2 natural number.
4. single BE according to claim 1 ties continuous output switch capacitor strap gap reference circuit, it is characterized in that: described potential storage circuit is electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410780583.4A CN104571245B (en) | 2014-12-17 | 2014-12-17 | Single BE ties continuous output switch capacitor strap gap reference circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410780583.4A CN104571245B (en) | 2014-12-17 | 2014-12-17 | Single BE ties continuous output switch capacitor strap gap reference circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104571245A true CN104571245A (en) | 2015-04-29 |
| CN104571245B CN104571245B (en) | 2016-03-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410780583.4A Active CN104571245B (en) | 2014-12-17 | 2014-12-17 | Single BE ties continuous output switch capacitor strap gap reference circuit |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5563504A (en) * | 1994-05-09 | 1996-10-08 | Analog Devices, Inc. | Switching bandgap voltage reference |
| US7932772B1 (en) * | 2009-11-02 | 2011-04-26 | Delphia Technologies, Inc. | Curvature-compensated band-gap voltage reference circuit |
| CN102176183A (en) * | 2011-03-11 | 2011-09-07 | 苏州易能微电子科技有限公司 | Band-gap reference circuit of self-cancellation diode offset voltage |
| US8736354B2 (en) * | 2009-12-02 | 2014-05-27 | Texas Instruments Incorporated | Electronic device and method providing a voltage reference |
| CN103901934A (en) * | 2014-02-27 | 2014-07-02 | 开曼群岛威睿电通股份有限公司 | Reference voltage generation device |
-
2014
- 2014-12-17 CN CN201410780583.4A patent/CN104571245B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5563504A (en) * | 1994-05-09 | 1996-10-08 | Analog Devices, Inc. | Switching bandgap voltage reference |
| US7932772B1 (en) * | 2009-11-02 | 2011-04-26 | Delphia Technologies, Inc. | Curvature-compensated band-gap voltage reference circuit |
| US8736354B2 (en) * | 2009-12-02 | 2014-05-27 | Texas Instruments Incorporated | Electronic device and method providing a voltage reference |
| CN102176183A (en) * | 2011-03-11 | 2011-09-07 | 苏州易能微电子科技有限公司 | Band-gap reference circuit of self-cancellation diode offset voltage |
| CN103901934A (en) * | 2014-02-27 | 2014-07-02 | 开曼群岛威睿电通股份有限公司 | Reference voltage generation device |
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| Publication number | Publication date |
|---|---|
| CN104571245B (en) | 2016-03-02 |
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