CN104537666A - System and method for detecting chip packaging appearance defects - Google Patents
System and method for detecting chip packaging appearance defects Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
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Abstract
The invention discloses a system and method for detecting chip packaging appearance defects. The system comprises an image acquisition module and a multi-layer parallel processing framework, and the image acquisition module collects packaging appearance images of detected products. The multi-layer parallel processing framework comprises a two-dimensional whole parallel processing unit array, a one-dimensional whole parallel processing unit array, an array controller and a processor, wherein the two-dimensional whole parallel processing unit array comprises a plurality of pixel processing units and is used for carrying out parallel processing on the packaging appearance images of the products in a low level mode, the one-dimensional whole parallel processing unit array comprises a plurality of parallel processing units and is used for carrying out parallel processing on the results already processed by the two-dimensional whole parallel processing unit array in a middle level mode, the array controller is used for controlling the multi-layer parallel processing framework to execute corresponding actions according to instructions of a processor, and the processor judges whether the packaging appearance images of the products to be detected have defects or not according to the processing result of the one-dimensional whole parallel processing unit array. By means of the system and method, the chip packaging appearance defects can be rapidly detected.
Description
Technical field
The present invention relates to the detection of chip package open defect and the image processing field based on multi-level parallel processing architecture, particularly relate to a kind of fast chip based on multi-level parallel processing encapsulation open defect detection system.
Background technology
Final visual inspection is last important step that semi-conductor chip is produced, and by visual inspection, can find and remove the defect of chip outward appearance, while ensureing chip complete appearance, also can avoid the chip functions defect caused by chip appearance defects.Current most of semi-conductor chip factories commercial city adopts the final visual inspection manually carrying out product, and the subjectivity of people has had a strong impact on the correctness detected.Existing automatic detection system, be all generally detect based on computing machine or digital signal processor, due to the restriction of hardware, the velocity ratio of detection is lower, cannot meet the requirement of high-speed production.
Along with the fast development of infotech, utilize extensive high performance on-site programmable gate array (FPGA), the hardware system of digital signal processor (DSP) and flush bonding processor becomes study hotspot, but be limited to traditional frame system, be still difficult to reach balance in processing power, power consumption, each side such as real-time.
Summary of the invention
(1) technical matters that will solve
For above problem, the invention provides a kind of fast chip based on multi-level parallel processing encapsulation open defect detection system, this system, by the parallel processing architecture designed and the defects detection algorithm adapted with it, can realize the quick detection of chip package open defect.
(2) technical scheme
To achieve the above object, the invention provides a kind of product based on multi-level parallel processing encapsulation open defect detection system, it is characterized in that, this device comprises:
Image collection module, for gathering detected product encapsulation appearance images;
Multi-level parallel processing architecture, it comprises:
Two dimension full parellel pe array: it comprises multiple pixel processing unit, for parallel processing chip package appearance images, carries out low-level image process to it;
One dimension full parellel row relax cell array, it comprises multiple row relax unit, for the result of parallel processing after the process of described two-dimentional full parellel pe array low-level image, carries out intermediate image procossing to it;
Array control unit, it performs corresponding action for controlling described multi-level parallel processing architecture according to the instruction of processor;
Processor, it is according to the result of described one dimension full parellel row relax cell array, judges chip package outward appearance to be detected whether defectiveness.
Present invention also offers a kind of method utilizing the said goods encapsulation open defect detection system to carry out product appearance defects detection, it is characterized in that, comprising:
For gathering detected product encapsulation appearance images;
Parallel processing product encapsulation appearance images, carries out low-level image process to it;
The result of parallel processing after low-level image process, carries out intermediate image procossing to it;
According to the result of described intermediate image procossing, judge product to be detected encapsulation outward appearance whether defectiveness.
(3) beneficial effect
The chip package open defect rapid detection system based on multi-level parallel processing that the present invention proposes, comprise high speed imaging sensor 101, camera lens 102, light source 103, two-dimentional full parellel processing unit (PE) array 112, one dimension full parellel processing unit (RP) array 114, reduced instruction processor 119, and realize the high degree of parallelism algorithm that chip package open defect detects fast.The rudimentary process such as filtering, extraction edge of image is wherein completed by two-dimentional full parellel processing unit (PE) array 112, the extraction of characteristics of image is completed by one dimension full parellel processing unit (RP) array 114, reduced instruction processor 119 makes the result of defects detection by characteristic matching, and reduced instruction processor 119 pairs of whole systems carry out control and management simultaneously.Owing to the present invention is based on two-dimentional full parellel processing unit (PE) array 112 and one dimension full parellel processing unit (RP) array 114, the rudimentary of image and intermediate process can be completed fast, thus substantially increasing the speed of defects detection, its detection speed is more than 3 times of existing checkout equipment.
Accompanying drawing explanation
Fig. 1 is the encapsulation of the fast chip based on the multi-level parallel processing open defect detection system Organization Chart that the present invention proposes;
Fig. 2 is the example structure figure of two-dimentional full parellel processing unit PE in the present invention;
Fig. 3 is the example structure figure of one dimension full parellel processing unit RP in the present invention;
Fig. 4 is the fast chip encapsulation open defect detection method process flow diagram based on multi-level parallel processing in the present invention;
Fig. 5 is the process schematic that in the present invention, two-dimentional full parellel processing unit PE carries out processes pixel;
Fig. 6 (a) ~ (d) is defects detection effect schematic diagram in the present invention.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail.
If Fig. 1 is the encapsulation of the fast chip based on the multi-level parallel processing open defect detection system Organization Chart that the present invention proposes, comprising:
Image collection module 10, the picture rich in detail of the product that this module acquires is detected; And
Multi-level parallel processing apparatus 11, the product image that this device obtains according to described image collection module 10, by realization of High Speed defects detection algorithm, completes the detection of product appearance defect; Alternatively, described product can be semi-conductor chip.
In such scheme, described image collection module 10 comprises:
High speed imaging sensor 101, for catching the image of detected product;
Camera lens 102, for amplifying testing product and focusing on imageing sensor;
Light source 103, for irradiating detected product equably;
In such scheme, described multi-level parallel processing apparatus 11 comprises:
Image input module 111, for storing the entire image data of the product appearance that described image collection module 10 collects, and according to initial row pre-configured in array control unit 116, initial row, sampling interval, required part image data is delivered to described two-dimentional full parellel pe array 112;
Two dimension full parellel pe array 112, for receiving the view data that image input module 111 transmits, execution comprises the low-level image process such as filtering, Threshold segmentation, Morphological scale-space, edge extracting, and the view data after process is passed to one dimension full parellel pe array 114;
One dimension full parellel pe array 114, for receiving the view data of two-dimentional full parellel pe array 112, perform the intermediate image procossing such as summation, statistics with histogram, and the view data after having carried out intermediate image procossing is passed to reduced instruction processor 119;
Array control unit 116, input corresponding view data to two-dimentional full parellel pe array 112 for controlling image input module 111, and control two-dimentional full parellel pe array 112 and carry out low-level image process and one dimension full parellel pe array 114 carries out intermediate image procossing;
Reduced instruction processor 119, for receiving the image feature data of one dimension full parellel pe array 114, and making defects detection judgement by characteristic matching and identification, being responsible for sequential and the logic control of whole system simultaneously;
On-chip bus 117, for being mapped to other each buses from the gating enable signal needed for device blocks (as array control unit 116, input/output module 118 etc.) and physical address information, to drive from device blocks complete operation by from the read-write control signal of reduced instruction processor 119 and logical address;
Input/output module 118, for carrying out exchanges data with exterior PC;
The present invention is based on this multi-level parallel processing architecture and testing requirement, devise corresponding detection algorithm, first two-dimentional full parellel processing unit (PE) array is utilized to realize the pre-service of image to be detected, recycling one dimension full parellel processing unit (RP) array extracts the feature of image, finally utilize reduced instruction processor matching characteristic and make and detect judgement, whole process is owing to have employed a large amount of parallel processings, so speed is far faster than traditional checkout equipment.
Two-dimentional full parellel processing unit (PE) array 112 in Fig. 1 contains multiple pixel processing unit PE113.Each PE accepts identical instruction under being operated in single instruction multiple data (SIMD) pattern, performs identical operation, but the data of operation are from the storer of each PE this locality; Each PE can complete topography's operation of applicable full parellel process, as filtering, edge extracting, enhancing etc.The data of each PE can be transmitted alternately with the adjacent unit of its upper and lower, left and right, and transmitted by adjacent unit data repeatedly, each PE can produce with other PE of optional position alternately.Each PE can complete 1 bit summation, negate, the operation such as logical and, logical OR, the operation of many bits can be decomposed into above-mentioned 1 bit arithmetic and realize.
As devised the PE array of 64 × 64 in the present embodiment, image to be processed is 512 × 320, relative to the image block of 40 64 × 64, so provide a storer in image input module, view data in one frame is preserved, and PE array repeatedly can read the view data in same frame.In order to improve speed, when carrying out some algorithm, sub-sampling can be carried out to image, meanwhile, according to the defective item that will detect, if the defect of cover strip, then navigate to the lower edges part of image, if the defect of chip, then navigate to the center section of image, thus find interested part in image, only need carry out defects detection to part interested in image, when ensureing accuracy of detection, reducing calculated amount, shortening the processing time.
Be illustrated in figure 2 the example structure figure of two-dimentional full parellel processing unit PE.Described PE 113 comprises at least two input data selectors, 1 bit arithmetic logic units, a result selector switch, the storer of a 1 bit temporary register and 64 bits.Particularly, described processing unit PE (113) comprising:
An ALU 23, for realizing at least comprising summation to first operand and second operand, negates, with, phase or computing;
First operand selector switch 21, selects data as the first operand of 1 bit arithmetic logic arithmetic element according to the steering order of array control unit from the random access memory of this unit or adjacent unit;
Second operand selector switch 22, selects individual data as the second operand of 1 bit arithmetic logic arithmetic element according to the steering order of array control unit from the data or 1 bit immediate 0 and 1 of this unit 1 bit temporary register;
A 1 bit temporary register 24;
A random access memory 25.
Described 1bit ALU 23 comprises: full adder, not gate, two input and door, one two input or door, a 1 bit carry storage register and an Output rusults selector switch.
Under the steering order of array control unit 116, PE 113 selects to input data and arithmetical logic function accordingly, after completing computing, result stored in the storer of appropriate address or temporary register.PE array is suitable for filtering, extracts the computing that edge etc. is realized by template.As the edge utilizing PE array to extract vertical direction in image, only need 130 instructions, under the frequency of operation of 27 megahertzes, only need 48 microseconds.
One dimension full parellel processing unit (RP) array shown in Fig. 1 comprises multiple row relax unit R P115, wherein: all RP unit 115 receive identical instruction, complete identical operation, under being operated in single instruction multiple data (SIMD) pattern, the image procossing that applicable one dimension is parallel can be completed; Each RP unit 115 is connected with its upper and lower adjacent unit, can carry out the exchange of data.
Be illustrated in figure 3 the example structure figure of one dimension full parellel processing unit RP.Each RP 115 includes two input data selectors, 8 bit arithmetic logic units, a condition flag selector switch, a temporary register and storer.Particularly, described RP unit 115 comprises:
8 bit arithmetic unit 33;
First operand selector switch 31, for selecting data as the first operand of 8 bit arithmetic unit according to the steering order of array control unit from the register file or 8 bit immediates of local unit or adjacent unit;
Second operand selector switch 32, for selecting data as the second operand of 8 bit arithmetic unit according to the steering order of array control unit from buffer shift register and immediate 0.
Condition flag selector switch 34, it for selecting from carry flag, result mark, PE unit zone bit and 1, enable for writing of control RP115 register file;
The temporary register 36 of 8 bits, for the exchanges data between two-dimentional full parellel pe array 112 and one dimension full parellel pe array 114, simultaneously for the interface of on-chip bus 117 pairs of one dimension full parellel pe array 114 access.
A bit wide is the register file 35 of 8 bits, for preserving the result of 8 bit arithmetic unit 33;
Under the steering order of array control unit, RP selects corresponding input data and arithmetical logic function, after completing computing, result stored in the storer of appropriate address or temporary register.RP array can complete summation, the computings such as statistics with histogram, can complete feature extraction according to the data of PE array.
Shown reduced instruction (RISC) processor 119 comprises:
Reduced instruction (RISC) processor core;
A random ROM (read-only memory), for the program of storage compacting instruction processing unit core;
A random access memory, for storage and the reading of the data in reduced instruction processor core processing procedure.
Be illustrated in figure 4 the algorithm flow of defects detection.Defects detection algorithm comprises cover strip defect, chip character defect, chip pin defect independent design according to the project of required detection, and every one-step algorithm all has very high degree of parallelism.
First input image data, each view data can comprise the appearance images of multiple chip to be detected, so by extracting the border that vertical edge locates each chip from described image, complete segmentation and the location of chip.Here the Sobel template operator of 3 × 3 is adopted to carry out Vertical edge detection.Shown in (1), by the rim value calculating each point of the pixel in 3 × 3 neighborhoods.Ey (i, j) is outline map, and I (i, j) is original image.
Ey(i，j)＝|I(i-1，j-1)+2×I(i-1，j)+I(i-1，j+1)-I(i+1，j-1)
-2×I(i+1，j)-I(i+1，j+1)| (1)
Implementation procedure inside PE array as shown in Figure 5, convolutional calculation is carried out by Sobel operator and original image, obtain vertical edge image, the computation process of pixel corresponding to one of them PE unit is illustrate only in figure, this PE unit is added the twice of the gray-scale value of top left pixel, leftmost pixel gray-scale value, bottom left pixel gray-scale value, deduct the gray-scale value of upper right pixel again, deduct the twice of right pixels gray-scale value, deduct bottom right pixel gray-scale value, obtain the rim value of this pixel corresponding to PE unit.Actual all PE unit complete same operation all simultaneously, because PE array has the degree of parallelism of Pixel-level, i.e. and the corresponding pixel of each PE unit; So the computings such as edge extracting can be completed fast.The rim value of the single pixel of chip package appearance images described in all pixel processing unit parallel computations in described two-dimentional full parellel pe array, and whether be edge pixel point according to the rim value threshold value determination current pixel point preset, and form the edge pixel point representing matrix corresponding with pel array.Particularly, after every two PE obtain the rim value of each pixel, according to a suitable Threshold segmentation edge and background.Such as, if the rim value of current pixel point is greater than threshold value, is divided into the white point that gray-scale value is 255, represents with 1, otherwise think background, represent with 0.Then successively every column data of PE array is moved on to inside RP array, and ask often arrange and, and the row position being greater than certain threshold value is the marginal position of chip.The row position being greater than separatrix threshold value, to the every column element parallel summing in described edge pixel point representing matrix, is defined as chip separatrix by each row relax unit in described one dimension full parellel pe array.In order to reduce calculated amount, improve detection rates, before carrying out defects detection, find the pre-estimation defect area at various defect place, i.e. interested region, as the defect of cover strip is detected in the region in only detecting distance cover strip up-and-down boundary 64 pixel coverages, the up-and-down boundary of cover strip can be set here by PC.
For part interested in image, complete filtering and gray scale morphology process by PE array, smoothed image also gives prominence to the defect in image.Then Threshold segmentation is carried out by PE array, be white point by defect Segmentation, represent with 1, background segment is stain, represents with 0, then the number of RP array statistics white point, as the feature of defect, after risc processor obtains defect characteristic, the feature to be detected feature with the standard extracted before is compared, it is defectiveness that difference is greater than certain threshold decision, otherwise is judged as zero defect.
Be illustrated in figure 6 defects detection effect schematic diagram.This figure (a), (b), (c) have reacted the product with cover strip defect, figure (d) has reacted the product with pin defect, the result that it detects is shown in character frame below each product, if defectiveness is exactly " FAIL ", defect is not had to be exactly " PASS "
Based on multi-level parallel architecture, the detection that detection system of the present invention completes piece image only needs 36.8 milliseconds, and wherein the storage of entire image data accounts for 18 milliseconds, and the defects detection of cover strip defect and pin accounts for 18.6ms.Every width image comprises three chips, so can detect 80 chips p.s., speed is far away faster than traditional checkout equipment.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a product encapsulation open defect detection system, it is characterized in that, this device comprises:
Image collection module, for gathering detected product encapsulation appearance images;
Multi-level parallel processing architecture, it comprises:
Two dimension full parellel pe array, it comprises multiple pixel processing unit, for parallel processing product encapsulation appearance images, carries out low-level image process to it;
One dimension full parellel row relax cell array, it comprises multiple row relax unit, for the result of parallel processing after the process of described two-dimentional full parellel pe array low-level image, carries out intermediate image procossing to it;
Array control unit, it performs corresponding action for controlling described multi-level parallel processing architecture according to the instruction of processor;
Processor, it is according to the result of described one dimension full parellel row relax cell array, judges product to be detected encapsulation outward appearance whether defectiveness.
2. the system as claimed in claim 1, wherein, described low-level image process comprises carries out filtering, Threshold segmentation, Morphological scale-space and edge extraction operation to described product encapsulation appearance images.
3. system as claimed in claim 2, wherein, every column border pixel value that described intermediate image procossing comprises extracting from product encapsulation appearance images is sued for peace and statistics with histogram.
4. the system as claimed in claim 1, wherein, the rim value of the single pixel of product encapsulation appearance images described in all pixel processing unit parallel computations in described two-dimentional full parellel pe array, and whether be edge pixel point according to the rim value threshold value determination current pixel point preset, and form the edge pixel point representing matrix corresponding with pel array.
5. system as claimed in claim 4, wherein, the row position being greater than separatrix threshold value, to the every column element parallel summing in described edge pixel point representing matrix, is defined as product separatrix by each row relax unit in described one dimension full parellel pe array.
6. the system as described in claim 4 or 5, wherein, described two-dimentional full parellel pe array only processes the pre-estimation defect area in product encapsulation appearance images when extracting defect characteristic.
7. the system as described in any one of claim 1-5, wherein,
All pixel processing units receive identical instruction, complete identical operation, under being operated in simd mode;
Each pixel processing unit completes the arithmetic logical operation of 1 bit;
Each pixel processing unit and other any pixel processing units carry out exchanges data, wherein each pixel processing unit upper and lower, left and right adjacent thereto pixel processing unit is connected, by the transmission of neighborhood pixels processing unit data repeatedly, the exchanges data between any two pixel processing units can be realized.
8. the system as described in any one of claim 1-5, wherein said pixel processing unit comprises:
An ALU, for realizing at least comprising summation, negate, with, mutually or arithmetic logic computing;
First operand selector switch, selects data as the first operand of 1 bit arithmetic logic arithmetic element according to the steering order of array control unit from the random access memory of this pixel processing unit or neighborhood pixels processing unit;
Second operand selector switch, selects the data of this pixel processing unit 1 bit temporary register according to the steering order of array control unit, or a second operand as 1 bit arithmetic logic arithmetic element in 1 bit immediate 0,1;
A 1 bit temporary register;
A random access memory.
9. the system as described in any one of claim 1-5, wherein,
All row relax unit receive identical instruction, complete identical operation, under being operated in simd mode;
Each row relax unit is connected with its upper and lower adjacent unit, can carry out the exchange of data.
10. the system as described in any one of claim 1-5, wherein, described row relax unit R P comprises:
8 bit arithmetic unit;
First operand selector switch, for selecting data as the first operand of 8 bit arithmetic unit according to the steering order of array control unit from the register file or 8 bit immediates of one's own profession processing unit or adjacent row processing unit;
Second operand selector switch, for selecting data as the second operand of 8 bit arithmetic unit according to the steering order of array control unit from buffer shift register and immediate 0.
Condition flag selector switch, enable for writing of control register file.
The temporary register of 8 bits, for the exchanges data between two-dimentional full parellel pe array and one dimension full parellel pe array;
A bit wide is the register file of 8 bits, for preserving the operation result of 8 bit arithmetic unit.
11. 1 kinds of methods utilizing the encapsulation of the product described in any one of claim 1-10 open defect detection system to carry out product appearance defects detection, is characterized in that, comprising:
For gathering detected product encapsulation appearance images;
Parallel processing product encapsulation appearance images, carries out low-level image process to it;
The result of parallel processing after low-level image process, carries out intermediate image procossing to it;
According to the result of described intermediate image procossing, judge product to be detected encapsulation outward appearance whether defectiveness.
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