CN104506060A - Parallel-mode inverter - Google Patents
Parallel-mode inverter Download PDFInfo
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- CN104506060A CN104506060A CN201410633399.7A CN201410633399A CN104506060A CN 104506060 A CN104506060 A CN 104506060A CN 201410633399 A CN201410633399 A CN 201410633399A CN 104506060 A CN104506060 A CN 104506060A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
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Abstract
The invention relates to a parallel-mode inverter. The problem that the routine technique needs high-precision co-frequency sampling and a stable voltage follower is solved. The technical scheme is as follows: the inverter comprises a power distribution module, a CPU distribution management module, a self-synchronic output module, a constant current constant voltage drive module and a power conversion module, wherein the power distribution module is connected with an input end of the CPU distribution management module, an input end of the self-synchronic output module and an input end of the constant current constant voltage drive module; an output end of the CPU distribution management module is connected with a control end of the constant current constant voltage drive module, an output end of the constant current constant voltage drive module is connected with a control end of the power conversion module, an output end of the power conversion module is connected with the input end of the self-synchronic output module, and an output end of the self-synchronic output module is an output end of the parallel-mode inverter, and a feedback end of the self-synchronic output module is connected with a feedback input end of the CPU distribution management module. The output frequency can be automatically regulated along the power grid without using high-speed CPU operation.
Description
Technical field
The present invention is a kind of power supply change-over device, particularly relates to a kind of parallel operation inverter.
Background technology
Electrifiedly develop rapidly, require more and more higher to the capacity of electric power system, Performance And Reliability, the research also promoting power electronic technology deepens continuously.Multi-machine parallel connection realizes Large Copacity power supply and is acknowledged as one of important directions of current power conversion technical development.The capacity of single Inverter is very limited, dilatation is carried out by multiple wired in parallel, not only can make full use of the advantage of novel full control device for power switching, the volume of minimizing system, reduce noise, the dynamic responding speed of system and the versatility of inverter converter can also be improved.Conventional parallel operation inverter in conjunction with SPWM design, detects the Balance route of output voltage and electric current by high-speed dsp chip, high-precision same frequency sampling and stable voltage follower.This is all that larger cost is paid on software and hardware.Therefore develop a kind of need not CPU computing at a high speed, it is imperative that output frequency can follow the parallel operation inverter that electrical network regulates automatically.
China Patent Publication No.: CN1149785A, publication date on May 14th, 1997, disclose a kind of inverter, comprise input rectifier, input filter, output rectifier and output filter, between described input filter and output rectifier, be connected to the convertor circuit be made up of electronic switch and two elementary intermediate frequency transformer; The intermediate frequency transformer B that described convertor circuit comprises 4 electronic switch S1 ~ S4,8 diode D1 ~ D8,2 uptake pathway R1C1, R2C2 and is made up of 2 armature windings N1, N2 and N number of secondary winding; The positive pole of the upper termination power of described switch S 1, the lower end of S1 connects the left end of R1 in the negative electrode of diode D1, the anode of D5, the upper end of transformer B armature winding N1 and uptake pathway R1C1 respectively, the negative electrode of diode D5 and D2 connects the positive pole of power supply respectively, the anode of diode D2 connects the right-hand member of C1 in the upper end of switch S 2, the negative electrode of diode D6, the lower end of transformer B armature winding N1, uptake pathway R1C1 respectively, and the anode of the anode of diode D1, the lower end of switch S 2, diode D6 connects the negative pole of power supply respectively; The positive pole of the upper termination power of described switch S 3, the lower end of S3 connects the left end of R2 in the negative electrode of diode D3, the anode of D7, the lower end of transformer B armature winding N2, uptake pathway R2C2 respectively, the negative electrode of diode D7 and D4 connects the positive pole of power supply respectively, the anode of diode D4 connects the right-hand member of C2 in the upper end of switch S 4, the negative electrode of diode D8, the upper end of transformer B armature winding N2, uptake pathway R2C2 respectively, and the anode of the anode of diode D3, the lower end of switch S 4, diode D8 connects the negative pole of power supply respectively.Although this technical scheme can carry out inversion output, but this working method, need when being applied on conventional parallel operation inverter to be designed in conjunction with SPWM by high-speed dsp chip, detect the Balance route of output voltage and electric current, high-precision same frequency sampling and stable voltage follower.This is all that larger cost is paid on software and hardware.
Summary of the invention
The object of the invention is to deposit conventional parallel operation inverter designed in conjunction with SPWM by high-speed dsp chip for solving current technical scheme, detect the Balance route of output voltage and electric current, want high-precision same frequency sampling and stable voltage follower, this is all the problem that larger cost is paid on software and hardware, there is provided a kind of need not CPU computing at a high speed, output frequency can follow the parallel operation inverter that electrical network regulates automatically.
The technical solution adopted for the present invention to solve the technical problems is: a kind of parallel operation inverter, be converted to digital power by Power supply to power to digital element, comprise power distribution module, CPU allocation manager module, motor synchronizing output module, constant current constant voltage driver module and power conversion module, described power distribution module respectively with the input of CPU allocation manager module, the input of motor synchronizing output module is connected with the input of constant current constant voltage driver module, the output of CPU allocation manager module is connected with the control end of described constant current constant voltage driver module, the output of constant current constant voltage driver module is connected with the control end of power conversion module, the output of power conversion module is connected with the input of motor synchronizing output module, the output of motor synchronizing output module is the output of parallel operation inverter, the feedback end of motor synchronizing output module is connected with the feedback input end of described CPU allocation manager module.The present invention is made up of five parts; power distribution module: this part is the voltage outside input; distribute the constant voltage required for each module; reach the stable of system voltage, CPU allocation manager module, the high-low voltage parameter of CPU real-time judge power supply; control constant current constant voltage driver module protection machine to work under reliable voltage status; supply voltage is too high and too low, and the temperature of machine intimate is too high, with regard to the output of closing module drive singal.Can also the synchronizing voltage parameter of real-time tracking motor synchronizing output module, control constant current constant voltage driver module drive singal, regulation output voltage parameter.After electric network fault being detected, protect the drive singal of constant current constant voltage driver module at any time, ensure the safety of machine and electrical network.Constant current constant voltage driver module, the operating current of automatic detecting machine device, regulates drive singal, current constant in desired current range.When load is greater than the power output of parallel operation, automatically regulate the pulse duty cycle reducing drive singal, the electric energy controlling power conversion module exports, and completes the parallel operation electric current of inversion.The synchronizing voltage parameter of the second, real-time tracking CPU allocation manager module, stablizes embedding firmly output voltage source.Reach the electric energy controlling power conversion module to export, complete the parallel operation voltage of inverter.Power conversion module, real-time tracking performs the drive singal of constant current constant voltage driver module, and high frequency demodulation exports big current, voltage DC voltage.Motor synchronizing output module: by power network signal, bootstrapping synchronizing signal, driver output module, and synchronized parallel operation.Mains frequency motor synchronizing, the same frequency completing inverter exports.Do not need other to detect, and follow.Decrease hardware detection and the CPU software computing at a high speed of other complexity.Do the safe and reliable parallel operation that arrives to export.
As preferably, described motor synchronizing output module comprises resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, field effect transistor VT1, field effect transistor VT2, field effect transistor VT3, field effect transistor VT4, triode Q1, triode Q2, triode Q3, piezo-resistance RT1, piezo-resistance RT2, piezo-resistance RT3, optocoupler QU1, optocoupler QU2, voltage stabilizing didoe D1, voltage stabilizing didoe D2, voltage stabilizing didoe D7, voltage stabilizing didoe D11, diode D3, diode D4, diode D5, diode D6, diode D8, diode D9, diode D10, diode D12, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, common mode inductance LG, inductance L 1, power transformation resistance RT4 and fuse F1, the drain electrode of described field effect transistor VT1 is connected with the first output of power conversion module, the source electrode of described field effect transistor VT2 is connected with the second output of power conversion module, the source electrode of field effect transistor VT1 is connected with the drain electrode of field effect transistor VT2, the grid of field effect transistor VT1 is connected with the negative electrode of voltage stabilizing didoe D1, the anode of voltage stabilizing didoe D1 is connected with the source electrode of field effect transistor VT1, the negative electrode of voltage stabilizing didoe D1 is connected with the first end of resistance R1, second end of resistance R1 is connected with the first end of electric capacity C1, second end of electric capacity C1 is connected with the anode of voltage stabilizing didoe D1, second end of resistance R1 is connected with the negative electrode of diode D3, the anode of diode D3 is successively by resistance R3, resistance R9 is connected with the anode of diode D8, the negative electrode of diode D3 is connected with the anode of diode D4 by resistance R4, the negative electrode of diode D4 is connected with the anode of diode D3, the anode of diode D4 is connected with the base stage of triode Q1, the collector electrode of triode Q1 is connected with the grid of field effect transistor VT1, the emitter of triode Q1 is connected with the anode of voltage stabilizing didoe D1, the base stage of triode Q1 is connected with the negative electrode of diode D5, the anode of diode D5 is connected with the emitter of triode Q1, the base stage of triode Q1 is connected with the emitter of triode Q1 by electric capacity C2, the negative electrode of diode D6 is connected with the emitter of triode Q1, the anode of diode D6 is connected with the grid of field effect transistor VT2, the anode of diode D6 is connected with the negative electrode of diode D6 with resistance R5 by resistance R6, the anode of diode D6 is connected with the negative electrode of voltage stabilizing didoe D2 by resistance R2, the anode of voltage stabilizing didoe D2 is connected with the source electrode of field effect transistor VT2, the drain electrode of described field effect transistor VT4 is connected with the drain electrode of described field effect transistor VT1, the source electrode of described field effect transistor VT3 is connected with the source electrode of described field effect transistor VT2, the source electrode of field effect transistor VT4 is connected with the drain electrode of field effect transistor VT3, the grid of field effect transistor VT4 is connected with the negative electrode of voltage stabilizing didoe D7, the anode of voltage stabilizing didoe D7 is connected with the source electrode of field effect transistor VT4, the negative electrode of voltage stabilizing didoe D7 is connected with the first end of resistance R7, second end of resistance R7 is connected with the first end of electric capacity C3, second end of electric capacity C3 is connected with the anode of voltage stabilizing didoe D7, second end of resistance R7 is connected with the negative electrode of diode D8, the anode of diode D8 is successively by resistance R9, resistance R3 is connected with the anode of diode D3, the negative electrode of diode D8 is connected with the anode of diode D9 by resistance R10, the negative electrode of diode D9 is connected with the anode of diode D8, the anode of diode D9 is connected with the base stage of triode Q2, the collector electrode of triode Q2 is connected with the grid of field effect transistor VT4, the emitter of triode Q2 is connected with the anode of voltage stabilizing didoe D7, the base stage of triode Q2 is connected with the negative electrode of diode D10, the anode of diode D10 is connected with the emitter of triode Q2, the base stage of triode Q2 is connected with the emitter of triode Q2 by electric capacity C4, the negative electrode of diode D12 is connected with the emitter of triode Q2, the anode of diode D12 is connected with the grid of field effect transistor VT3, the anode of diode D12 is connected with the negative electrode of diode D12 with resistance R11 by resistance R12, the anode of diode D12 is connected with the negative electrode of voltage stabilizing didoe D11 by resistance R8, the anode of voltage stabilizing didoe D11 is connected with the source electrode of field effect transistor VT3, the emitter of triode Q1 is connected with the first input end of common mode inductance L G, the emitter of triode Q1 is connected with second input of common mode inductance L G by inductance L 1, first output of common mode inductance LG is connected with the protective earthing interface of motor synchronizing output module by electric capacity C7, protective earthing interface is respectively by electric capacity C5 and electric capacity C6 ground connection, electric capacity C8 is connected with between first output of common mode inductance LG and second output of common mode inductance LG, first output of common mode inductance LG is connected with the zero line interface of motor synchronizing output module, second output of common mode inductance LG passes through the first end of fuse F1 and piezo-resistance RT1, the first end of piezo-resistance RT2 is connected with the first end of piezo-resistance RT3, second end of piezo-resistance RT1, second end of piezo-resistance RT2 is connected with the phase line interface of motor synchronizing output module with second end of piezo-resistance RT3, first output of common mode inductance LG is connected with second input of second input of optocoupler QU1 and optocoupler QU2, second output of common mode inductance LG is connected with the first input end of the first input end of optocoupler QU1 and optocoupler QU2, first conduction terminal of optocoupler QU1 is respectively by resistance R18 and electric capacity C10 ground connection, first conduction terminal of optocoupler QU1 is connected with digital power with resistance R19 by power transformation resistance RT4 successively, second conduction terminal of optocoupler QU2 is connected with second conduction terminal of optocoupler QU1, the second conduction terminal ground connection of optocoupler QU2, first conduction terminal of optocoupler QU2 is connected with triode Q3 base stage by resistance R17, digital power is connected with the collector electrode of triode Q3 by resistance R15, digital power is connected with first conduction terminal of optocoupler QU2 by resistance R16, be connected by electric capacity C9 between the collector electrode of triode Q3 and the emitter of triode Q3, the collector electrode of triode Q3 is connected with a port of CPU allocation manager module.
As preferably, described constant current constant voltage driver module comprises resonance control chip U1, operation amplifier chip U2, triode Q4, triode Q5, triode Q6, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, resistance R35, resistance R36, resistance R37, resistance R38, power transformation resistance RT5, electric capacity C11, electric capacity C12, electric capacity C13, electric capacity C14, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, diode D13, diode D14, diode D15 and diode D16, the emitter of triode Q4 is by resistance R20 ground connection, the base stage of triode Q4 is connected with the collector electrode of triode Q4 by resistance R23, the collector electrode of triode Q4 connects digitally by electric capacity C11, the collector electrode of triode Q4 is held with the CURLIM of resonance control chip U1 by resistance R21 and is connected, the collector electrode of triode Q4 is also held with the VREF of resonance control chip U1 and is connected, the base stage of triode Q4 to be held with the CT of resonance control chip U1 by diode D13 and diode D14 successively and is connected, the CT end of resonance control chip U1 is by electric capacity C12 ground connection, the CS-of resonance control chip U1 holds ground connection, the CS+ end of resonance control chip U1 is successively by resistance R22 and resistance R20 ground connection, the NI end of resonance control chip U1 is connected with the first end of resistance R27, the first end of resistance R27 is respectively by electric capacity C15 and resistance R26 ground connection, second end of resistance R27 is respectively by resistance R25 and electric capacity C16 ground connection, second end of resistance R27 is electrically connected with a port of CPU allocation manager module by resistance R28, the INV end of resonance control chip U1 respectively with the first end of electric capacity C13, the first end of electric capacity C14, the first end of electric capacity C7 and the first end of resistance R29 connect, second end of electric capacity C13 is connected with second end of electric capacity C14 by resistance R24, second end of electric capacity C14 is connected with the COMP of resonance control chip U1, second end of electric capacity C17 is held with the OUTB of operation amplifier chip U2 by resistance R30 and is connected, second end of resistance R29 is held with the OUTB of operation amplifier chip U2 and is connected, and second end of resistance R29 is also successively by resistance R31, power transformation resistance RT5 and resistance R32 ground connection, second end of resistance R29 is also connected with the first end of electric capacity C18, second end of electric capacity C18 is held with the INB-of operation amplifier chip U2 and is connected, second end of electric capacity C18 is by resistance R32 ground connection, the INB+ end of operation amplifier chip U2 connects digitally by resistance R33, the INB+ end of operation amplifier chip U2 to be held with the GND of operation amplifier chip U2 by electric capacity C19 and is connected, the SHUTDOWM end of resonance control chip U1 is electrically connected with a port of CPU allocation manager module, the VIN end of resonance control chip U1 is connected with digital power, the VIN end of resonance control chip U1 is respectively by electric capacity C20 and electric capacity C21 ground connection, the VIN end of resonance control chip U1 is held with the VC of resonance control chip U1 and is connected, the BOUT end of resonance control chip U1 is connected with the base stage of triode Q5 by resistance R35, be connected by resistance R37 between the collector electrode of triode Q5 and the base stage of triode Q5, the base stage of triode Q5 is connected with the anode of diode D15, the negative electrode of diode D15 is connected with the emitter of triode Q5, the collector electrode of triode Q5 is connected with power conversion module pwm signal port, the collector electrode of triode Q5 connects digitally, the GND of resonance control chip U1 holds ground connection, the AOUT end of resonance control chip U1 is connected with the base stage of triode Q6 by resistance R36, the collector electrode of triode Q6 connects digitally, be connected by resistance R38 between the base stage of triode Q6 and the collector electrode of triode Q6, the base stage of triode Q6 is connected with the anode of diode D16, the emitter of triode Q6 is connected with the negative electrode of diode D16, the emitter of triode Q6 is connected with another pwm signal port of power conversion module, the RT end of resonance control chip U1 is by resistance R34 ground connection.
As preferably, described resonance control chip U1 is UCC2806DW chip.Apply this chip cost lower.
As preferably, described operation amplifier chip U2 is LM358 chip.Apply this chip cost lower.
Substantial effect of the present invention is: need not CPU computing at a high speed, and output frequency automatically can be followed electrical network and be regulated.
Accompanying drawing explanation
Fig. 1 is a kind of frame structure schematic diagram in the present invention;
Fig. 2 is the circuit theory diagrams of motor synchronizing output module in the present invention;
Fig. 3 is the circuit theory diagrams of constant current constant voltage driver module in the present invention;
Fig. 4 is the circuit theory schematic diagram of the power conversion module in the present invention;
Fig. 5 is the circuit theory schematic diagram of the CPU allocation manager module in the present invention.
In figure: 1, power distribution module, 2, CPU allocation manager module, 3, constant current constant voltage driver module, 4, motor synchronizing output module, 5, power conversion module.
Embodiment
Below by specific embodiment, and by reference to the accompanying drawings, technical scheme of the present invention is described in further detail.
Embodiment:
A kind of parallel operation inverter is (see accompanying drawing 1, accompanying drawing 2, accompanying drawing 3, accompanying drawing 4 and accompanying drawing 5), be converted to digital power by Power supply to power to digital element, comprise power distribution module, CPU allocation manager module, motor synchronizing output module, constant current constant voltage driver module and power conversion module, described power distribution module respectively with the input of CPU allocation manager module, the input of motor synchronizing output module is connected with the input of constant current constant voltage driver module, the output of CPU allocation manager module is connected with the control end of described constant current constant voltage driver module, the output of constant current constant voltage driver module is connected with the control end of power conversion module, the output of power conversion module is connected with the input of motor synchronizing output module, the output of motor synchronizing output module is the output of parallel operation inverter, the feedback end of motor synchronizing output module is connected with the feedback input end of described CPU allocation manager module.Described motor synchronizing output module comprises resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, field effect transistor VT1, field effect transistor VT2, field effect transistor VT3, field effect transistor VT4, triode Q1, triode Q2, triode Q3, piezo-resistance RT1, piezo-resistance RT2, piezo-resistance RT3, optocoupler QU1, optocoupler QU2, voltage stabilizing didoe D1, voltage stabilizing didoe D2, voltage stabilizing didoe D7, voltage stabilizing didoe D11, diode D3, diode D4, diode D5, diode D6, diode D8, diode D9, diode D10, diode D12, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, common mode inductance LG, inductance L 1, power transformation resistance RT4 and fuse F1, the drain electrode of described field effect transistor VT1 is connected with the first output of power conversion module, the source electrode of described field effect transistor VT2 is connected with the second output of power conversion module, the source electrode of field effect transistor VT1 is connected with the drain electrode of field effect transistor VT2, the grid of field effect transistor VT1 is connected with the negative electrode of voltage stabilizing didoe D1, the anode of voltage stabilizing didoe D1 is connected with the source electrode of field effect transistor VT1, the negative electrode of voltage stabilizing didoe D1 is connected with the first end of resistance R1, second end of resistance R1 is connected with the first end of electric capacity C1, second end of electric capacity C1 is connected with the anode of voltage stabilizing didoe D1, second end of resistance R1 is connected with the negative electrode of diode D3, the anode of diode D3 is successively by resistance R3, resistance R9 is connected with the anode of diode D8, the negative electrode of diode D3 is connected with the anode of diode D4 by resistance R4, the negative electrode of diode D4 is connected with the anode of diode D3, the anode of diode D4 is connected with the base stage of triode Q1, the collector electrode of triode Q1 is connected with the grid of field effect transistor VT1, the emitter of triode Q1 is connected with the anode of voltage stabilizing didoe D1, the base stage of triode Q1 is connected with the negative electrode of diode D5, the anode of diode D5 is connected with the emitter of triode Q1, the base stage of triode Q1 is connected with the emitter of triode Q1 by electric capacity C2, the negative electrode of diode D6 is connected with the emitter of triode Q1, the anode of diode D6 is connected with the grid of field effect transistor VT2, the anode of diode D6 is connected with the negative electrode of diode D6 with resistance R5 by resistance R6, the anode of diode D6 is connected with the negative electrode of voltage stabilizing didoe D2 by resistance R2, the anode of voltage stabilizing didoe D2 is connected with the source electrode of field effect transistor VT2, the drain electrode of described field effect transistor VT4 is connected with the drain electrode of described field effect transistor VT1, the source electrode of described field effect transistor VT3 is connected with the source electrode of described field effect transistor VT2, the source electrode of field effect transistor VT4 is connected with the drain electrode of field effect transistor VT3, the grid of field effect transistor VT4 is connected with the negative electrode of voltage stabilizing didoe D7, the anode of voltage stabilizing didoe D7 is connected with the source electrode of field effect transistor VT4, the negative electrode of voltage stabilizing didoe D7 is connected with the first end of resistance R7, second end of resistance R7 is connected with the first end of electric capacity C3, second end of electric capacity C3 is connected with the anode of voltage stabilizing didoe D7, second end of resistance R7 is connected with the negative electrode of diode D8, the anode of diode D8 is successively by resistance R9, resistance R3 is connected with the anode of diode D3, the negative electrode of diode D8 is connected with the anode of diode D9 by resistance R10, the negative electrode of diode D9 is connected with the anode of diode D8, the anode of diode D9 is connected with the base stage of triode Q2, the collector electrode of triode Q2 is connected with the grid of field effect transistor VT4, the emitter of triode Q2 is connected with the anode of voltage stabilizing didoe D7, the base stage of triode Q2 is connected with the negative electrode of diode D10, the anode of diode D10 is connected with the emitter of triode Q2, the base stage of triode Q2 is connected with the emitter of triode Q2 by electric capacity C4, the negative electrode of diode D12 is connected with the emitter of triode Q2, the anode of diode D12 is connected with the grid of field effect transistor VT3, the anode of diode D12 is connected with the negative electrode of diode D12 with resistance R11 by resistance R12, the anode of diode D12 is connected with the negative electrode of voltage stabilizing didoe D11 by resistance R8, the anode of voltage stabilizing didoe D11 is connected with the source electrode of field effect transistor VT3, the emitter of triode Q1 is connected with the first input end of common mode inductance L G, the emitter of triode Q1 is connected with second input of common mode inductance L G by inductance L 1, first output of common mode inductance LG is connected with the protective earthing interface of motor synchronizing output module by electric capacity C7, protective earthing interface is respectively by electric capacity C5 and electric capacity C6 ground connection, electric capacity C8 is connected with between first output of common mode inductance LG and second output of common mode inductance LG, first output of common mode inductance LG is connected with the zero line interface of motor synchronizing output module, second output of common mode inductance LG passes through the first end of fuse F1 and piezo-resistance RT1, the first end of piezo-resistance RT2 is connected with the first end of piezo-resistance RT3, second end of piezo-resistance RT1, second end of piezo-resistance RT2 is connected with the phase line interface of motor synchronizing output module with second end of piezo-resistance RT3, first output of common mode inductance LG is connected with second input of second input of optocoupler QU1 and optocoupler QU2, second output of common mode inductance LG is connected with the first input end of the first input end of optocoupler QU1 and optocoupler QU2, first conduction terminal of optocoupler QU1 is respectively by resistance R18 and electric capacity C10 ground connection, first conduction terminal of optocoupler QU1 is connected with digital power with resistance R19 by power transformation resistance RT4 successively, second conduction terminal of optocoupler QU2 is connected with second conduction terminal of optocoupler QU1, the second conduction terminal ground connection of optocoupler QU2, first conduction terminal of optocoupler QU2 is connected with triode Q3 base stage by resistance R17, digital power is connected with the collector electrode of triode Q3 by resistance R15, digital power is connected with first conduction terminal of optocoupler QU2 by resistance R16, be connected by electric capacity C9 between the collector electrode of triode Q3 and the emitter of triode Q3, the collector electrode of triode Q3 is connected with a port of CPU allocation manager module.Described constant current constant voltage driver module comprises resonance control chip U1, operation amplifier chip U2, triode Q4, triode Q5, triode Q6, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, resistance R35, resistance R36, resistance R37, resistance R38, power transformation resistance RT5, electric capacity C11, electric capacity C12, electric capacity C13, electric capacity C14, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, diode D13, diode D14, diode D15 and diode D16, the emitter of triode Q4 is by resistance R20 ground connection, the base stage of triode Q4 is connected with the collector electrode of triode Q4 by resistance R23, the collector electrode of triode Q4 connects digitally by electric capacity C11, the collector electrode of triode Q4 is held with the CURLIM of resonance control chip U1 by resistance R21 and is connected, the collector electrode of triode Q4 is also held with the VREF of resonance control chip U1 and is connected, the base stage of triode Q4 to be held with the CT of resonance control chip U1 by diode D13 and diode D14 successively and is connected, the CT end of resonance control chip U1 is by electric capacity C12 ground connection, the CS-of resonance control chip U1 holds ground connection, the CS+ end of resonance control chip U1 is successively by resistance R22 and resistance R20 ground connection, the NI end of resonance control chip U1 is connected with the first end of resistance R27, the first end of resistance R27 is respectively by electric capacity C15 and resistance R26 ground connection, second end of resistance R27 is respectively by resistance R25 and electric capacity C16 ground connection, second end of resistance R27 is electrically connected with a port of CPU allocation manager module by resistance R28, the INV end of resonance control chip U1 respectively with the first end of electric capacity C13, the first end of electric capacity C14, the first end of electric capacity C7 and the first end of resistance R29 connect, second end of electric capacity C13 is connected with second end of electric capacity C14 by resistance R24, second end of electric capacity C14 is connected with the COMP of resonance control chip U1, second end of electric capacity C17 is held with the OUTB of operation amplifier chip U2 by resistance R30 and is connected, second end of resistance R29 is held with the OUTB of operation amplifier chip U2 and is connected, and second end of resistance R29 is also successively by resistance R31, power transformation resistance RT5 and resistance R32 ground connection, second end of resistance R29 is also connected with the first end of electric capacity C18, second end of electric capacity C18 is held with the INB-of operation amplifier chip U2 and is connected, second end of electric capacity C18 is by resistance R32 ground connection, the INB+ end of operation amplifier chip U2 connects digitally by resistance R33, the INB+ end of operation amplifier chip U2 to be held with the GND of operation amplifier chip U2 by electric capacity C19 and is connected, the SHUTDOWM end of resonance control chip U1 is electrically connected with a port of CPU allocation manager module, the VIN end of resonance control chip U1 is connected with digital power, the VIN end of resonance control chip U1 is respectively by electric capacity C20 and electric capacity C21 ground connection, the VIN end of resonance control chip U1 is held with the VC of resonance control chip U1 and is connected, the BOUT end of resonance control chip U1 is connected with the base stage of triode Q5 by resistance R35, be connected by resistance R37 between the collector electrode of triode Q5 and the base stage of triode Q5, the base stage of triode Q5 is connected with the anode of diode D15, the negative electrode of diode D15 is connected with the emitter of triode Q5, the collector electrode of triode Q5 is connected with power conversion module pwm signal port, the collector electrode of triode Q5 connects digitally, the GND of resonance control chip U1 holds ground connection, the AOUT end of resonance control chip U1 is connected with the base stage of triode Q6 by resistance R36, the collector electrode of triode Q6 connects digitally, be connected by resistance R38 between the base stage of triode Q6 and the collector electrode of triode Q6, the base stage of triode Q6 is connected with the anode of diode D16, the emitter of triode Q6 is connected with the negative electrode of diode D16, the emitter of triode Q6 is connected with another pwm signal port of power conversion module, the RT end of resonance control chip U1 is by resistance R34 ground connection.Described resonance control chip U1 is UCC2806DW chip.Described operation amplifier chip U2 is LM358 chip.
The present invention is made up of five parts; power distribution module: this part is the voltage outside input; distribute the constant voltage required for each module; reach the stable of system voltage, CPU allocation manager module, the high-low voltage parameter of CPU real-time judge power supply; control constant current constant voltage driver module protection machine to work under reliable voltage status; supply voltage is too high and too low, and the temperature of machine intimate is too high, with regard to the output of closing module drive singal.Can also the synchronizing voltage parameter of real-time tracking motor synchronizing output module, control constant current constant voltage driver module drive singal, regulation output voltage parameter.After electric network fault being detected, protect the drive singal of constant current constant voltage driver module at any time, ensure the safety of machine and electrical network.Constant current constant voltage driver module, the operating current of automatic detecting machine device, regulates drive singal, current constant in desired current range.When load is greater than the power output of parallel operation, automatically regulate the pulse duty cycle reducing drive singal, the electric energy controlling power conversion module exports, and completes the parallel operation electric current of inversion.The synchronizing voltage parameter of the second, real-time tracking CPU allocation manager module, stablizes embedding firmly output voltage source.Reach the electric energy controlling power conversion module to export, complete the parallel operation voltage of inverter.Power conversion module, real-time tracking performs the drive singal of constant current constant voltage driver module, and high frequency demodulation exports big current, voltage DC voltage.Motor synchronizing output module: by power network signal, bootstrapping synchronizing signal, driver output module, and synchronized parallel operation.Mains frequency motor synchronizing, the same frequency completing inverter exports.Do not need other to detect, and follow.Decrease hardware detection and the CPU software computing at a high speed of other complexity.Do the safe and reliable parallel operation that arrives to export.
Above-described embodiment is one of the present invention preferably scheme, not does any pro forma restriction to the present invention, also has other variant and remodeling under the prerequisite not exceeding the technical scheme described in claim.
Claims (5)
1. a parallel operation inverter, be converted to digital power by Power supply to power to digital element, it is characterized in that: comprise power distribution module, CPU allocation manager module, motor synchronizing output module, constant current constant voltage driver module and power conversion module, described power distribution module respectively with the input of CPU allocation manager module, the input of motor synchronizing output module is connected with the input of constant current constant voltage driver module, the output of CPU allocation manager module is connected with the control end of described constant current constant voltage driver module, the output of constant current constant voltage driver module is connected with the control end of power conversion module, the output of power conversion module is connected with the input of motor synchronizing output module, the output of motor synchronizing output module is the output of parallel operation inverter, the feedback end of motor synchronizing output module is connected with the feedback input end of described CPU allocation manager module.
2. parallel operation inverter according to claim 1, it is characterized in that: described motor synchronizing output module comprises resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, field effect transistor VT1, field effect transistor VT2, field effect transistor VT3, field effect transistor VT4, triode Q1, triode Q2, triode Q3, piezo-resistance RT1, piezo-resistance RT2, piezo-resistance RT3, optocoupler QU1, optocoupler QU2, voltage stabilizing didoe D1, voltage stabilizing didoe D2, voltage stabilizing didoe D7, voltage stabilizing didoe D11, diode D3, diode D4, diode D5, diode D6, diode D8, diode D9, diode D10, diode D12, electric capacity C1, electric capacity C2, electric capacity C3, electric capacity C4, electric capacity C5, electric capacity C6, electric capacity C7, electric capacity C8, electric capacity C9, electric capacity C10, common mode inductance LG, inductance L 1, power transformation resistance RT4 and fuse F1, the drain electrode of described field effect transistor VT1 is connected with the first output of power conversion module, the source electrode of described field effect transistor VT2 is connected with the second output of power conversion module, the source electrode of field effect transistor VT1 is connected with the drain electrode of field effect transistor VT2, the grid of field effect transistor VT1 is connected with the negative electrode of voltage stabilizing didoe D1, the anode of voltage stabilizing didoe D1 is connected with the source electrode of field effect transistor VT1, the negative electrode of voltage stabilizing didoe D1 is connected with the first end of resistance R1, second end of resistance R1 is connected with the first end of electric capacity C1, second end of electric capacity C1 is connected with the anode of voltage stabilizing didoe D1, second end of resistance R1 is connected with the negative electrode of diode D3, the anode of diode D3 is successively by resistance R3, resistance R9 is connected with the anode of diode D8, the negative electrode of diode D3 is connected with the anode of diode D4 by resistance R4, the negative electrode of diode D4 is connected with the anode of diode D3, the anode of diode D4 is connected with the base stage of triode Q1, the collector electrode of triode Q1 is connected with the grid of field effect transistor VT1, the emitter of triode Q1 is connected with the anode of voltage stabilizing didoe D1, the base stage of triode Q1 is connected with the negative electrode of diode D5, the anode of diode D5 is connected with the emitter of triode Q1, the base stage of triode Q1 is connected with the emitter of triode Q1 by electric capacity C2, the negative electrode of diode D6 is connected with the emitter of triode Q1, the anode of diode D6 is connected with the grid of field effect transistor VT2, the anode of diode D6 is connected with the negative electrode of diode D6 with resistance R5 by resistance R6, the anode of diode D6 is connected with the negative electrode of voltage stabilizing didoe D2 by resistance R2, the anode of voltage stabilizing didoe D2 is connected with the source electrode of field effect transistor VT2, the drain electrode of described field effect transistor VT4 is connected with the drain electrode of described field effect transistor VT1, the source electrode of described field effect transistor VT3 is connected with the source electrode of described field effect transistor VT2, the source electrode of field effect transistor VT4 is connected with the drain electrode of field effect transistor VT3, the grid of field effect transistor VT4 is connected with the negative electrode of voltage stabilizing didoe D7, the anode of voltage stabilizing didoe D7 is connected with the source electrode of field effect transistor VT4, the negative electrode of voltage stabilizing didoe D7 is connected with the first end of resistance R7, second end of resistance R7 is connected with the first end of electric capacity C3, second end of electric capacity C3 is connected with the anode of voltage stabilizing didoe D7, second end of resistance R7 is connected with the negative electrode of diode D8, the anode of diode D8 is successively by resistance R9, resistance R3 is connected with the anode of diode D3, the negative electrode of diode D8 is connected with the anode of diode D9 by resistance R10, the negative electrode of diode D9 is connected with the anode of diode D8, the anode of diode D9 is connected with the base stage of triode Q2, the collector electrode of triode Q2 is connected with the grid of field effect transistor VT4, the emitter of triode Q2 is connected with the anode of voltage stabilizing didoe D7, the base stage of triode Q2 is connected with the negative electrode of diode D10, the anode of diode D10 is connected with the emitter of triode Q2, the base stage of triode Q2 is connected with the emitter of triode Q2 by electric capacity C4, the negative electrode of diode D12 is connected with the emitter of triode Q2, the anode of diode D12 is connected with the grid of field effect transistor VT3, the anode of diode D12 is connected with the negative electrode of diode D12 with resistance R11 by resistance R12, the anode of diode D12 is connected with the negative electrode of voltage stabilizing didoe D11 by resistance R8, the anode of voltage stabilizing didoe D11 is connected with the source electrode of field effect transistor VT3, the emitter of triode Q1 is connected with the first input end of common mode inductance L G, the emitter of triode Q1 is connected with second input of common mode inductance L G by inductance L 1, first output of common mode inductance LG is connected with the protective earthing interface of motor synchronizing output module by electric capacity C7, protective earthing interface is respectively by electric capacity C5 and electric capacity C6 ground connection, electric capacity C8 is connected with between first output of common mode inductance LG and second output of common mode inductance LG, first output of common mode inductance LG is connected with the zero line interface of motor synchronizing output module, second output of common mode inductance LG passes through the first end of fuse F1 and piezo-resistance RT1, the first end of piezo-resistance RT2 is connected with the first end of piezo-resistance RT3, second end of piezo-resistance RT1, second end of piezo-resistance RT2 is connected with the phase line interface of motor synchronizing output module with second end of piezo-resistance RT3, first output of common mode inductance LG is connected with second input of second input of optocoupler QU1 and optocoupler QU2, second output of common mode inductance LG is connected with the first input end of the first input end of optocoupler QU1 and optocoupler QU2, first conduction terminal of optocoupler QU1 is respectively by resistance R18 and electric capacity C10 ground connection, first conduction terminal of optocoupler QU1 is connected with digital power with resistance R19 by power transformation resistance RT4 successively, second conduction terminal of optocoupler QU2 is connected with second conduction terminal of optocoupler QU1, the second conduction terminal ground connection of optocoupler QU2, first conduction terminal of optocoupler QU2 is connected with triode Q3 base stage by resistance R17, digital power is connected with the collector electrode of triode Q3 by resistance R15, digital power is connected with first conduction terminal of optocoupler QU2 by resistance R16, be connected by electric capacity C9 between the collector electrode of triode Q3 and the emitter of triode Q3, the collector electrode of triode Q3 is connected with a port of CPU allocation manager module.
3. parallel operation inverter according to claim 1, is characterized in that: described constant current constant voltage driver module comprises resonance control chip U1, operation amplifier chip U2, triode Q4, triode Q5, triode Q6, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, resistance R26, resistance R27, resistance R28, resistance R29, resistance R30, resistance R31, resistance R32, resistance R33, resistance R34, resistance R35, resistance R36, resistance R37, resistance R38, power transformation resistance RT5, electric capacity C11, electric capacity C12, electric capacity C13, electric capacity C14, electric capacity C15, electric capacity C16, electric capacity C17, electric capacity C18, electric capacity C19, electric capacity C20, electric capacity C21, diode D13, diode D14, diode D15 and diode D16, the emitter of triode Q4 is by resistance R20 ground connection, the base stage of triode Q4 is connected with the collector electrode of triode Q4 by resistance R23, the collector electrode of triode Q4 connects digitally by electric capacity C11, the collector electrode of triode Q4 is held with the CURLIM of resonance control chip U1 by resistance R21 and is connected, the collector electrode of triode Q4 is also held with the VREF of resonance control chip U1 and is connected, the base stage of triode Q4 to be held with the CT of resonance control chip U1 by diode D13 and diode D14 successively and is connected, the CT end of resonance control chip U1 is by electric capacity C12 ground connection, the CS-of resonance control chip U1 holds ground connection, the CS+ end of resonance control chip U1 is successively by resistance R22 and resistance R20 ground connection, the NI end of resonance control chip U1 is connected with the first end of resistance R27, the first end of resistance R27 is respectively by electric capacity C15 and resistance R26 ground connection, second end of resistance R27 is respectively by resistance R25 and electric capacity C16 ground connection, second end of resistance R27 is electrically connected with a port of CPU allocation manager module by resistance R28, the INV end of resonance control chip U1 respectively with the first end of electric capacity C13, the first end of electric capacity C14, the first end of electric capacity C7 and the first end of resistance R29 connect, second end of electric capacity C13 is connected with second end of electric capacity C14 by resistance R24, second end of electric capacity C14 is connected with the COMP of resonance control chip U1, second end of electric capacity C17 is held with the OUTB of operation amplifier chip U2 by resistance R30 and is connected, second end of resistance R29 is held with the OUTB of operation amplifier chip U2 and is connected, and second end of resistance R29 is also successively by resistance R31, power transformation resistance RT5 and resistance R32 ground connection, second end of resistance R29 is also connected with the first end of electric capacity C18, second end of electric capacity C18 is held with the INB-of operation amplifier chip U2 and is connected, second end of electric capacity C18 is by resistance R32 ground connection, the INB+ end of operation amplifier chip U2 connects digitally by resistance R33, the INB+ end of operation amplifier chip U2 to be held with the GND of operation amplifier chip U2 by electric capacity C19 and is connected, the SHUTDOWM end of resonance control chip U1 is electrically connected with a port of CPU allocation manager module, the VIN end of resonance control chip U1 is connected with digital power, the VIN end of resonance control chip U1 is respectively by electric capacity C20 and electric capacity C21 ground connection, the VIN end of resonance control chip U1 is held with the VC of resonance control chip U1 and is connected, the BOUT end of resonance control chip U1 is connected with the base stage of triode Q5 by resistance R35, be connected by resistance R37 between the collector electrode of triode Q5 and the base stage of triode Q5, the base stage of triode Q5 is connected with the anode of diode D15, the negative electrode of diode D15 is connected with the emitter of triode Q5, the collector electrode of triode Q5 is connected with power conversion module pwm signal port, the collector electrode of triode Q5 connects digitally, the GND of resonance control chip U1 holds ground connection, the AOUT end of resonance control chip U1 is connected with the base stage of triode Q6 by resistance R36, the collector electrode of triode Q6 connects digitally, be connected by resistance R38 between the base stage of triode Q6 and the collector electrode of triode Q6, the base stage of triode Q6 is connected with the anode of diode D16, the emitter of triode Q6 is connected with the negative electrode of diode D16, the emitter of triode Q6 is connected with another pwm signal port of power conversion module, the RT end of resonance control chip U1 is by resistance R34 ground connection.
4. parallel operation inverter according to claim 3, is characterized in that: described resonance control chip U1 is UCC2806DW chip.
5. parallel operation inverter according to claim 3, is characterized in that: described operation amplifier chip U2 is LM358 chip.
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| CN201410633399.7A CN104506060B (en) | 2014-11-12 | A kind of also machine inverter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410633399.7A CN104506060B (en) | 2014-11-12 | A kind of also machine inverter |
Publications (2)
| Publication Number | Publication Date |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108900104A (en) * | 2018-09-10 | 2018-11-27 | 深圳市德利和能源技术有限公司 | IGBT analog device, level analog circuit and three level emulation platforms |
| CN113778004A (en) * | 2021-10-14 | 2021-12-10 | 葡藤文化传媒河北有限公司 | Multi-channel controller |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992501A (en) * | 2005-12-30 | 2007-07-04 | 中国科学院电工研究所 | Grid-Connected Power inverter and control method of output current |
| CN101582592A (en) * | 2008-05-15 | 2009-11-18 | 宣昆 | Transless photovoltaic merging and inverting device and control method thereof |
| CN101640489A (en) * | 2008-07-28 | 2010-02-03 | 上海斯堪亚电气调速设备有限公司 | PWM rectification type energy feedback device |
| CN102097964A (en) * | 2011-03-14 | 2011-06-15 | 山东鲁冶瑞宝电气自动化有限公司 | Photovoltaic grid-connected inverter |
| US20120218789A1 (en) * | 2011-02-25 | 2012-08-30 | Phillip Gerard Langhorst | Electrical Power Conditioner |
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1992501A (en) * | 2005-12-30 | 2007-07-04 | 中国科学院电工研究所 | Grid-Connected Power inverter and control method of output current |
| CN101582592A (en) * | 2008-05-15 | 2009-11-18 | 宣昆 | Transless photovoltaic merging and inverting device and control method thereof |
| CN101640489A (en) * | 2008-07-28 | 2010-02-03 | 上海斯堪亚电气调速设备有限公司 | PWM rectification type energy feedback device |
| US20120218789A1 (en) * | 2011-02-25 | 2012-08-30 | Phillip Gerard Langhorst | Electrical Power Conditioner |
| CN102097964A (en) * | 2011-03-14 | 2011-06-15 | 山东鲁冶瑞宝电气自动化有限公司 | Photovoltaic grid-connected inverter |
Non-Patent Citations (1)
| Title |
|---|
| 夏向阳 等: "基于ＤＳＰ控制的单相光伏并网逆变器设计", 《电力科学与技术学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108900104A (en) * | 2018-09-10 | 2018-11-27 | 深圳市德利和能源技术有限公司 | IGBT analog device, level analog circuit and three level emulation platforms |
| CN108900104B (en) * | 2018-09-10 | 2024-04-16 | 深圳市德利和能源技术有限公司 | IGBT analog device, level analog circuit and three-level simulation platform |
| CN113778004A (en) * | 2021-10-14 | 2021-12-10 | 葡藤文化传媒河北有限公司 | Multi-channel controller |
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