CN100459395C - Adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply - Google Patents

Adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply Download PDF

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CN100459395C
CN100459395C CNB2006100187795A CN200610018779A CN100459395C CN 100459395 C CN100459395 C CN 100459395C CN B2006100187795 A CNB2006100187795 A CN B2006100187795A CN 200610018779 A CN200610018779 A CN 200610018779A CN 100459395 C CN100459395 C CN 100459395C
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mutually
triode
diode
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phase
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CN1845439A (en
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章祖文
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Abstract

The disclosed tunable stable-frequency/voltage frequency/voltage-changing power comprises: a three-phase transformer rectification filter circuit, a reversing-switch signal generation/ amplification circuit, an auxiliary power circuit, an independent power circuit, a triode voltage-regulation circuit, a reversing-switch power circuit, a transformer load circuit, a load voltage sampling circuit, a load environmental change voltage sampling circuit, a sample signal amplification/control circuit, and a initiation-control signal generation circuit for power protection. This product has well performance.

Description

Adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply
Technical field
The present invention relates to regulated power supply, especially relate to a kind of adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply.
Background technology
At present, single-phase variable frequency power supply adopts bridge circuit usually, and four IGBT do brachium pontis, and bridge itself is the CL series circuit.The method of circuit operation is to be one group with the diagonal angle brachium pontis, two groups of IGBT of phase-veversal switch, produce alternating current in the bridge CL series circuit, again by being that the transformer of primary coil transmits the frequency conversion electric energy to load with L, the characteristics of this power supply are to produce alternating current in single CL series circuit, control circuit is complicated, the last high pressure that generates easily of IGBT, and power can not be done very greatly.
(patent No. is the utility model patent " light DC voltage stabilization and current stabilization variable voltage and variable current power supply " of applicant's application: ZL032640056) disclose a kind of new phase-veversal switch power supply, it is with two coils of two IGBT phase-veversal switches, in two coils, produce alternating current, these two coils both can be on two ferrite toroidal magnetic cores, also can be on a ferrite toroidal magnetic core, just can go out the frequency conversion energy delivery by the transformer on the magnetic core, this power control circuit is simple, but also generates high pressure easily on the IGBT.
Summary of the invention
The object of the present invention is to provide that a kind of input and output voltage is adjustable continuously, frequency-and voltage-stabilizing, the variable-frequency variable-voltage characteristic is good, efficient is high, power is big, switching device safety, the simple power supply of control circuit.
The object of the present invention is achieved like this: the present invention includes three-phase transformer current rectifying and wave filtering circuit, phase-veversal switch signal generating circuit, auxiliary power circuit and independent current source circuit, feature is to comprise that also triode regulating circuit, phase-veversal switch signal amplification circuit, phase-veversal switch power circuit, transformer load circuit, load voltage sample circuit, load environmental change voltage sample circuit, sampled signal amplifying circuit, sampled signal control circuit and power protection start to control signal generating circuit.
Described triode regulating circuit T ABy A phase fuse BX A, A the 30th, 31 triode GTR mutually A7, GTR A8, A phase 13-16 triode BG A13--BG A16, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase 1--10 diode D A1-D A10, A phase 1--3 adjustable resistance W A1--W A3, A phase 5--9 resistance R A5-R A9, A phase 24-27 resistance R A24-R A27, A phase 1--3 capacitor C A1--C A3 and other element form; Or, described triode regulating circuit T ABy A phase fuse BX A, A the 32nd, 33 triode GTR mutually A9, GTR A10, A phase 17-21 triode BG A17--BG A21, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase the 7th, 8 diode D A7, D A8, A phase 11-18 diode D A11--D A18, A phase 1--3 adjustable resistance W A1--W A3, A phase 5--9 resistance R A5-R A9, A phase 28-31 resistance R A28-R A31, A phase 1--3 capacitor C A1--C A3 and other element form; Or, described triode regulating circuit T ABy A phase fuse BX A, A the 1st, 2 bidirectional triode thyristor BCR mutually A1, BCR A2, A phase the 5th, 6 field effect transistor NMOS A5, NMOS A6, A phase the 3rd, 4 voltage stabilizing didoe ZW A3, ZW A4, A phase 1--6 diode D A1--D A6, A phase the 9th, 10 diode D A9, D A10, A phase the 9th adjustable resistance W A9, A phase 32--34 resistance R A32-R A34 and other element form; Or, described triode regulating circuit T ABy A phase fuse BX A, A the 3rd, 4 bidirectional triode thyristor BCR mutually A3, BCR A4, A phase the 5th triode BG A5, A phase the 22nd, 23 triode BG A22, BG A23, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase 1--6 diode D A1--D A6, A phase the 19th, 20 diode D A19, D A20, A phase 1--3 adjustable resistance W A1--W A3, A phase 5--9 resistance R A5-R A9, A phase the 35th, 36 resistance R A35, R A36 and other element form.
From the electric current elder generation process triode regulating circuit pressure regulation that civil power comes, arrive the phase-veversal switch power circuit through the transformer current rectifying and wave filtering circuit again, in the phase-veversal switch power circuit the two groups switches that are made of PNP pipe and NPN pipe are under the control of phase-veversal switch signal, in two CL series circuits, produce alternating current, and the L in these two CL series circuits be by end of the same name in the rule of a side on same ferrite toroidal magnetic core and as the former limit of transformer, any one constantly, electric current among two L is anti-phase, but the magnetic flux that produces in magnetic core is a homophase, thereby can induce the frequency conversion energy and send out at the secondary of transformer.
The present invention has that input and output voltage is adjustable continuously, frequency-and voltage-stabilizing, the variable-frequency variable-voltage characteristic is good, efficient is high, power is big, switching device safety, the simple advantage of control circuit.
Description of drawings
Fig. 1 is a single phase circuit schematic diagram of the present invention;
Fig. 2 is to be to wait the triode regulating circuit T that constitutes with the PNP pipe A, T B, T CFirst kind of replacement circuit schematic diagram;
Fig. 3 is to be to wait the triode regulating circuit T that constitutes with the PNP pipe A, T B, T CSecond kind of replacement circuit schematic diagram;
Fig. 4 is to be the triode regulating circuit T that constitutes with BCR etc. A, T B, T CThe third replacement circuit schematic diagram;
Fig. 5 is to be the triode regulating circuit T that constitutes with BCR etc. A, T B, T CThe 4th kind of replacement circuit schematic diagram;
Fig. 6 is a three-phase circuit schematic diagram of the present invention;
Fig. 7 is the circuit theory diagrams of three-phase signal generation circuit (SXXHFSDL).
Embodiment
Below in conjunction with embodiment and contrast accompanying drawing the present invention is described in further detail.
Embodiment 1: single-phase adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply (is example mutually with A)
The present invention is by triode regulating circuit T AThe opposite phase switching signal amplifying circuit of A (FXKGXHFDDL); the mutually anti-phase switching power circuit of A (FXKGDYDL); A phase transformer load circuit; load voltage sample circuit (FZQYDL); load environmental change voltage sample circuit (HJQYDL); sampled signal amplifying circuit (QYXHFDDL); sampled signal control circuit (QYXHKZDL); power protection starts to control signal generating circuit; A phase transformer current rectifying and wave filtering circuit (ZLLBDL); the phase-veversal switch signal generating circuit; auxiliary power circuit (FZDYDL) and independent current source circuit (DLDYDL) are formed.
Triode regulating circuit T ABy A phase fuse BX A, A the 24th, 25 triode GTR mutually A1, GTR A2, A phase 1--5 triode BG A1--BG A5, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase 1--10 diode D A1-D A10, A phase 1--3 adjustable resistance W A1--W A3, A phase 1--9 resistance R A1-R A9, A phase 1--3 capacitor C A1--C A3 and other element form, A is the 24th triode GTR mutually A1 collector electrode and A be fuse BX mutually AConnect the end of civil power 380V after the series connection, A is the 24th triode GTR mutually A1 emitter meets A the 3rd diode D mutually A3 anodes and A be the 5th diode D mutually AThe common port of 5 anodes, A is the 3rd diode D mutually A3 negative electrode meets A the 1st diode D mutually A1 anode, A be the 2nd diode D mutually A2 anodes and A be the 4th diode D mutually AThe common port of 4 negative electrodes, A is the 4th diode D mutually A4 anode meets A the 25th triode GTR mutually A2 emitters and A be the 6th diode D mutually AThe common port of 6 anodes, A is the 24th triode GTR mutually A1 base stage meets A the 1st triode BG mutually A1 emitter, A is the 1st resistance R mutually A1 is connected in parallel on A the 24th triode GTR mutually A1 collector electrode and A be the 1st triode BG mutually ABetween 1 the collector electrode, A is the 1st triode BG mutually A1 base stage meets A the 3rd triode BG mutually A3 collector electrode, A is the 3rd resistance R mutually A3 are connected in parallel on A the 3rd triode BG mutually A3 emitter and A be the 24th triode GTR mutually ABetween 1 the collector electrode, A is the 25th triode GTR mutually A2 base stage meets A the 2nd triode BG mutually A2 emitter, A is the 2nd resistance R mutually A2 are connected in parallel on A the 25th triode GTR mutually A2 collector electrode and A be the 2nd triode BG mutually ABetween 2 the collector electrode, A is the 2nd triode BG mutually A2 base stage meets A the 4th triode BG mutually A4 collector electrode, A is the 4th resistance R mutually A4 are connected in parallel on A the 4th triode BG mutually A4 emitter and A be the 25th triode GTR mutually ABetween 2 the collector electrode, A is the 1st diode D mutually A1 negative electrode and A be the 5th diode D mutually AThe public termination A of 5 negative electrodes is the 24th triode GTR mutually A1 collector electrode, A is the 2nd diode D mutually A2 negative electrodes and A be the 6th diode D mutually AThe public termination A of 6 negative electrodes is the 25th triode GTR mutually A2 collector electrode, A is the 3rd triode BG mutually A3 base stages and A be the 4th triode BG mutually A4 base stages all meet A the 8th diode D mutually A8 negative electrode, A is the 8th diode D mutually A8 anode meets A the 1st field effect transistor NMOS mutually A1 drain electrode, A is the 1st field effect transistor NMOS mutually A1 grid and A be the 1st adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 1 series connection, A is the 1st field effect transistor NMOS mutually A1 source electrode and A be the 2nd adjustable resistance W mutually AMeet A the 5th triode BG mutually after 2 series connection A5 collector electrode, A is the 1st field effect transistor NMOS mutually A1 source electrode, A be the 2nd field effect transistor NMOS mutually A2 source electrodes and A be the 5th triode BG mutually AThe common port of 5 base stages all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 5th triode BG mutually A5 emitter meets A the 9th diode D mutually A9 anodes and A be the 10th diode D mutually AThe common port of 10 anodes, A is the 9th diode D mutually A9 negative electrode meets A the 24th triode GTR mutually A1 collector electrode, A is the 10th diode D mutually A10 negative electrode meets A the 25th triode GTR mutually A2 collector electrode, A is the 7th diode D mutually A7 with A the 8th diode D mutually A8 reverse parallel connections, A is the 5th resistance R mutually A5 are connected in parallel on A the 1st field effect transistor NMOS mutually ABetween 1 the source electrode and grid, A is the 2nd field effect transistor NMOS mutually A2 drain electrode and A be the 7th resistance R mutually AMeet A the 5th triode BG mutually after 7 series connection A5 collector electrode, A is the 2nd field effect transistor NMOS mutually A2 grid and A be the 3rd adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 3 series connection, A the 9th resistance R A9 mutually is connected in parallel on A the 2nd field effect transistor NMOS mutually ABetween 2 the source electrode and grid, A is the 1st capacitor C mutually A1 is connected in parallel on A the 24th triode GTR mutually ABetween 1 the collector electrode and ground, A is the 2nd capacitor C mutually A2 are connected in parallel on A the 25th triode GTR mutually ABetween 2 the collector electrode and ground, A is the 3rd capacitor C mutually A3 are connected in parallel on A the 8th diode D mutually A8 anode and A be the 28th triode GTR mutually ABetween 5 the emitter.
The opposite phase switching signal amplifying circuit of A is by A phase the 3rd field effect transistor NMOS A3, A phase the 4th field effect transistor NMOS A4, A phase 10--13 triode BG A10--BG A13, A phase the 1st, 2 switching tube IGBT A1, IGBT A2, A phase the 1st, 2 voltage-stabiliser tube ZW A1, ZW A2, A phase 6--9 adjustable resistance W A6--W A9, A phase 14--23 resistance R A14--R A23 form, and A is the 15th resistance R mutually A15 one termination+12V voltage, A is another termination A phase the 10th triode BG of the 15th resistance mutually A10 emitter, A is the 10th triode BG mutually A10 collector electrode meets A the 11st triode BG mutually A11 collector electrode, A is the 11st triode BG mutually A11 grounded emitter, A is the 10th triode BG mutually A10 base stage and A be the 16th resistance R mutually AMeet A the 11st triode BG mutually after 16 series connection A11 base stage, A is the 14th resistance R mutually A14 one termination+12V voltage, A is the other end and A the 6th adjustable resistance W mutually of the 14th resistance mutually AMeet A the 11st triode BG mutually after 6 series connection A11 base stages and A be the 3rd field effect transistor NMOS mutually AThe common port of 3 drain electrodes, A is the 3rd field effect transistor NMOS mutually A3 source ground, A is the 3rd field effect transistor NMOS mutually A3 grid connects phase comparator output 2 pin of phase-locked loop intergrated circuit IC3, and A is the 17th resistance R mutually A17 are connected in parallel on A the 3rd field effect transistor NMOS mutually ABetween 3 the grid and ground, A is the 7th adjustable resistance W mutually AA termination A of 7 is the 10th triode BG mutually A10 collector electrode, A is the 7th adjustable resistance W mutually AAnother termination A of 7 is the 1st switching tube IGBT mutually A1 grid, A is the 18th resistance R mutually A18 are connected in parallel on A the 1st switching tube IGBT mutually ABetween 1 the grid and ground, A is the 1st voltage-stabiliser tube ZW mutually A1 negative electrode meets A the 1st switching tube IGBT mutually A1 grid, A is the 1st voltage-stabiliser tube ZW mutually A1 plus earth, A is the 1st switching tube IGBT mutually A1 grounded emitter, A is the 20th resistance R mutually A20 one termination+12V voltage, A is the 20th resistance R mutually AAnother termination A of 20 is the 12nd triode BG mutually A12 emitter, A is the 12nd triode BG mutually A12 collector electrode meets A the 13rd triode BG mutually A13 collector electrode, A is the 13rd triode BG mutually A13 grounded emitter, A is the 12nd triode BG mutually A12 base stage and A be the 21st resistance R mutually AMeet A the 13rd triode BG mutually after 21 series connection A13 base stage, A is the 19th resistance R mutually A19 one termination+12V voltage, A is the 19th resistance R mutually A19 the other end and A be the 8th adjustable resistance W mutually AMeet A the 13rd triode BG mutually after 8 series connection A13 base stages and A be the 4th field effect transistor NMOS mutually AThe common port of 4 drain electrodes, A is the 4th field effect transistor NMOS mutually A4 source ground, A is the 4th field effect transistor NMOS mutually A4 grid connects phase comparator input 3 pin and voltage controlled oscillator output 4 pin of phase-locked loop intergrated circuit IC3, and A is the 22nd resistance R mutually A22 are connected in parallel on A the 4th field effect transistor NMOS mutually ABetween 4 the grid and ground, A is the 9th adjustable resistance W mutually AA termination A of 9 is the 12nd triode BG mutually A12 collector electrode, A is the 9th adjustable resistance W mutually AAnother termination A of 9 is the 2nd switching tube IGBT mutually A2 grid, A is the 23rd resistance R mutually A23 are connected in parallel on A the 2nd switching tube IGBT mutually ABetween 2 the grid and ground, A is the 2nd voltage-stabiliser tube ZW mutually A2 negative electrode meets A the 2nd switching tube IGBT mutually A2 grid, A is the 2nd voltage-stabiliser tube ZW mutually A2 plus earth, A is the 2nd switching tube IGBT mutually A2 grounded emitter.
The mutually anti-phase switching power circuit of A is by A phase 26--29 triode GTR A3--GTR A6) A phase 6--9 triode BG A6--BG A9, A phase the 4th, 5 adjustable resistance W A4, W A5, A phase 10--13 resistance R A10--R A13, A phase the 4th, 5 polar capacitor C A4, C A5, A phase the 6th, 7 capacitor C A6, C A7, A phase 3--6 inductance L A3--L AThe 6 A phase transformer B that constitute with the toroidal core circle AAnd other element is formed A phase the 26th triode GTR A3 emitter, A be the 28th triode GTR mutually A5 emitter all meets A the 4th polar capacitor C mutually A4, A phase the 5th polar capacitor C A5 positive pole, A is the 4th polar capacitor C mutually A4, A phase the 5th polar capacitor C AThe equal ground connection of 5 negative pole, A is the 10th resistance R mutually AA termination A of 10 is the 4th polar capacitor C mutually A4, A phase the 5th polar capacitor C A5 positive pole, A is the 10th resistance R mutually A10 the other end and A be the 4th adjustable resistance W mutually AMeet A the 1st switching tube IGBT mutually after 4 series connection A1 collector electrode, A be the 7th triode BG mutually A7 base stages and A be the 11st resistance R mutually AThe common port of 11 1 ends, A is the 11st resistance R mutually AAnother termination A of 11 is the 6th triode BG mutually A6 base stage, A is the 26th triode GTR mutually A3 collector electrode meets A the 27th triode GTR mutually A4 collector electrodes, A be the 6th triode BG mutually A6 collector electrodes, A be the 7th triode BG mutually AThe common port of 7 collector electrodes, A is the 26th triode GTR mutually A3 base stage meets A the 6th triode BG mutually A6 emitter, A is the 27th triode GTR mutually A4 base stage meets A the 7th triode BG mutually A7 emitter, A is the 27th triode GTR mutually A4 grounded emitter, A is the 28th triode GTR mutually A5 collector electrode meets A the 29th triode GTR mutually A6 collector electrodes, A be the 8th triode BG mutually A8 collector electrodes, A be the 9th triode BG mutually AThe common port of 9 collector electrodes, A is the 28th triode GTR mutually A5 base stage meets A the 8th triode BG mutually A8 emitter, A is the 29th triode GTR mutually A6 base stage meets A the 9th triode BG mutually A9 emitter, A is the 29th triode GTR mutually A6 grounded emitter, A is the 12nd resistance R mutually AA termination polar capacitor C of 12 A4, C A5 positive pole, A is the 12nd resistance R mutually A12 the other end and A be the 5th adjustable resistance W mutually AMeet A the 2nd switching tube IGBT mutually after 5 series connection A2 collector electrode, A be the 9th triode BG mutually A9 base stages and A be the 13rd resistance R mutually AThe common port of 13 1 ends, A is the 13rd resistance R mutually AAnother termination A of 13 is the 8th triode BG mutually A8 base stage, A is the 6th capacitor C mutually AA termination A of 6 is the 26th triode GTR mutually A3 collector electrode, A is the 6th capacitor C mutually A6 the other end and A phase transformer B AOn A the 3rd inductance L mutually A3 series connection back ground connection, A is the 7th capacitor C mutually AA termination A of 7 is the 28th triode GTR mutually A5 collector electrode, A is the 7th capacitor C mutually A7 the other end and A phase transformer B AOn A the 4th inductance L mutually A4 series connection back ground connection; A is the 3rd inductance L mutually A3, A phase the 4th inductance L A4 end of the same name is in the same side.
A phase transformer load circuit is by A phase the 5th inductance L A5, A phase the 8th capacitor C A8 and A phase load Z AForm, A is the 8th capacitor C mutually A8 and A phase load Z AAll be connected in parallel on transformer A phase B AOn A the 5th inductance L mutually A5 two ends.
Live presses sample circuit by the 3rd photoelectrical coupler TLP3,13--16 diode D13-D16, the 6th resistance R 6, the 19th resistance R 19 and the 6th polar capacitor C6 form, the 6th polar capacitor C6 is connected in parallel between the common port of the common port of the 13rd diode D13 anode and the 14th diode D14 negative electrode and the 15th diode D15 anode and the 16th diode D16 negative electrode, the 13rd diode D13, the negative electrode of the 15th diode D15 all connects the positive pole of the 6th polar capacitor C6, the 14th diode D14, the anode of the 16th diode D16 all connects the negative pole of the 6th polar capacitor C6, the positive pole of one termination the 6th polar capacitor C6 of the 19th resistance R 19, the anode of the photodiode of another termination the 3rd photoelectrical coupler TLP3 of the 19th resistance R 19, the negative electrode of the photodiode of the 3rd photoelectrical coupler TLP3 connects the negative pole of polarity the 6th capacitor C 6, the collector electrode of the phototriode of the 3rd photoelectrical coupler TLP3 connects+12V voltage, the end points Q3 of the emitter order cutter three throw switch K of the 3rd photoelectrical coupler TLP3 and the common port of the 6th resistance R 6 one ends, the other end ground connection of the 6th resistance R 6.
Load environmental change voltage sample circuit is by transducer CHGQ, the 1st field effect transistor NMOS1, the 2nd, 3 adjustable resistance W2, W3 and the 4th, 5 resistance R 4, R5 forms, the positive input terminal of transducer CHGQ with connect+12V voltage after the 4th resistance R 4 is connected, ground connection after the negative input end of transducer CHGQ is connected with the 2nd adjustable resistance W2, the grid of positive output termination the 1st field effect transistor NMOS1 of transducer CHGQ, the common port of the source electrode of negative output termination the 1st field effect transistor NMOS1 of transducer CHGQ and the end points Q2 of K switch, the 5th resistance R 5 is connected in parallel on+common port of the drain electrode of 12V voltage and the 1st field effect transistor NMOS1 and the end points Q1 of K switch between, the 3rd adjustable resistance W3 is connected in parallel between the source electrode and ground of the 1st field effect transistor NMOS1.
The sampled signal amplifying circuit is by the 4th, 5 integrated circuit (IC) 4, IC5, the 4th, 5 adjustable resistance W4, W5,7--14 resistance R 7-R14 forms, the middle end points Q of the positive input termination K switch of the 4th integrated circuit (IC) 4, the negative input end of the 4th integrated circuit (IC) 4 connects the 7th resistance R 7, the public connecting end of the 8th resistance R 8, another termination+12V voltage of the 7th resistance R 7, ground connection after the other end of the 8th resistance R 8 is connected with the 4th adjustable resistance W4, the power end of the 4th integrated circuit (IC) 4 with connect+12V voltage after the 9th resistance R 9 is connected, the earth terminal ground connection of the 4th integrated circuit (IC) 4, the negative input end of output termination the 5th integrated circuit (IC) 5 of the 4th integrated circuit (IC) 4, positive input termination the 11st resistance R 11 of the 5th integrated circuit (IC) 5, the public connecting end of the 12nd resistance R 12, another termination+12V voltage of the 11st resistance R 11, ground connection after the other end of the 12nd resistance R 12 is connected with the 5th adjustable resistance W5, the power end of the 5th integrated circuit (IC) 5 with connect+12V voltage earth terminal ground connection after the 13rd resistance R 13 is connected.
The sampled signal control circuit is formed by the sampled signal control circuit of foundation electric power output voltage effective value fluctuating range control power input voltage with according to the sampled signal control circuit of load environment control electric power output voltage frequency.
The sampled signal control circuit of controlling power input voltage according to electric power output voltage effective value fluctuating range is by A phase the 1st, 2 photoelectrical coupler TLP A1, TLP A2, A phase 6--8 resistance R A6--R A8, the 10th resistance R 10, A phase the 14th resistance R 14 are formed A phase the 1st photoelectrical coupler TLP to A mutually AThe anode of 1 photodiode connects the output of the 4th integrated circuit (IC) 4, and A is the 1st photoelectrical coupler TLP mutually AGround connection after the negative electrode of 1 photodiode is connected with the 10th resistance R 10, A is the 1st photoelectrical coupler TLP mutually AThe collector electrode of 1 phototriode and A be the 8th resistance R mutually AMeet A the 2nd field effect transistor NMOS mutually after 8 series connection A2 grid, A is the 1st photoelectrical coupler TLP mutually AThe emitter of 1 phototriode meets A the 5th triode BG mutually A5 base stage, A is the 2nd photoelectrical coupler TLP mutually AThe anode of 2 photodiode connects the output of the 5th integrated circuit (IC) 5, and A is the 2nd photoelectrical coupler TLP mutually AGround connection after the negative electrode of 2 photodiode is connected with the 14th resistance R 14, A is the 2nd photoelectrical coupler TLP mutually AThe collector electrode of 2 phototriode meets A the 5th triode BG mutually A5 collector electrode, A is the 2nd photoelectrical coupler TLP mutually AThe emitter of 2 phototriode and A be the 6th resistance R mutually AMeet A the 2nd field effect transistor NMOS mutually after 6 series connection A2 drain electrode, A is the 7th resistance R mutually A7 are connected in parallel on A the 2nd field effect transistor NMOS mutually A2 drain electrode and A be the 5th triode BG mutually ABetween 5 the collector electrode.
Control the sampled signal control circuit of electric power output voltage frequency by the 1st according to the load environment, 2 photoelectrical coupler TLP1, TLP2, the 1st, 2 resistance R 1, R2 forms, the anode of the photodiode of the 1st photoelectrical coupler TLP1 connects the output of the 5th integrated circuit (IC) 5, ground connection after the negative electrode of the photodiode of the 1st photoelectrical coupler TLP1 is connected with the 14th resistance R 14, the collector electrode of the phototriode of the 1st photoelectrical coupler TLP1 with connect+12V voltage after the 1st resistance R 1 is connected, the emitter of the phototriode of the 1st photoelectrical coupler TLP1 connects the sliding end of the 1st adjustable resistance W1, the anode of the photodiode of the 2nd photoelectrical coupler TLP2 connects the output of the 4th integrated circuit (IC) 4, ground connection after the negative electrode of the photodiode of the 2nd photoelectrical coupler TLP2 is connected with the 10th resistance R 10, the collector electrode of the phototriode of the 2nd photoelectrical coupler TLP2 and the emitter that connects the phototriode of the 1st photoelectrical coupler TLP1 after the 2nd resistance R 2 is connected, the grounded emitter of the phototriode of the 2nd photoelectrical coupler TLP2.
Power protection starts to control signal generating circuit by the 2nd field effect transistor NMOS the 2, the 1st triode BG1, A phase the 3rd photoelectrical coupler TLP A3, the 11st, 12 diode D11, D12, the 6th adjustable resistance W6,15--18 resistance R 15--R18, the 7th polar capacitor C7, LED and loud speaker SPK form, the anode of the 11st diode D11 connects the output of the 4th integrated circuit (IC) 4, the negative electrode of the 11st diode D11 connects the common port of the 2nd field effect transistor NMOS 2 grids and the 7th polar capacitor C7 positive pole, the minus earth of the 7th polar capacitor C7, the 15th resistance R 15 is connected in parallel on the two ends of the 4th polar capacitor C4, the drain electrode of the 2nd field effect transistor NMOS 2 with connect+12V voltage after the 16th resistance R 16 is connected, the source electrode of the 2nd field effect transistor NMOS 2 connects the anode of the 12nd diode D12, the negative electrode of the 12nd diode D12 connects the sliding end of the 6th adjustable resistance W6, one termination of the 17th resistance R 17+12V voltage, ground connection after the other end of the 17th resistance R 17 is connected with the 6th adjustable resistance W6, the emitter of the 1st triode BG1 with connect+12V voltage after the 18th resistance R 18 is connected, the base stage of the 1st triode BG1 connects the drain electrode of the 2nd field effect transistor NMOS 2, the anode of sending and receiving optical diode LED after the collector electrode of the 1st triode BG1 is connected with loud speaker SPK, the negative electrode of LED meet A the 3rd photoelectrical coupler TLP mutually AThe anode of 3 photodiode, A is the 3rd photoelectrical coupler TLP mutually AThe minus earth of 3 photodiode, A is the 3rd photoelectrical coupler TLP mutually AThe collector electrode of 3 phototriode meets A the 1st field effect transistor NMOS mutually A1 grid, A is the 3rd photoelectrical coupler TLP mutually AThe emitter of 3 phototriode meets A the 1st field effect transistor NMOS mutually A1 source electrode.
A phase transformer current rectifying and wave filtering circuit is by A phase the 1st, 2 inductance L A1, L A2, B phase the 1st, 2 inductance L B1, L B2, C phase the 1st, 2 inductance L C1, L C2,17--22 diode D17-D22, A phase the 4th, 5 polar capacitor C A4, C A5 form, and A is the 1st inductance L mutually A1 is connected in parallel on the 25th triode GTR ABetween 2 the collector electrode and ground, A is the 2nd inductance L mutually A2, B phase the 2nd inductance L B2, C phase the 2nd inductance L CAn end of 2 links together, and A is the 2nd inductance L mutually A2 another terminating diode D17 anode and the common port of diode D18 negative electrode, B is the 2nd inductance L mutually B2 another terminating diode D19 anode and the common port of diode D20 negative electrode, C is the 2nd inductance L mutually C2 another termination the 21st diode D21 anode and the common port of the 22nd diode D22 negative electrode, public termination the 4th polar capacitor C of the negative electrode of the 17th diode D17, the 19th diode D19, the 21st diode D21 A4, A phase the 5th polar capacitor C A5 positive pole, the anode of the 18th diode D18, the 20th diode D20, the 22nd diode D22, A be the 4th polar capacitor C mutually A4, A phase the 5th polar capacitor C AThe equal ground connection of the common port of 5 negative pole.
The phase-veversal switch signal generating circuit is made up of phase-locked loop intergrated circuit (SXHJCDL) IC3, the 1st adjustable resistance W1, the 3rd resistance R the 3, the 5th capacitor C 5,16,14 pin of phase-locked loop intergrated circuit IC3 connect+12V, 8, the 5 pin ground connection of phase-locked loop intergrated circuit IC3, ground connection after 11 pin of phase-locked loop intergrated circuit IC3 are connected with the 3rd resistance R 3, the 5th capacitor C 5 is connected in parallel between 6,7 pin of phase-locked loop intergrated circuit IC3, and 2 pin of phase-locked loop intergrated circuit IC3 meet A the 3rd field effect transistor NMOS mutually A3 grid, phase-locked loop intergrated circuit IC33,4 pin meet A the 4th field effect transistor NMOS mutually A4 grid.
Auxiliary power circuit is made up of the 1st, 2 coil L1, L2, the 1st integrated regulator IC1,1--5 diode D1-D5 and the 1st, 2 polar capacitor C1, the C2 of the 1st fuse BX1, the 1st transformer B1, the civil power of 220V is output+12V voltage after the 1st transformer B1 step-down, 1--4 diode D1-D4 rectification, the 1st integrated regulator IC1 voltage stabilizing and the 1st polar capacitor C1, the 2nd polar capacitor C2 filtering, supplies with other circuit.
The independent current source circuit is made up of the 1st coil L1, the 3rd coil L3, the 2nd integrated regulator IC2,6--10 diode D6-D10 and the 3rd, 4 polar capacitor C3, the C4 of the 1st fuse BX1, the 1st transformer B1, and the civil power of 220V is output+12V voltage after the 1st transformer B1 step-down, 6--9 diode D6-D9 rectification, the 2nd integrated regulator IC2 voltage stabilizing and the 3rd polar capacitor C3, the 4th polar capacitor C4 filtering.
Embodiment 2: single-phase adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply (is example mutually with A)
The circuit of embodiment 2 is identical with the circuit of embodiment 1, and difference is: triode regulating circuit T AAdopt first kind of replacement circuit to substitute (referring to Fig. 2).
Triode regulating circuit T ABy A phase fuse BX A, A the 30th, 31 triode GTR mutually A7, GTR A8, A phase 13-16 triode BG A13--BG A16, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase 1--10 diode D A1-D A10, A phase 1--3 adjustable resistance W A1--W A3, A phase 5--9 resistance R A5-R A9, A phase 24-27 resistance R A24-R A27, A phase 1--3 capacitor C A1--C A3 and other element form, A is the 30th triode GTR mutually A7 emitter and A be fuse BX mutually AConnect the end of civil power 380V after the series connection, A is the 30th triode GTR mutually A7 collector electrode meets A the 3rd diode D mutually A3 anodes and A be the 5th diode D mutually AThe common port of 5 anodes, A is the 3rd diode D mutually A3 negative electrode meets A the 1st diode D mutually A1 anode, A be the 2nd diode D mutually A2 anodes and A be the 4th diode D mutually AThe common port of 4 negative electrodes, A is the 4th diode D mutually A4 anode meets A the 31st triode GTR mutually A8 collector electrodes and A be the 6th diode D mutually AThe common port of 6 anodes, A is the 30th triode GTR mutually A7 base stage meets A the 13rd triode BG mutually A13 emitter, A is the 24th resistance R mutually A24 are connected in parallel on A the 13rd triode BG mutually A13 collector electrode and A be the 3rd diode D mutually ABetween 3 the negative electrode, A is the 13rd triode BG mutually A13 base stage meets A the 15th triode BG mutually A15 emitter, A is the 26th resistance R mutually A26 are connected in parallel on A the 15th triode BG mutually A15 collector electrode and A be the 3rd diode D mutually ABetween 3 the negative electrode, A is the 31st triode GTR mutually A8 base stage meets A the 14th triode BG mutually A14 emitter, A is the 25th resistance R mutually A25 are connected in parallel on A the 14th triode BG mutually A14 collector electrode and A be the 3rd diode D mutually ABetween 3 the negative electrode, A is the 14th triode BG mutually A14 base stage meets A the 16th triode BG mutually A16 emitter, A is the 27th resistance R mutually A27 are connected in parallel on A the 16th triode BG mutually A16 collector electrode and A be the 3rd diode D mutually ABetween 3 the negative electrode, A is the 1st diode D mutually A1 negative electrode and A be the 5th diode D mutually AThe public termination A of 5 negative electrodes is the 30th triode GTR mutually A7 emitter, A is the 2nd diode D mutually A2 negative electrodes and A be the 6th diode D mutually AThe public termination A of 6 negative electrodes is the 31st triode GTR mutually A8 emitter, A is the 15th triode BG mutually A15 base stages and A be the 16th triode BG mutually A16 base stages all meet A the 8th diode D mutually A8 negative electrode, A is the 8th diode D mutually A8 anode meets A the 1st field effect transistor NMOS mutually A1 drain electrode, A is the 1st field effect transistor NMOS mutually A1 grid and A be the 1st adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 1 series connection, A is the 1st field effect transistor NMOS mutually A1 source electrode and A be the 2nd adjustable resistance W mutually AMeet A the 5th triode BG mutually after 2 series connection A5 collector electrode, A is the 1st field effect transistor NMOS mutually A1 source electrode, A be the 2nd field effect transistor NMOS mutually A2 source electrodes and A be the 5th triode BG mutually AThe common port of 5 base stages all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 5th triode BG mutually A5 emitter meets A the 9th diode D mutually A9 anodes and A be the 10th diode D mutually AThe common port of 10 anodes, A is the 9th diode D mutually A9 negative electrode meets A the 30th triode GTR mutually A7 emitter, A is the 10th diode D mutually A10 negative electrode meets A the 31st triode GTR mutually A8 emitter, A is the 7th diode D mutually A7 with A the 8th diode D mutually A8 reverse parallel connections, A is the 5th resistance R mutually A5 are connected in parallel on A the 1st field effect transistor NMOS mutually ABetween 1 the source electrode and grid, A is the 2nd field effect transistor NMOS mutually A2 drain electrode and A be the 7th resistance R mutually AMeet A the 5th triode BG mutually after 7 series connection A5 collector electrode, A is the 2nd field effect transistor NMOS mutually A2 grid and A be the 3rd adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 3 series connection, A is the 9th resistance R mutually A9 are connected in parallel on A the 2nd field effect transistor NMOS mutually ABetween 2 the source electrode and grid, A is the 1st capacitor C mutually A1 is connected in parallel on A the 30th triode GTR mutually ABetween 7 the emitter and ground, A is the 2nd capacitor C mutually A2 are connected in parallel on A the 31st triode GTR mutually A)Between 8 the emitter and ground, A is the 3rd capacitor C mutually A3 are connected in parallel on A the 8th diode D mutually A8 anode and A be the 5th triode BG mutually ABetween 5 the emitter.
Embodiment 3: single-phase adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply (is example mutually with A)
The circuit of embodiment 3 is identical with the circuit of embodiment 1, and difference is: triode regulating circuit T AAdopt second kind of replacement circuit to substitute (referring to Fig. 3).
Triode regulating circuit T ABy A phase fuse BX A, A the 32nd, 33 triode GTR mutually A9, GTR A10, A phase 17-21 triode BG A17--BG A21, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase the 7th, 8 diode D A7, D A8, A phase 11-18 diode D A11--D A18, A phase 1--3 adjustable resistance W A1--W A3, A phase 5--9 resistance R A5-R A9, A phase 28-31 resistance R A28-R A31, A phase 1--3 capacitor C A1--C A3 and other element form, A is the 11st diode D mutually A11 anodes and A be the 13rd diode D mutually AThe common port of 13 negative electrodes and A be fuse BX mutually AConnect the end of civil power 380V after the series connection, A is the 13rd diode D mutually A13 anodes and A be the 15th diode D mutually AThe public termination A of 15 anodes is the 32nd triode GTR mutually A9 collector electrode, A is the 11st diode D mutually A11 negative electrode meets A the 12nd diode D mutually A12 negative electrodes, A be the 15th diode D mutually A15 negative electrodes, A be the 16th diode D mutually A16 negative electrodes and A be the 31st triode GTR mutually AThe common port of 8 emitters, A is the 32nd triode GTR mutually A9 base stage meets A the 17th triode BG mutually A17 emitter, A is the 28th resistance R mutually A28 are connected in parallel on A the 17th triode BG mutually A17 collector electrode and A be the 13rd diode D mutually ABetween 13 the negative electrode, A is the 17th triode BG mutually A17 base stage meets A the 19th triode BG mutually A19 collector electrode, A is the 30th resistance R mutually A30 are connected in parallel on A the 19th triode BG mutually A19 emitter and A be the 13rd diode D mutually ABetween 13 the negative electrode, A is the 14th diode D mutually A14 anodes and A be the 16th diode D mutually AThe public termination A of 16 anodes is the 33rd triode GTR mutually A10 collector electrodes, A is the 33rd triode GTR mutually A10 base stage meets A the 18th triode BG mutually A18 emitter, A is the 29th resistance R mutually A29 are connected in parallel on A the 18th triode BG mutually A18 collector electrode and A be the 14th diode D mutually ABetween 14 the negative electrode, A is the 18th triode BG mutually A18 base stage meets A the 20th triode BG mutually A20 collector electrode, A is the 31st resistance R mutually A31 are connected in parallel on A the 20th triode BG mutually A20 emitter and A be the 14th diode D mutually ABetween 14 the negative electrode, A is the 19th triode BG mutually A19 base stages and A be the 20th triode BG mutually A20 base stages all meet A the 8th diode D mutually A8 negative electrode, A is the 8th diode D mutually A8 anode meets A the 1st field effect transistor NMOS mutually A1 source electrode, A is the 1st field effect transistor NMOS mutually A1 source electrode, A be the 2nd field effect transistor NMOS mutually A2 source electrodes and A be the 21st triode BG mutually AThe common port of 21 base stages all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 1st field effect transistor NMOS mutually A1 grid and A be the 1st adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 1 series connection, A is the 1st field effect transistor NMOS mutually A1 drain electrode and A be the 2nd adjustable resistance W mutually AMeet A the 21st triode BG mutually after 2 series connection A21 emitter, A is the 21st triode BG mutually A21 collector electrode meets A the 17th diode D mutually A17 negative electrodes and A be the 18th diode D mutually AThe common port of 18 negative electrodes, A is the 17th diode D mutually A17 anode meets A the 11st diode D mutually A11 anode, A is the 18th diode D mutually A18 anode meets A the 12nd diode D mutually A12 anode, A is the 7th diode D mutually A7 with A the 8th diode D mutually A8 reverse parallel connections, A is the 5th resistance R mutually A5 are connected in parallel on A the 1st field effect transistor NMOS mutually ABetween 1 the source electrode and grid, A is the 2nd field effect transistor NMOS mutually A2 drain electrode and A be the 7th resistance R mutually AMeet A the 21st triode BG mutually after 7 series connection A21 collector electrode, A is the 2nd field effect transistor NMOS mutually A2 grid and A be the 3rd adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 3 series connection, A is the 9th resistance R mutually A9 are connected in parallel on A the 2nd field effect transistor NMOS mutually ABetween 2 the source electrode and grid, A is the 1st capacitor C mutually A1 is connected in parallel on A the 11st diode D mutually ABetween 11 the anode and ground, A is the 2nd capacitor C mutually A2 are connected in parallel on A the 12nd diode D mutually ABetween 12 the anode and ground, A is the 3rd capacitor C mutually A3 are connected in parallel on A the 8th diode D mutually A8 anode and A be the 21st triode BG mutually ABetween 21 the collector electrode.
Embodiment 4: single-phase adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply (is example mutually with A)
The circuit of embodiment 4 is identical with the circuit of embodiment 1, and difference is: triode regulating circuit T AAdopt second kind of replacement circuit to substitute (referring to Fig. 4).
Triode regulating circuit T ABy A phase fuse BX A, A the 1st, 2 bidirectional triode thyristor BCR mutually A1, BCR A2, A phase the 5th, 6 field effect transistor NMOS A5, NMOS A6, A phase the 3rd, 4 voltage stabilizing didoe ZW A3, ZW A4, A phase 1--6 diode D A1--D A6, A phase the 9th, 10 diode D A9, D A10, A phase the 9th adjustable resistance W A9, A phase 32--34 resistance R A32-R A34 and other element form, A is the 1st bidirectional triode thyristor BCR mutually A1 the T1 utmost point, A be the 1st diode D mutually A1 negative electrode and A be the 5th diode D mutually AThe common port of 5 negative electrodes and A be fuse BX mutually AConnect the end of civil power 380V after the series connection, A is the 1st bidirectional triode thyristor BCR mutually A1 the T2 utmost point meets A the 3rd diode D mutually A3 anodes and A be the 5th diode D mutually AThe common port of 5 anodes, A is the 3rd diode D mutually A3 negative electrode meets A the 1st diode D mutually A1 anode, A be the 2nd diode D mutually A2 anodes and A be the 4th diode D mutually AThe common port of 4 negative electrodes, A is the 4th diode D mutually A4 anode meets A the 2nd bidirectional triode thyristor BCR mutually A2 the T2 utmost point and A be the 6th diode D mutually AThe common port of 6 anodes, A is the 1st bidirectional triode thyristor BCR mutually A2 the T1 utmost point meets A the 2nd diode D mutually A2 negative electrodes and A be the 6th diode D mutually AThe common port of 6 negative electrodes, A is the 1st bidirectional triode thyristor BCR mutually A1 the control utmost point meets A the 5th field effect transistor NMOS mutually A5 source electrodes and A be the 3rd voltage stabilizing didoe ZW mutually AThe common port of 3 anodes, A is the 32nd resistance R mutually A32 are connected in parallel on A the 1st diode D mutually A1 negative electrode and A be the 5th field effect transistor NMOS mutually ABetween 5 the drain electrode, A is the 2nd bidirectional triode thyristor BCR mutually A2 the control utmost point meets A the 6th field effect transistor NMOS mutually A6 source electrodes and A be the 4th voltage stabilizing didoe ZW mutually AThe common port of 4 anodes, A is the 33rd resistance R mutually A33 are connected in parallel on A the 2nd diode D mutually A2 negative electrodes and A be the 6th field effect transistor NMOS mutually ABetween 6 the drain electrode, A is the 9th adjustable resistance W mutually AA termination A of 9 is the 3rd diode D mutually A3 negative electrodes and A be the 4th diode D mutually AThe common port of 4 negative electrodes, A is the 9th adjustable resistance W mutually A9 the other end and A be the 34th resistance R mutually AMeet A the 9th diode D mutually after 34 series connection A9 negative electrodes and A be the 10th diode D mutually AThe common port of 10 negative electrodes, A is the 9th adjustable resistance W mutually A9 slip termination A is the 5th field effect transistor NMOS mutually A5 grids, A be the 6th field effect transistor NMOS mutually A6 grids, A be the 3rd voltage stabilizing didoe ZW mutually A3 negative electrodes, A be the 4th voltage stabilizing didoe ZW mutually AThe common port of 4 negative electrodes, A is the 9th diode D mutually A9 anode meets A the 1st diode D mutually A1 negative electrode, A is the 10th diode D mutually A10 anode meets A the 2nd diode D mutually A2 negative electrode, the A in the sampled signal control circuit is the 1st photoelectrical coupler TLP mutually AThe collector electrode of the phototriode in 1 meets A the 9th adjustable resistance W mutually A9 sliding end, A is the 1st photoelectrical coupler TLP mutually AThe emitter of the phototriode in 1 and A be the 8th resistance R mutually AMeet A the 3rd diode D mutually after 8 series connection A3 negative electrode, A is the 2nd photoelectrical coupler TLP mutually AThe collector electrode of the phototriode in 2 meets A the 9th adjustable resistance W mutually A9 with A the 34th resistance R mutually A34 public connecting end, A is the 2nd photoelectrical coupler TLP mutually AThe emitter of the phototriode in 2 and A be the 6th resistance R mutually AMeet A the 9th adjustable resistance W mutually after 6 series connection A9 sliding end, A is the 3rd photoelectrical coupler TLP mutually AThe collector electrode of the phototriode in 3 meets A the 3rd diode D mutually A3 negative electrode, A is the 3rd photoelectrical coupler TLP mutually AThe emitter of the phototriode in 3 meets A the 9th adjustable resistance W mutually A9 sliding end, A is the 1st capacitor C mutually A1 is connected in parallel on A the 1st diode D mutually ABetween 1 the negative electrode and ground, A is the 2nd capacitor C mutually A2 are connected in parallel on A the 2nd diode D mutually ABetween 2 the negative electrode and ground.
Embodiment 5: single-phase adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply (is example mutually with A)
The circuit of embodiment 5 is identical with the circuit of embodiment 1, and difference is: triode regulating circuit T AAdopt second kind of replacement circuit to substitute (referring to Fig. 5).
Triode regulating circuit T ABy A phase fuse BX A, A the 3rd, 4 bidirectional triode thyristor BCR mutually A3, BCR A4, A phase the 5th triode BG A5, A phase the 22nd, 23 triode BG A22, BG A23, A phase the 1st, 2 field effect transistor NMOS A1, NMOS A2, A phase 1--6 diode D A1--D A6, A phase the 19th, 20 diode D A19, D A20, A phase 1--3 adjustable resistance W A1--W A3, A phase 5--9 resistance R A5-R A9, A phase the 35th, 36 resistance R A35, R A36 and other element form, A is the 3rd bidirectional triode thyristor BCR mutually A3 the T1 utmost point, A be the 1st diode D mutually A1 negative electrode and A be the 5th diode D mutually AThe common port of 5 negative electrodes and A be fuse BX mutually AConnect the end of civil power 380V after the series connection, A is the 3rd bidirectional triode thyristor BCR mutually A3 the T2 utmost point meets A the 3rd diode D mutually A3 anodes and A be the 5th diode D mutually AThe common port of 5 anodes, A is the 3rd diode D mutually A3 negative electrode meets A the 1st diode D mutually A1 anode, A be the 2nd diode D mutually A2 anodes and A be the 4th diode D mutually AThe common port of 4 negative electrodes, A is the 4th diode D mutually A4 anode meets A the 4th bidirectional triode thyristor BCR mutually A4 the T2 utmost point and A be the 6th diode D mutually AThe common port of 6 anodes, A is the 4th bidirectional triode thyristor BCR mutually A4 the T1 utmost point meets A the 2nd diode D mutually A2 negative electrodes and A be the 6th diode D mutually AThe common port of 6 negative electrodes, A is the 3rd bidirectional triode thyristor BCR mutually A3 the control utmost point meets A the 22nd triode BG mutually A22 collector electrode, A is the 35th resistance R mutually A35 are connected in parallel on A the 1st diode D mutually A1 negative electrode and A be the 22nd triode BG mutually ABetween 22 the emitter, A is the 4th bidirectional triode thyristor BCR mutually A4 the control utmost point meets A the 23rd triode BG mutually A23 collector electrode, A is the 36th resistance R mutually A36 are connected in parallel on A the 2nd diode D mutually A2 negative electrodes and A be the 23rd triode (BG mutually A23) between the emitter, A is the 22nd triode BG mutually A22 base stages and A be the 23rd triode BG mutually A23 base stages all meet A the 1st field effect transistor NMOS mutually A1 drain electrode, A is the 1st field effect transistor NMOS mutually A1 grid and A be the 1st adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 1 series connection, A is the 1st field effect transistor NMOS mutually A1 source electrode, A be the 2nd field effect transistor NMOS mutually A2 source electrodes and A be the 5th triode BG mutually AThe common port of 5 base stages all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 1st field effect transistor NMOS mutually A1 source electrode and A be the 2nd adjustable resistance W mutually AMeet A the 5th triode BG mutually after 2 series connection A5 collector electrode, A is the 5th triode BG mutually A5 emitter meets A the 19th diode D mutually A19 anodes and A be the 20th diode D mutually AThe common port of 20 anodes, A is the 19th diode D mutually A19 negative electrode meets A the 1st diode D mutually A1 negative electrode, A is the 20th diode D mutually A20 negative electrode meets A the 2nd diode D mutually A2 negative electrode, A is the 5th resistance R mutually A5 are connected in parallel on A the 1st field effect transistor NMOS mutually ABetween 1 the source electrode and grid, A is the 2nd field effect transistor NMOS mutually A2 drain electrode and A be the 7th resistance R mutually AMeet A the 5th triode BG mutually after 7 series connection A5 collector electrode, A is the 2nd field effect transistor NMOS mutually A2 grid and A be the 3rd adjustable resistance W mutually AMeet the anodal E of the independent 12V power supply of auxiliary power circuit output after 3 series connection, A is the 9th resistance R mutually A9 are connected in parallel on A the 2nd field effect transistor NMOS mutually ABetween 2 the source electrode and grid, A is the 1st capacitor C mutually A1 is connected in parallel on A the 1st diode D mutually ABetween 1 the negative electrode and ground, A is the 2nd capacitor C mutually A2 are connected in parallel on A the 2nd diode D mutually ABetween 2 the anode and ground.
Embodiment 6: the three-phase adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply
The present invention is by ABC three-phase triode regulating circuit; ABC three-phase phase-veversal switch signal amplification circuit; ABC three-phase phase-veversal switch power circuit; ABC three-phase transformer load circuit; the load voltage sample circuit; load environmental change voltage sample circuit; the sampled signal amplifying circuit; the sampled signal control circuit; power protection starts to control signal generating circuit; ABC three-phase transformer current rectifying and wave filtering circuit; the phase-veversal switch signal generating circuit; auxiliary power circuit and independent current source circuit are formed; the triode regulating circuit of BC phase wherein; the phase-veversal switch signal amplification circuit; the phase-veversal switch power circuit; sampled signal control circuit according to electric power output voltage effective value fluctuating range control power input voltage; power protection starts to control signal generating circuit; the former limit of the transformer of transformer current rectifying and wave filtering circuit; transformer load circuit all element and the structure with A same item circuit is identical, and the load voltage sample circuit; load environmental change voltage sample circuit; the sampled signal amplifying circuit; sampled signal control circuit according to load environment control electric power output voltage frequency; the transformer secondary of three-phase transformer current rectifying and wave filtering circuit; filter capacitor; auxiliary power circuit and independent current source circuit three-phase are shared.
Three-phase signal generation circuit (SXXHFSDL) is used for a pair of phase-veversal switch signal of phase-locked loop intergrated circuit output is become three-phase phase-veversal switch signal, this three-phase phase-veversal switch signal can remove to drive three-phase phase-veversal switch power circuit after amplifying, thereby exports three-phase current on the three-phase transformer load circuit.

Claims (6)

1, a kind of adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply comprises three-phase transformer current rectifying and wave filtering circuit, phase-veversal switch signal generating circuit, auxiliary power circuit and independent current source circuit, it is characterized in that: also comprise triode regulating circuit (T A), the opposite phase switching signal amplifying circuit of A, the mutually anti-phase switching power circuit of A, A phase transformer load circuit, load voltage sample circuit, load environmental change voltage sample circuit, sampled signal amplifying circuit, sampled signal control circuit and power protection start to control signal generating circuit, wherein:
The opposite phase switching signal amplifying circuit of A is by A phase the 3rd field effect transistor (NMOS A3), A phase the 4th field effect transistor (NMOS A4), A phase 10--13 triode (BG A10--BG A13), A phase the 1st, 2 switching tube (IGBT A1, IGBT A2), A phase the 1st, 2 voltage-stabiliser tube (ZW A1, ZW A2), A phase 6--9 adjustable resistance (W A6--W A9), A phase 14--23 resistance (R A14--R A23) form, A is the 15th resistance (R mutually A15) one termination+12V voltage, A is another termination A phase the 10th triode (BG of the 15th resistance mutually A10) emitter, A is the 10th triode (BG mutually A10) collector electrode meets A the 11st triode (BG mutually A11) collector electrode, A is the 11st triode (BG mutually A11) grounded emitter, A is the 10th triode (BG mutually A10) base stage and A be the 16th resistance (R mutually A16) meet A the 11st triode (BG mutually after the series connection A11) base stage, A is the 14th resistance (R mutually A14) one termination+12V voltage, A is the other end and A the 6th adjustable resistance (W mutually of the 14th resistance mutually A6) meet A the 11st triode (BG mutually after the series connection A11) base stage and A the 3rd field effect transistor (NMOS mutually A3) Lou Ji common port, A is the 3rd field effect transistor (NMOS mutually A3) source ground, A is the 3rd field effect transistor (NMOS mutually A3) grid connects phase comparator output 2 pin of phase-locked loop intergrated circuit (IC3), and A is the 17th resistance (R mutually A17) be connected in parallel on A the 3rd field effect transistor (NMOS mutually A3) between the grid and ground, A is the 7th adjustable resistance (W mutually A7) a termination A is the 10th triode (BG mutually A10) collector electrode, A is the 7th adjustable resistance (W mutually A7) another termination A is the 1st switching tube (IGBT mutually A1) grid, A is the 18th resistance (R mutually A18) be connected in parallel on A the 1st switching tube (IGBT mutually A1) between the grid and ground, A is the 1st voltage-stabiliser tube (ZW mutually A1) negative electrode meets A the 1st switching tube (IGBT mutually A1) grid, A is the 1st voltage-stabiliser tube (ZW mutually A1) plus earth, A is the 1st switching tube (IGBT mutually A1) grounded emitter, A is the 20th resistance (R mutually A20) one termination+12V voltage, A is the 20th resistance (R mutually A20) another termination A is the 12nd triode (BG mutually A12) emitter, A is the 12nd triode (BG mutually A12) collector electrode meets A the 13rd triode (BG mutually A13) collector electrode, A is the 13rd triode (BG mutually A13) grounded emitter, A is the 12nd triode (BG mutually A12) base stage and A be the 21st resistance (R mutually A21) meet A the 13rd triode (BG mutually after the series connection A13) base stage, A is the 19th resistance (R mutually A19) one termination+12V voltage, A is the 19th resistance (R mutually A19) the other end and A be the 8th adjustable resistance (W mutually A8) meet A the 13rd triode (BG mutually after the series connection A13) base stage and A the 4th field effect transistor (NMOS mutually A4) Lou Ji common port, A is the 4th field effect transistor (NMOS mutually A4) source ground, A is the 4th field effect transistor (NMOS mutually A4) grid connects phase comparator input 3 pin and voltage controlled oscillator output 4 pin of phase-locked loop intergrated circuit (IC3), and A is the 22nd resistance (R mutually A22) be connected in parallel on A the 4th field effect transistor (NMOS mutually A4) between the grid and ground, A is the 9th adjustable resistance (W mutually A9) a termination A is the 12nd triode (BG mutually A12) collector electrode, A is the 9th adjustable resistance (W mutually A9) another termination A is the 2nd switching tube (IGBT mutually A2) grid, A is the 23rd resistance (R mutually A23) be connected in parallel on A the 2nd switching tube (IGBT mutually A2) between the grid and ground, A is the 2nd voltage-stabiliser tube (ZW mutually A2) negative electrode meets A the 2nd switching tube (IGBT mutually A2) grid, A is the 2nd voltage-stabiliser tube (ZW mutually A2) plus earth, A is the 2nd switching tube (IGBT mutually A2) grounded emitter;
The mutually anti-phase switching power circuit of A comprises A 26--29 triode (GTR mutually A3--GTR A6), A phase 6--9 triode (BG A6--BG A9), A phase the 4th, 5 adjustable resistance (W A4, W A5), A phase 10--13 resistance (R A10--R A13), A phase the 4th, 5 polar capacitor (C A4, C A5), A phase the 6th, 7 electric capacity (C A6, C A7), A phase 3--6 inductance (L A3--L A6) the A phase transformer (B that constitutes with the toroidal core circle A), A is the 26th triode (GTR mutually A3) emitter, A be the 28th triode (GTR mutually A5) emitter all meets A the 4th polar capacitor (C mutually A4), A phase the 5th polar capacitor (C A5) positive pole, A is the 4th polar capacitor (C mutually A4), A phase the 5th polar capacitor (C A5) the equal ground connection of negative pole, A is the 10th resistance (R mutually A10) a termination A is the 4th polar capacitor (C mutually A4), A phase the 5th polar capacitor (C A5) positive pole, A is the 10th resistance (R mutually A10) the other end and A be the 4th adjustable resistance (W mutually A4) meet A the 1st switching tube (IGBT mutually after the series connection A1) collector electrode, A be the 7th triode (BG mutually A7) base stage and A the 11st resistance (R mutually A11) common port of an end, A is the 11st resistance (R mutually A11) another termination A is the 6th triode (BG mutually A6) base stage, A is the 26th triode (GTR mutually A3) collector electrode meets A the 27th triode (GTR mutually A4) collector electrode, A phase the 6th triode (BG A6) collector electrode, A phase the 7th triode (BG A7) common port of collector electrode, A is the 26th triode (GTR mutually A3) base stage meets A the 6th triode (BG mutually A6) emitter, A is the 27th triode (GTR mutually A4) base stage meets A the 7th triode (BG mutually A7) emitter, A is the 27th triode (GTR mutually A4) grounded emitter, A is the 28th triode (GTR mutually A5) collector electrode meets A the 29th triode (GTR mutually A6) collector electrode, A phase the 8th triode (BG A8) collector electrode, A phase the 9th triode (BG A9) common port of collector electrode, A is the 28th triode (GTR mutually A5) base stage meets A the 8th triode (BG mutually A8) emitter, A is the 29th triode (GTR mutually A6) base stage meets A the 9th triode (BG mutually A9) emitter, A is the 29th triode (GTR mutually A6) grounded emitter, A is the 12nd resistance (R mutually A12) a termination A is the 4th polar capacitor (C mutually A4), A phase the 5th polar capacitor (C A5) positive pole, A is the 12nd resistance (R mutually A12) the other end and A be the 5th adjustable resistance (W mutually A5) meet A the 2nd switching tube (IGBT mutually after the series connection A2) collector electrode, A be the 9th triode (BG mutually A9) base stage and A the 13rd resistance (R mutually A13) common port of an end, A is the 13rd resistance (R mutually A13) another termination A is the 8th triode (BG mutually A8) base stage, A is the 6th electric capacity (C mutually A6) a termination A is the 26th triode (GTR mutually A3) collector electrode, A is the 6th electric capacity (C mutually A6) the other end and A phase transformer (B A) on A the 3rd inductance (L mutually A3) series connection back ground connection, A is the 7th electric capacity (C mutually A7) a termination A is the 28th triode (GTR mutually A5) collector electrode, A is the 7th electric capacity (C mutually A7) the other end and A phase transformer (B A) on A the 4th inductance (L mutually A4) series connection back ground connection; A is the 3rd inductance (L mutually A3), A phase the 4th inductance (L A4) end of the same name is in the same side;
A phase transformer load circuit is by A phase the 5th inductance (L A5), A phase the 8th electric capacity (C A8) and A phase load (Z A) form, A is the 8th electric capacity (C mutually A8) and A phase load (Z A) all be connected in parallel on transformer A phase (B A) on A the 5th inductance (L mutually A5) two ends;
The load voltage sample circuit is by the 3rd photoelectrical coupler (TLP3), 13--16 diode (D13-D16), the 6th resistance (R6), the 19th resistance (R19) and the 6th polar capacitor (C6) are formed, the 6th polar capacitor (C6) is connected in parallel between the common port of the common port of the 13rd diode (D13) anode and the 14th diode (D14) negative electrode and the 15th diode (D15) anode and the 16th diode (D16) negative electrode, the 13rd diode (D13), the negative electrode of the 15th diode (D15) all connects the positive pole of the 6th polar capacitor (C6), the 14th diode (D14), the anode of the 16th diode (D16) all connects the negative pole of the 6th polar capacitor (C6), the positive pole of one termination the 6th polar capacitor (C6) of the 19th resistance (R19), the anode of the photodiode of another termination the 3rd photoelectrical coupler (TLP3) of the 19th resistance (R19), the negative electrode of the photodiode of the 3rd photoelectrical coupler (TLP3) connects the negative pole of polarity the 6th electric capacity (C6), the collector electrode of the phototriode of the 3rd photoelectrical coupler (TLP3) connects+12V voltage, the common port of the end points Q3 of emitter order cutter three throw switches (K) of the 3rd photoelectrical coupler (TLP3) and the 6th resistance (R6) end, the other end ground connection of the 6th resistance (R6);
Load environmental change voltage sample circuit is by transducer (CHGQ), the 1st field effect transistor (NMOS1), the 2nd, 3 adjustable resistance (W2, W3) and the 4th, 5 resistance (R4, R5) form, the positive input terminal of transducer (CHGQ) with connect+12V voltage after the 4th resistance (R4) is connected, ground connection after the negative input end of transducer (CHGQ) is connected with the 2nd adjustable resistance (W2), the grid of positive output termination the 1st field effect transistor (NMOS1) of transducer (CHGQ), the common port of the source electrode of negative output termination the 1st field effect transistor (NMOS1) of transducer (CHGQ) and the end points Q2 of SP3T switch (K), the 5th resistance (R5) is connected in parallel on+common port of the drain electrode of 12V voltage and the 1st field effect transistor (NMOS1) and the end points Q1 of SP3T switch (K) between, the 3rd adjustable resistance (W3) is connected in parallel between the source electrode and ground of the 1st field effect transistor (NMOS1);
The sampled signal amplifying circuit is by the 4th, 5 integrated circuit (IC4, IC5), the 4th, 5 adjustable resistance (W4, W5), 7--14 resistance (R7-R14) is formed, the middle end points Q of positive input terminal order cutter three throw switches (K) of the 4th integrated circuit (IC4), the negative input end of the 4th integrated circuit (IC4) connects the 7th resistance (R7), the public connecting end of the 8th resistance (R8), another termination+12V voltage of the 7th resistance (R7), ground connection after the other end of the 8th resistance (R8) is connected with the 4th adjustable resistance (W4), the power end of the 4th integrated circuit (IC4) with connect+12V voltage after the 9th resistance (R9) is connected, the earth terminal ground connection of the 4th integrated circuit (IC4), the negative input end of output termination the 5th integrated circuit (IC5) of the 4th integrated circuit (IC4), positive input termination the 11st resistance (R11) of the 5th integrated circuit (IC5), the public connecting end of the 12nd resistance (R12), another termination+12V voltage of the 11st resistance (R11), ground connection after the other end of the 12nd resistance (R12) is connected with the 5th adjustable resistance (W5), the power end of the 5th integrated circuit (IC5) with connect+12V voltage earth terminal ground connection after the 13rd resistance (R13) is connected;
The sampled signal control circuit is formed by the sampled signal control circuit of foundation electric power output voltage effective value fluctuating range control power input voltage with according to the sampled signal control circuit of load environment control electric power output voltage frequency;
The sampled signal control circuit of controlling power input voltage according to electric power output voltage effective value fluctuating range is by A phase the 1st, 2 photoelectrical coupler (TLP A1, TLP A2), A phase 6--8 resistance (R A6--R A8), the 10th resistance (R10), A phase the 14th resistance (R14) are formed A phase the 1st photoelectrical coupler (TLP to A mutually AThe anode of photodiode 1) connects the output of the 4th integrated circuit (IC4), and A is the 1st photoelectrical coupler (TLP mutually AGround connection after the negative electrode of photodiode 1) is connected with the 10th resistance (R10), A is the 1st photoelectrical coupler (TLP mutually AThe collector electrode of phototriode 1) and A be the 8th resistance (R mutually A8) meet A the 2nd field effect transistor (NMOS mutually after the series connection A2) grid, A is the 1st photoelectrical coupler (TLP mutually AThe emitter of phototriode 1) meets A the 5th triode (BG mutually A5) base stage, A is the 2nd photoelectrical coupler (TLP mutually AThe anode of photodiode 2) connects the output of the 5th integrated circuit (IC5), and A is the 2nd photoelectrical coupler (TLP mutually AGround connection after the negative electrode of photodiode 2) is connected with the 14th resistance (R14), A is the 2nd photoelectrical coupler (TLP mutually AThe collector electrode of phototriode 2) meets A the 5th triode (BG mutually A5) collector electrode, A is the 2nd photoelectrical coupler (TLP mutually AThe emitter of phototriode 2) and A be the 6th resistance (R mutually A6) meet A the 2nd field effect transistor (NMOS mutually after the series connection A2) drain electrode, A is the 7th resistance (R mutually A7) be connected in parallel on A the 2nd field effect transistor (NMOS mutually A2) drain electrode and A be the 5th triode (BG mutually A5) between the collector electrode;
Control the sampled signal control circuit of electric power output voltage frequency by the 1st according to the load environment, 2 photoelectrical coupler (TLP1, TLP2), the 1st, 2 resistance (R1, R2) form, the anode of the photodiode of the 1st photoelectrical coupler (TLP1) connects the output of the 5th integrated circuit (IC5), ground connection after the negative electrode of the photodiode of the 1st photoelectrical coupler (TLP1) is connected with the 14th resistance (R14), the collector electrode of the phototriode of the 1st photoelectrical coupler (TLP1) with connect+12V voltage after the 1st resistance (R1) is connected, the emitter of the phototriode of the 1st photoelectrical coupler (TLP1) connects the sliding end of the 1st adjustable resistance (W1), the anode of the photodiode of the 2nd photoelectrical coupler (TLP2) connects the output of the 4th integrated circuit (IC4), ground connection after the negative electrode of the photodiode of the 2nd photoelectrical coupler (TLP2) is connected with the 10th resistance (R10), the collector electrode of the phototriode of the 2nd photoelectrical coupler (TLP2) and the emitter that connects the phototriode of the 1st photoelectrical coupler (TLP1) after the 2nd resistance (R2) is connected, the grounded emitter of the phototriode of the 2nd photoelectrical coupler (TLP2);
Power protection starts to control signal generating circuit by the 2nd field effect transistor (NMOS 2), the 1st triode (BG1), A phase the 3rd photoelectrical coupler (TLP A3), the 11st, 12 diode (D11, D12), the 6th adjustable resistance (W6), 15--18 resistance (R15--R18), the 7th polar capacitor (C7), light-emitting diode (LED) and loud speaker (SPK) are formed, the anode of the 11st diode (D11) connects the output of the 4th integrated circuit (IC4), the negative electrode of the 11st diode (D11) connects the 2nd field effect transistor (NMOS 2) grid and the anodal common port of the 7th polar capacitor (C7), the minus earth of the 7th polar capacitor (C7), the 15th resistance (R15) is connected in parallel on the two ends of the 4th polar capacitor (C4), the drain electrode of the 2nd field effect transistor (NMOS 2) with connect+12V voltage after the 16th resistance (R16) is connected, the source electrode of the 2nd field effect transistor (NMOS 2) connects the anode of the 12nd diode (D12), the negative electrode of the 12nd diode (D12) connects the sliding end of the 6th adjustable resistance (W6), one termination of the 17th resistance (R17)+12V voltage, ground connection after the other end of the 17th resistance (R17) is connected with the 6th adjustable resistance (W6), the emitter of the 1st triode (BG1) with connect+12V voltage after the 18th resistance (R18) is connected, the base stage of the 1st triode (BG1) connects the drain electrode of the 2nd field effect transistor (NMOS 2), the anode of sending and receiving optical diodes (LED) after the collector electrode of the 1st triode (BG1) is connected with loud speaker (SPK), the negative electrode of light-emitting diode (LED) meet A the 3rd photoelectrical coupler (TLP mutually AThe anode of photodiode 3), A is the 3rd photoelectrical coupler (TLP mutually AThe minus earth of photodiode 3), A is the 3rd photoelectrical coupler (TLP mutually AThe collector electrode of phototriode 3) meets A the 1st field effect transistor (NMOS mutually A1) grid, A is the 3rd photoelectrical coupler (TLP mutually AThe emitter of phototriode 3) meets A the 1st field effect transistor (NMOS mutually A1) source electrode.
2, adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply as claimed in claim 1 is characterized in that: described triode regulating circuit (T A) comprise A phase fuse (BX A), A the 24th, 25 triode (GTR mutually A1, GTR A2), A phase 1--5 triode (BG A1--BG A5), A phase the 1st, 2 field effect transistor (NMOS A1, NMOS A2), A phase 1--10 diode (D A1-D A10), A phase 1--3 adjustable resistance (W A1--W A3), A phase 1--9 resistance (R A1-R A9), A phase 1--3 electric capacity (C A1--C A3), A phase the 24th triode (GTR A1) collector electrode and A be fuse (BX mutually A) connecing the end of civil power 380V after the series connection, A is the 24th triode (GTR mutually A1) emitter meets A the 3rd diode (D mutually A3) anode and A the 5th diode (D mutually A5) common port of anode, A is the 3rd diode (D mutually A3) negative electrode meets A the 1st diode (D mutually A1) anode, A phase the 2nd diode (D A2) anode and A the 4th diode (D mutually A4) common port of negative electrode, A is the 4th diode (D mutually A4) anode meets A the 25th triode (GTR mutually A2) emitter and A the 6th diode (D mutually A6) common port of anode, A is the 24th triode (GTR mutually A1) base stage meets A the 1st triode (BG mutually A1) emitter, A is the 1st resistance (R mutually A1) is connected in parallel on A the 24th triode (GTR mutually A1) collector electrode and A be the 1st triode (BG mutually A1) between the collector electrode, A is the 1st triode (BG mutually A1) base stage meets A the 3rd triode (BG mutually A3) collector electrode, A is the 3rd resistance (R mutually A3) be connected in parallel on A the 3rd triode (BG mutually A3) emitter and A be the 24th triode (GTR mutually A1) between the collector electrode, A is the 25th triode (GTR mutually A2) base stage meets A the 2nd triode (BG mutually A2) emitter, A is the 2nd resistance (R mutually A2) be connected in parallel on A the 25th triode (GTR mutually A2) collector electrode and A be the 2nd triode (BG mutually A2) between the collector electrode, A is the 2nd triode (BG mutually A2) base stage meets A the 4th triode (BG mutually A4) collector electrode, A is the 4th resistance (R mutually A4) be connected in parallel on A the 4th triode (BG mutually A4) emitter and A be the 25th triode (GTR mutually A2) between the collector electrode, A is the 1st diode (D mutually A1) negative electrode and A the 5th diode (D mutually A5) public termination A phase the 24th triode (GTR of negative electrode A1) collector electrode, A is the 2nd diode (D mutually A2) negative electrode and A the 6th diode (D mutually A6) public termination A phase the 25th triode (GTR of negative electrode A2) collector electrode, A is the 3rd triode (BG mutually A3) base stage and A the 4th triode (BG mutually A4) base stage all meets A the 8th diode (D mutually A8) negative electrode, A is the 8th diode (D mutually A8) anode meets A the 1st field effect transistor (NMOS mutually A1) drain electrode, A is the 1st field effect transistor (NMOS mutually A1) grid and A be the 1st adjustable resistance (W mutually A1) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 1st field effect transistor (NMOS mutually A1) source electrode and A be the 2nd adjustable resistance (W mutually A2) meet A the 5th triode (BG mutually after the series connection A5) collector electrode, A is the 1st field effect transistor (NMOS mutually A1) source electrode, A phase the 2nd field effect transistor (NMOS A2) source electrode and A the 5th triode (BG mutually A5) common port of base stage all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 5th triode (BG mutually A5) emitter meets A the 9th diode (D mutually A9) anode and A the 10th diode (D mutually A10) common port of anode, A is the 9th diode (D mutually A9) negative electrode meets A the 24th triode (GTR mutually A1) collector electrode, A is the 10th diode (D mutually A10) negative electrode meets A the 25th triode (GTR mutually A2) collector electrode, A is the 7th diode (D mutually A7) with A the 8th diode (D mutually A8) reverse parallel connection, A is the 5th resistance (R mutually A5) be connected in parallel on A the 1st field effect transistor (NMOS mutually A1) between the source electrode and grid, A is the 2nd field effect transistor (NMOS mutually A2) drain electrode and A be the 7th resistance (R mutually A7) meet A the 5th triode (BG mutually after the series connection A5) collector electrode, A is the 2nd field effect transistor (NMOS mutually A2) grid and A be the 3rd adjustable resistance (W mutually A3) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 9th resistance (R mutually A9) be connected in parallel on A the 2nd field effect transistor (NMOS mutually A2) between the source electrode and grid, A is the 1st electric capacity (C mutually A1) is connected in parallel on A the 24th triode (GTR mutually A1) between the collector electrode and ground, A is the 2nd electric capacity (C mutually A2) be connected in parallel on A the 25th triode (GTR mutually A2) between the collector electrode and ground, A is the 3rd electric capacity (C mutually A3) be connected in parallel on A the 8th diode (D mutually A8) anode and A be the 28th triode (GTR mutually A5) between the emitter.
3, adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply as claimed in claim 1 is characterized in that: described triode regulating circuit (T A) comprise A phase fuse (BX A), A the 30th, 31 triode (GTR mutually A7, GTR A8), A phase 13-16 triode (BG A13--BG A16), A phase the 1st, 2 field effect transistor (NMOS A1, NMOS A2), A phase 1--10 diode (D A1-D A10), A phase 1--3 adjustable resistance (W A1--W A3), A phase 5--9 resistance (R A5-R A9), A phase 24-27 resistance (R A24-R A27), A phase 1--3 electric capacity (C A1--C A3), A phase the 30th triode (GTR A7) emitter and A be fuse (BX mutually A) connecing the end of civil power 380V after the series connection, A is the 30th triode (GTR mutually A7) collector electrode meets A the 3rd diode (D mutually A3) anode and A the 5th diode (D mutually A5) common port of anode, A is the 3rd diode (D mutually A3) negative electrode meets A the 1st diode (D mutually A1) anode, A phase the 2nd diode (D A2) anode and A the 4th diode (D mutually A4) common port of negative electrode, A is the 4th diode (D mutually A4) anode meets A the 31st triode (GTR mutually A8) collector electrode and A the 6th diode (D mutually A6) common port of anode, A is the 30th triode (GTR mutually A7) base stage meets A the 13rd triode (BG mutually A13) emitter, A is the 24th resistance (R mutually A24) be connected in parallel on A the 13rd triode (BG mutually A13) collector electrode and A be the 3rd diode (D mutually A3) between the negative electrode, A is the 13rd triode (BG mutually A13) base stage meets A the 15th triode (BG mutually A15) emitter, A is the 26th resistance (R mutually A26) be connected in parallel on A the 15th triode (BG mutually A15) collector electrode and A be the 3rd diode (D mutually A3) between the negative electrode, A is the 31st triode (GTR mutually A8) base stage meets A the 14th triode (BG mutually A14) emitter, A is the 25th resistance (R mutually A25) be connected in parallel on A the 14th triode (BG mutually A14) collector electrode and A be the 3rd diode (D mutually A3) between the negative electrode, A is the 14th triode (BG mutually A14) base stage meets A the 16th triode (BG mutually A16) emitter, A is the 27th resistance (R mutually A27) be connected in parallel on A the 16th triode (BG mutually A16) collector electrode and A be the 3rd diode (D mutually A3) between the negative electrode, A is the 1st diode (D mutually A1) negative electrode and A the 5th diode (D mutually A5) public termination A phase the 30th triode (GTR of negative electrode A7) emitter, A is the 2nd diode (D mutually A2) negative electrode and A the 6th diode (D mutually A6) public termination A phase the 31st triode (GTR of negative electrode A8) emitter, A is the 15th triode (BG mutually A15) base stage and A the 16th triode (BG mutually A16) base stage all meets A the 8th diode (D mutually A8) negative electrode, A is the 8th diode (D mutually A8) anode meets A the 1st field effect transistor (NMOS mutually A1) drain electrode, A is the 1st field effect transistor (NMOS mutually A1) grid and A be the 1st adjustable resistance (W mutually A1) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 1st field effect transistor (NMOS mutually A1) source electrode and A be the 2nd adjustable resistance (W mutually A2) meet A the 5th triode (BG mutually after the series connection A5) collector electrode, A is the 1st field effect transistor (NMOS mutually A1) source electrode, A phase the 2nd field effect transistor (NMOS A2) source electrode and A the 5th triode (BG mutually A5) common port of base stage all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 5th triode (BG mutually A5) emitter meets A the 9th diode (D mutually A9) anode and A the 10th diode (D mutually A10) common port of anode, A is the 9th diode (D mutually A9) negative electrode meets A the 30th triode (GTR mutually A7) emitter, A is the 10th diode (D mutually A10) negative electrode meets A the 31st triode (GTR mutually A8) emitter, A is the 7th diode (D mutually A7) with A the 8th diode (D mutually A8) reverse parallel connection, A is the 5th resistance (R mutually A5) be connected in parallel on A the 1st field effect transistor (NMOS mutually A1) between the source electrode and grid, A is the 2nd field effect transistor (NMOS mutually A2) drain electrode and A be the 7th resistance (R mutually A7) meet A the 5th triode (BG mutually after the series connection A5) collector electrode, A is the 2nd field effect transistor (NMOS mutually A2) grid and A be the 3rd adjustable resistance (W mutually A3) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 9th resistance (R mutually A9) be connected in parallel on A the 2nd field effect transistor (NMOS mutually A2) between the source electrode and grid, A is the 1st electric capacity (C mutually A1) is connected in parallel on A the 30th triode (GTR mutually A7) between the emitter and ground, A is the 2nd electric capacity (C mutually A2) be connected in parallel on A the 31st triode (GTR mutually A)8) between the emitter and ground, A is the 3rd electric capacity (C mutually A3) be connected in parallel on A the 8th diode (D mutually A8) anode and A be the 5th triode (BG mutually A5) between the emitter.
4, adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply as claimed in claim 1 is characterized in that: described triode regulating circuit (T A) comprise A phase fuse (BX A), A the 32nd, 33 triode (GTR mutually A9, GTR A10), A phase 17-21 triode (BG A17--BG A21), A phase the 1st, 2 field effect transistor (NMOS A1, NMOS A2), A phase the 7th, 8 diode (D A7, D A8), A phase 11-18 diode (D A11--D A18), A phase 1--3 adjustable resistance (W A1--W A3), A phase 5--9 resistance (R A5-R A9), A phase 28-31 resistance (R A28--R A31), A phase 1--3 electric capacity (C A1--C A3), A phase the 11st diode (D A11) anode and A the 13rd diode (D mutually A13) common port of negative electrode and A fuse (BX mutually A) connecing the end of civil power 380V after the series connection, A is the 13rd diode (D mutually A13) anode and A the 15th diode (D mutually A15) public termination A phase the 32nd triode (GTR of anode A9) collector electrode, A is the 11st diode (D mutually A11) negative electrode meets A the 12nd diode (D mutually A12) negative electrode, A phase the 15th diode (D A15) negative electrode, A phase the 16th diode (D A16) negative electrode and A the 31st triode (GTR mutually A8) common port of emitter, A is the 32nd triode (GTR mutually A9) base stage meets A the 17th triode (BG mutually A17) emitter, A is the 28th resistance (R mutually A28) be connected in parallel on A the 17th triode (BG mutually A17) collector electrode and A be the 13rd diode (D mutually A13) between the negative electrode, A is the 17th triode (BG mutually A17) base stage meets A the 19th triode (BG mutually A19) collector electrode, A is the 30th resistance (R mutually A30) be connected in parallel on A the 19th triode (BG mutually A19) emitter and A be the 13rd diode (D mutually A13) between the negative electrode, A is the 14th diode (D mutually A14) anode and A the 16th diode (D mutually A16) public termination A phase the 33rd triode (GTR of anode A10) collector electrode, A is the 33rd triode (GTR mutually A10) base stage meets A the 18th triode (BG mutually A18) emitter, A is the 29th resistance (R mutually A29) be connected in parallel on A the 18th triode (BG mutually A18) collector electrode and A be the 14th diode (D mutually A14) between the negative electrode, A is the 18th triode (BG mutually A18) base stage meets A the 20th triode (BG mutually A20) collector electrode, A is the 31st resistance (R mutually A31) be connected in parallel on A the 20th triode (BG mutually A20) emitter and A be the 14th diode (D mutually A14) between the negative electrode, A is the 19th triode (BG mutually A19) base stage and A the 20th triode (BG mutually A20) base stage all meets A the 8th diode (D mutually A8) negative electrode, A is the 8th diode (D mutually A8) anode meets A the 1st field effect transistor (NMOS mutually A1) source electrode, A is the 1st field effect transistor (NMOS mutually A1) source electrode, A phase the 2nd field effect transistor (NMOS A2) source electrode and A the 21st triode (BG mutually A21) common port of base stage all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 1st field effect transistor (NMOS mutually A1) grid and A be the 1st adjustable resistance (W mutually A1) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 1st field effect transistor (NMOS mutually A1) drain electrode and A be the 2nd adjustable resistance (W mutually A2) meet A the 21st triode (BG mutually after the series connection A21) emitter, A is the 21st triode (BG mutually A21) collector electrode meets A the 17th diode (D mutually A17) negative electrode and A the 18th diode (D mutually A18) common port of negative electrode, A is the 17th diode (D mutually A17) anode meets A the 11st diode (D mutually A11) anode, A is the 18th diode (D mutually A18) anode meets A the 12nd diode (D mutually A12) anode, A is the 7th diode (D mutually A7) with A the 8th diode (D mutually A8) reverse parallel connection, A is the 5th resistance (R mutually A5) be connected in parallel on A the 1st field effect transistor (NMOS mutually A1) between the source electrode and grid, A is the 2nd field effect transistor (NMOS mutually A2) drain electrode and A be the 7th resistance (R mutually A7) meet A the 21st triode (BG mutually after the series connection A21) collector electrode, A is the 2nd field effect transistor (NMOS mutually A2) grid and A be the 3rd adjustable resistance (W mutually A3) connect the positive pole (E) of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 9th resistance (R mutually A9) be connected in parallel on A the 2nd field effect transistor (NMOS mutually A2) between the source electrode and grid, A is the 1st electric capacity (C mutually A1) is connected in parallel on A the 11st diode (D mutually A11) between the anode and ground, A is the 2nd electric capacity (C mutually A2) be connected in parallel on A the 12nd diode (D mutually A12) between the anode and ground, A is the 3rd electric capacity (C mutually A3) be connected in parallel on A the 8th diode (D mutually A8) anode and A be the 21st triode (BG mutually A21) between the collector electrode.
5, adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply as claimed in claim 1 is characterized in that: described triode regulating circuit (T A) comprise A phase fuse (BX A), A the 1st, 2 bidirectional triode thyristor (BCR mutually A1, BCR A2), A phase the 5th, 6 field effect transistor (NMOS A5, NMOS A6), A phase the 3rd, 4 voltage stabilizing didoe (ZW A3, ZW A4), A phase 1--6 diode (D A1--D A6), A phase the 9th, 10 diode (D A9, D A10), A phase the 9th adjustable resistance (W A9), A phase 32--34 resistance (R A32-R A34), A phase the 1st bidirectional triode thyristor (BCR A1) the T1 utmost point, A be the 1st diode (D mutually A1) negative electrode and A the 5th diode (D mutually A5) common port of negative electrode and A fuse (BX mutually A) connecing the end of civil power 380V after the series connection, A is the 1st bidirectional triode thyristor (BCR mutually A1) the T2 utmost point meets A the 3rd diode (D mutually A3) anode and A the 5th diode (D mutually A5) common port of anode, A is the 3rd diode (D mutually A3) negative electrode meets A the 1st diode (D mutually A1) anode, A phase the 2nd diode (D A2) anode and A the 4th diode (D mutually A4) common port of negative electrode, A is the 4th diode (D mutually A4) anode meets A the 2nd bidirectional triode thyristor (BCR mutually A2) the T2 utmost point and A be the 6th diode (D mutually A6) common port of anode, A is the 1st bidirectional triode thyristor (BCR mutually A2) the T1 utmost point meets A the 2nd diode (D mutually A2) negative electrode and A the 6th diode (D mutually A6) common port of negative electrode, A is the 1st bidirectional triode thyristor (BCR mutually A1) the control utmost point meets A the 5th field effect transistor (NMOS mutually A5) source electrode and A the 3rd voltage stabilizing didoe (ZW mutually A3) common port of anode, A is the 32nd resistance (R mutually A32) be connected in parallel on A the 1st diode (D mutually A1) negative electrode and A the 5th field effect transistor (NMOS mutually A5) between the drain electrode, A is the 2nd bidirectional triode thyristor (BCR mutually A2) the control utmost point meets A the 6th field effect transistor (NMOS mutually A6) source electrode and A the 4th voltage stabilizing didoe (ZW mutually A4) common port of anode, A is the 33rd resistance (R mutually A33) be connected in parallel on A the 2nd diode (D mutually A2) negative electrode and A the 6th field effect transistor (NMOS mutually A6) between the drain electrode, A is the 9th adjustable resistance (W mutually A9) a termination A is the 3rd diode (D mutually A3) negative electrode and A the 4th diode (D mutually A4) common port of negative electrode, A is the 9th adjustable resistance (W mutually A9) the other end and A be the 34th resistance (R mutually A34) meet A the 9th diode (D mutually after the series connection A9) negative electrode and A the 10th diode (D mutually A10) common port of negative electrode, A is the 9th adjustable resistance (W mutually A9) slip termination A is the 5th field effect transistor (NMOS mutually A5) grid, A phase the 6th field effect transistor (NMOS A6) grid, A phase the 3rd voltage stabilizing didoe (ZW A3) negative electrode, A phase the 4th voltage stabilizing didoe (ZW A4) common port of negative electrode, A is the 9th diode (D mutually A9) anode meets A the 1st diode (D mutually A1) negative electrode, A is the 10th diode (D mutually A10) anode meets A the 2nd diode (D mutually A2) negative electrode, the A in the sampled signal control circuit is the 1st photoelectrical coupler (TLP mutually AThe collector electrode of the phototriode 1) meets A the 9th adjustable resistance (W mutually A9) sliding end, A is the 1st photoelectrical coupler (TLP mutually AThe emitter of the phototriode 1) and A be the 8th resistance (R mutually A8) meet A the 3rd diode (D mutually after the series connection A3) negative electrode, A is the 2nd photoelectrical coupler (TLP mutually AThe collector electrode of the phototriode 2) meets A the 9th adjustable resistance (W mutually A9) with A the 34th resistance (R mutually A34) public connecting end, A is the 2nd photoelectrical coupler (TLP mutually AThe emitter of the phototriode 2) and A be the 6th resistance (R mutually A6) meet A the 9th adjustable resistance (W mutually after the series connection A9) sliding end, A is the 3rd photoelectrical coupler (TLP mutually AThe collector electrode of the phototriode 3) meets A the 3rd diode (D mutually A3) negative electrode, A is the 3rd photoelectrical coupler (TLP mutually AThe emitter of the phototriode 3) meets A the 9th adjustable resistance (W mutually A9) sliding end, A is the 1st electric capacity (C mutually A1) is connected in parallel on A the 1st diode (D mutually A1) between the negative electrode and ground, A is the 2nd electric capacity (C mutually A2) be connected in parallel on A the 2nd diode (D mutually A2) between the negative electrode and ground.
6, adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply as claimed in claim 1 is characterized in that: described triode regulating circuit (T A) comprise A phase fuse (BX A), A the 3rd, 4 bidirectional triode thyristor (BCR mutually A3, BCR A4), A phase the 5th triode (BG A5), A phase the 22nd, 23 triode (BG A22, BG A23), A phase the 1st, 2 field effect transistor (NMOS A1, NMOS A2), A phase 1--6 diode (D A1--D A6), A phase the 19th, 20 diode (D A19, D A20), A phase 1--3 adjustable resistance (W A1--W A3), A phase 5--9 resistance (R A5-R A9), A phase the 35th, 36 resistance (R A35, R A36), A phase the 3rd bidirectional triode thyristor (BCR A3) the T1 utmost point, A be the 1st diode (D mutually A1) negative electrode and A the 5th diode (D mutually A5) common port of negative electrode and A fuse (BX mutually A) connecing the end of civil power 380V after the series connection, A is the 3rd bidirectional triode thyristor (BCR mutually A3) the T2 utmost point meets A the 3rd diode (D mutually A3) anode and A the 5th diode (D mutually A5) common port of anode, A is the 3rd diode (D mutually A3) negative electrode meets A the 1st diode (D mutually A1) anode, A phase the 2nd diode (D A2) anode and A the 4th diode (D mutually A4) common port of negative electrode, A is the 4th diode (D mutually A4) anode meets A the 4th bidirectional triode thyristor (BCR mutually A4) the T2 utmost point and A be the 6th diode (D mutually A6) common port of anode, A is the 4th bidirectional triode thyristor (BCR mutually A4) the T1 utmost point meets A the 2nd diode (D mutually A2) negative electrode and A the 6th diode (D mutually A6) common port of negative electrode, A is the 3rd bidirectional triode thyristor (BCR mutually A3) the control utmost point meets A the 22nd triode (BG mutually A22) collector electrode, A is the 35th resistance (R mutually A35) be connected in parallel on A the 1st diode (D mutually A1) negative electrode and A the 22nd triode (BG mutually A22) between the emitter, A is the 4th bidirectional triode thyristor (BCR mutually A4) the control utmost point meets A the 23rd triode (BG mutually A23) collector electrode, A is the 36th resistance (R mutually A36) be connected in parallel on A the 2nd diode (D mutually A2) negative electrode and A the 23rd triode (BG mutually A23) between the emitter, A is the 22nd triode (BG mutually A22) base stage and A the 23rd triode (BG mutually A23) base stage all meets A the 1st field effect transistor (NMOS mutually A1) drain electrode, A is the 1st field effect transistor (NMOS mutually A1) grid and A be the 1st adjustable resistance (W mutually A1) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 1st field effect transistor (NMOS mutually A1) source electrode, A phase the 2nd field effect transistor (NMOS A2) source electrode and A the 5th triode (BG mutually A5) common port of base stage all meets the negative pole F of the independent 12V power supply of auxiliary power circuit output, and A is the 1st field effect transistor (NMOS mutually A1) source electrode and A be the 2nd adjustable resistance (W mutually A2) meet A the 5th triode (BG mutually after the series connection A5) collector electrode, A is the 5th triode (BG mutually A5) emitter meets A the 19th diode (D mutually A19) anode and A the 20th diode (D mutually A20) common port of anode, A is the 19th diode (D mutually A19) negative electrode meets A the 1st diode (D mutually A1) negative electrode, A is the 20th diode (D mutually A20) negative electrode meets A the 2nd diode (D mutually A2) negative electrode, A is the 5th resistance (R mutually A5) be connected in parallel on A the 1st field effect transistor (NMOS mutually A1) between the source electrode and grid, A is the 2nd field effect transistor (NMOS mutually A2) drain electrode and A be the 7th resistance (R mutually A7) meet A the 5th triode (BG mutually after the series connection A5) collector electrode, A is the 2nd field effect transistor (NMOS mutually A2) grid and A be the 3rd adjustable resistance (W mutually A3) meet the anodal E of the independent 12V power supply of auxiliary power circuit output after the series connection, A is the 9th resistance (R mutually A9) be connected in parallel on A the 2nd field effect transistor (NMOS mutually A2) between the source electrode and grid, A is the 1st electric capacity (C mutually A1) is connected in parallel on A the 1st diode (D mutually A1) between the negative electrode and ground, A is the 2nd electric capacity (C mutually A2) be connected in parallel on A the 2nd diode (D mutually A2) between the anode and ground.
CNB2006100187795A 2006-04-12 2006-04-12 Adjustable frequency-stabilizing voltage-stabilizing variable-frequency variable-voltage power supply Expired - Fee Related CN100459395C (en)

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CN101858934B (en) * 2009-04-10 2012-08-22 北京动力源科技股份有限公司 Method and system for implementing program controlled alternating current source
WO2011090048A1 (en) * 2010-01-19 2011-07-28 株式会社村田製作所 Frequency stabilization circuit, frequency stabilization device, antenna device, communication terminal apparatus, and impedance transformation element
CN102142811B (en) * 2010-02-01 2013-02-13 华东师范大学 Low-noise CMOS (complementary metal oxide semiconductor) voltage-controlled oscillation circuit based on low-voltage difference voltage regulator
CN101867307B (en) * 2010-07-12 2012-07-04 天津市东文高压电源厂 Ozone high-voltage power supply
CN102266935B (en) * 2011-06-29 2014-08-27 章祖文 Casting device composed of alternated current/direct current gas shielded electric welder and mobile intermediate frequency mould
CN110006020A (en) * 2019-04-08 2019-07-12 章祖文 The manufacturing method of simple and fast temperature controllable timing originally hot water and steam device

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