CN104505922B - A kind of wireless charger with WIFI function - Google Patents
A kind of wireless charger with WIFI function Download PDFInfo
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- CN104505922B CN104505922B CN201410740566.8A CN201410740566A CN104505922B CN 104505922 B CN104505922 B CN 104505922B CN 201410740566 A CN201410740566 A CN 201410740566A CN 104505922 B CN104505922 B CN 104505922B
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Abstract
The invention discloses a kind of wireless charger with WIFI function, it includes microprocessor module, microprocessor module connects the WIFI chip circuit having for microprocessor module synchronous communication transmission data, WIFI chip circuit is connected by wave filter the antenna realizing data communication for the communication equipment with outside with WIFI function, WIFI chip circuit has chip selection signal input, clock signal input terminal, data receiver, data sending terminal, sleep signal input and interrupt signal outfan, microprocessor module has sheet selected control signal output part, clock control signal outfan, data sending terminal, data receiver, dormancy drives signal output part and interrupt signal input；Advantage is for the WIFI chip circuit with microprocessor module synchronous communication transmission data by connection one on microprocessor module, makes this wireless charger can carry out data interaction and communication by WIFI interface with the outside communication equipment (including being electrically charged equipment) with WIFI function.
Description
Technical field
The present invention relates to a kind of wireless charging technology, especially relate to a kind of wireless charger with WIFI function, it can realize data communication by WIFI.
Background technology
Current wireless charging technology is with induction the most popular with magnetic resonance type.The feature of induction wireless charging technology is that charging distance diameter short, induction coil is smaller, operating frequency ratio is relatively low, is primarily now main industry standard with QI standard；The feature of magnetic resonance type wireless charging technology is that charging distance is relatively long, induction coil diameter is bigger, operating frequency is higher, is primarily now main industry standard with A4WP standard.
But, either wireless charger based on QI standard is also based on the wireless charger of A4WP standard, it is problematic in that, i.e. charger cannot carry out data communication with external communication device (including being electrically charged equipment), cannot be carried out the control in charging process and monitoring, the widely use of wireless charger of such large effect.
Summary of the invention
The technical problem to be solved is to provide a kind of wireless charger with WIFI function, it can make charger and carry out data interaction and communication between the external communication device being electrically charged including equipment, it is achieved the monitoring and control to wireless charging process.
nullThe present invention solves the technical scheme that above-mentioned technical problem used: a kind of wireless charger with WIFI function，Including microprocessor module，It is characterized in that described microprocessor module connects the WIFI chip circuit having for described microprocessor module synchronous communication transmission data，Described WIFI chip circuit is connected by wave filter the antenna realizing data communication for the communication equipment with outside with WIFI function，Described WIFI chip circuit has chip selection signal input、Clock signal input terminal、Data receiver、Data sending terminal、Sleep signal input and interrupt signal outfan，Described microprocessor module has sheet selected control signal output part、Clock control signal outfan、Data sending terminal、Data receiver、Dormancy drives signal output part and interrupt signal input；After described microprocessor module wakes up up from Low-power-consumptiodormancy dormancy pattern, after described microprocessor module drives the signal output part output drive signal sleep signal input to described WIFI chip circuit by its dormancy, described WIFI chip circuit is started working；Described WIFI chip circuit gives the interrupt signal input of described microprocessor module by the interrupt signal of the WIFI chip circuit generation described in the output of its interrupt signal outfan, and after described microprocessor module gives the chip selection signal input of described WIFI chip circuit by its sheet selected control signal output part output low level signal, described WIFI chip circuit and described microprocessor module start synchronous communication transmission data.
Described microprocessor module is also associated with for by the power conversion circuit of converting direct-current power into alternating-current power and the signal pre-processing circuit being used for being demodulated to modulated signal demodulated signal, and described power conversion circuit connects to be had and be electrically charged on equipment on the wireless charging receptor installed the transmitting coil that the receiving coil being connected matches；nullDescribed microprocessor module provides two-way pulse-width signal to described power conversion circuit，Described power conversion circuit produces high frequency ac signal after receiving two-way pulse-width signal，The high frequency ac signal that described power conversion circuit produces is coupled in described wireless charging receptor by described transmitting coil and described receiving coil，The modulated signal that it is modulated obtaining including charging status information after receiving high frequency ac signal by described wireless charging receptor，Described wireless charging receptor is fed back by described receiving coil and described transmitting coil and includes the modulated signal of charging status information to described signal pre-processing circuit，Described signal pre-processing circuit is demodulated to include the demodulated signal of charging status information after receiving the modulated signal including charging status information，Described signal pre-processing circuit provides and includes the demodulated signal of charging status information to described microprocessor module，Described microprocessor module transmits its data including charging status information obtained to the data receiver of described WIFI chip circuit by its data sending terminal，Described WIFI chip circuit includes the data of charging status information by described antenna transmission and has the communication equipment of WIFI function to outside，Outside has after the communication equipment of WIFI function sends instructions to described microprocessor module by described WIFI chip circuit，Wireless charging process is controlled by described microprocessor module.
nullDescribed microprocessor module is made up of the peripheral circuit of the single-chip microcomputer that model is STM32F103C8T6 and described single-chip microcomputer，29th foot of described single-chip microcomputer and the 30th foot are connected with described power conversion circuit respectively，11st foot of described single-chip microcomputer、12nd foot and the 13rd foot are connected with described signal pre-processing circuit respectively，14th foot of described single-chip microcomputer is that sheet selected control signal output part is connected with the chip selection signal input of described WIFI chip circuit，15th foot of described single-chip microcomputer is that clock control signal outfan is connected with the clock signal input terminal of described WIFI chip circuit，16th foot of described single-chip microcomputer is that data sending terminal is connected with the data receiver of described WIFI chip circuit，17th foot of described single-chip microcomputer is that data receiver is connected with the data sending terminal of described WIFI chip circuit，21st foot of described single-chip microcomputer is that dormancy drives signal output part to be connected with the sleep signal input of described WIFI chip circuit，22nd foot of described single-chip microcomputer is that interrupt signal input is connected with the interrupt signal outfan of described WIFI chip circuit.
Described power conversion circuit is made up of full bridge inverter and the first field effect transistor drive circuit and the second field effect transistor drive circuit, the road pulse-width signal that the microprocessor module described in input reception of the first described field effect transistor drive circuit provides, another road pulse-width signal that the microprocessor module described in input reception of the second described field effect transistor drive circuit provides, the high-voltage output end of the first described field effect transistor drive circuit and low-voltage output and the high-voltage output end of the second described field effect transistor drive circuit and low-voltage output are connected with described full bridge inverter respectively, described full bridge inverter is connected with described transmitting coil.
The first described field effect transistor drive circuit includes the first field effect transistor driving chip and the first resistance and the second resistance, the second described field effect transistor drive circuit includes the second field effect transistor driving chip and the 3rd resistance and the 4th resistance, and described full bridge inverter includes the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the first electric capacity, the second electric capacity and the 5th resistance；nullThe described input of the first field effect transistor driving chip is connected the road pulse-width signal that the single-chip microcomputer described in receiving provides with the 29th foot of described single-chip microcomputer，The high-voltage output end of the first described field effect transistor driving chip is connected by the grid of the first described resistance with the first described field effect transistor，The low-voltage output of the first described field effect transistor driving chip is connected by the grid of the second described resistance with the second described field effect transistor，The source electrode of the first described field effect transistor is connected with the source electrode of the second described field effect transistor，And both public connecting ends are connected with one end of described transmitting coil，The described input of the second field effect transistor driving chip is connected another road pulse-width signal that the single-chip microcomputer described in receiving provides with the 30th foot of described single-chip microcomputer，The high-voltage output end of the second described field effect transistor driving chip is connected with the grid of the 3rd described field effect transistor by the 3rd described resistance，The low-voltage output of the second described field effect transistor driving chip is connected with the grid of the 4th described field effect transistor by the 4th described resistance，The source electrode of the 3rd described field effect transistor is connected with the source electrode of the 4th described field effect transistor，And both public connecting ends are connected with the other end of described transmitting coil by the second described electric capacity，The drain electrode of the first described field effect transistor all accesses+5V voltage with the drain electrode of the 3rd described field effect transistor，And its public connecting end is by the first described capacity earth，The drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor，And both public connecting ends are by the 5th described resistance eutral grounding，The public connecting end that the second described electric capacity is connected with the other end of described transmitting coil is pressure feedback port，The public connecting end that the drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor is current feedback terminal，Described pressure feedback port and described current feedback terminal are connected with described signal pre-processing circuit respectively.
nullDescribed signal pre-processing circuit is by bandwidth-limited circuit、Voltage follower、First active low-pass filter、First voltage comparator、Second active low-pass filter and the second voltage comparator composition，The pressure feedback port of described power conversion circuit is connected with the input of described bandwidth-limited circuit，The outfan of described bandwidth-limited circuit is connected with the input of described voltage follower，The outfan of described voltage follower is connected with the input of the first described active low-pass filter，The outfan of the first described active low-pass filter is connected with the input of the first described voltage comparator，The outfan of the first described voltage comparator is connected with described microprocessor module，The current feedback terminal of described power conversion circuit is connected with the input of the second described active low-pass filter，The outfan of the second described active low-pass filter is connected with the input of the second described voltage comparator，The second described active low-pass filter is connected with described microprocessor module，The outfan of the second described voltage comparator is connected with described microprocessor module.
nullDescribed bandwidth-limited circuit includes the 27th resistance、28th resistance、29th resistance、30th resistance、31st resistance、First diode、25th electric capacity and the 26th electric capacity，Described voltage follower includes the 27th electric capacity、28th electric capacity、32nd resistance and the first operational amplifier，The first described active low-pass filter includes the 33rd resistance、34th resistance、35th resistance、36th resistance、29th electric capacity、30th electric capacity and the second operational amplifier，The first described voltage comparator includes the 37th resistance、38th resistance、39th resistance、31st electric capacity and the 3rd operational amplifier，The second described active low-pass filter includes the 40th resistance、41st resistance、42nd resistance、43rd resistance、44th resistance、45th resistance、46th resistance、32nd electric capacity、33rd electric capacity、34th electric capacity、Four-operational amplifier and the 5th operational amplifier，The second described voltage comparator includes the 49th resistance、50th resistance、35th electric capacity、36th electric capacity、37th electric capacity and the 6th operational amplifier；
nullDescribed one end of the 27th resistance is connected with the pressure feedback port of described power conversion circuit，The other end of the 27th described resistance is connected with the positive pole of the first described diode，The negative pole of the first described diode respectively with one end of the 26th described electric capacity、One end of the 25th described electric capacity and one end of the 28th described resistance connect，The other end of the 26th described electric capacity respectively with one end of the 29th described resistance、One end of the 30th described resistance and one end of the 31st described resistance connect，Another termination+3.3V voltage of the 29th described resistance，The other end of the 28th described resistance、The other end of the 25th described electric capacity and the equal ground connection of the other end of the 30th described resistance，The other end of the 31st described resistance is by the 27th described capacity earth，The other end of the 31st described resistance is connected with the in-phase input end of the first described operational amplifier，The inverting input of the first described operational amplifier is connected with the outfan of the first described operational amplifier，The positive power source terminal of the first described operational amplifier accesses+3.3V voltage and by the 28th described capacity earth，The negative power end ground connection of the first described operational amplifier，The outfan of the first described operational amplifier by the 32nd described resistance and the 33rd described resistance respectively one end with the in-phase input end of the second described operational amplifier and the 30th described electric capacity be connected，The public connecting end that the 32nd described resistance is connected with the 33rd described resistance is by the 29th described capacity earth，And be connected with the other end of the 30th described electric capacity and the outfan of the second described operational amplifier respectively by the 36th described resistance，The inverting input of the second described operational amplifier is connected with one end of the 35th described resistance and one end of the 34th described resistance respectively，Another termination+3.3V voltage of the 35th described resistance，The other end ground connection of the 34th described resistance，The outfan of the second described operational amplifier is connected with the in-phase input end of the 3rd described operational amplifier and one end of the 39th described resistance respectively by the 37th described resistance，The outfan of the second described operational amplifier is connected with the inverting input of the 3rd described operational amplifier and one end of the 31st described electric capacity respectively by the 38th described resistance，The other end ground connection of the 31st described electric capacity，The other end of the 39th described resistance is connected with the outfan of the 3rd described operational amplifier，The described outfan of the 3rd operational amplifier is connected with the 12nd foot of described single-chip microcomputer；
nullDescribed one end of the 40th resistance is connected with the current feedback terminal of described power conversion circuit，The other end of the 40th described resistance is by the 32nd described capacity earth，The described other end of the 40th resistance is connected with the in-phase input end of described four-operational amplifier，The inverting input of described four-operational amplifier is by the 41st described resistance eutral grounding，And be connected with the outfan of described four-operational amplifier by the 42nd described resistance，The outfan of described four-operational amplifier is connected with the 11st foot of described single-chip microcomputer by the 43rd described resistance，The public connecting end that the outfan of described four-operational amplifier is connected with the 42nd described resistance is connected with the in-phase input end of the 5th described operational amplifier and one end of the 33rd described electric capacity respectively by the 44th described resistance and the 45th described resistance，The public connecting end that the 44th described resistance is connected with the 45th described resistance is by the 34th described capacity earth，And be connected with the other end of the 33rd described electric capacity and the outfan of the 5th described operational amplifier respectively by the 46th described resistance，The reverse inter-input-ing ending grounding of the 5th described operational amplifier，The outfan of the 5th described operational amplifier is connected with the in-phase input end of the 6th described operational amplifier by the 49th described resistance，The in-phase input end of the 6th described operational amplifier is by the 35th described capacity earth，The outfan of the 5th described operational amplifier is connected with the inverting input of the 6th described operational amplifier by the 50th described resistance，The inverting input of the 6th described operational amplifier is by the 37th described capacity earth，The positive power source terminal of the 6th described operational amplifier accesses+3.3V voltage and by the 36th described capacity earth，The negative power end ground connection of the 6th described operational amplifier，The described outfan of the 6th operational amplifier is connected with the 13rd foot of described single-chip microcomputer.
Described WIFI chip circuit is made up of the peripheral circuit of the WIFI chip that model is CC3100 and described WIFI chip, 2nd foot of described WIFI chip is sleep signal input, 8th foot of described WIFI chip is chip selection signal input, 5th foot of described WIFI chip is clock signal input terminal, 6th foot of described WIFI chip is data sending terminal, the 7th of described WIFI chip is data receiver, and the 15th of described WIFI chip is interrupt signal outfan.
This wireless charger also includes that supply module, described supply module provide supply voltage to described microprocessor module, described WIFI chip circuit, described signal pre-processing circuit and described power conversion circuit.
Compared with prior art, it is an advantage of the current invention that:
1) pass through on microprocessor module, connect one to be used for and the WIFI chip circuit of microprocessor module synchronous communication transmission data, make this wireless charger can carry out data interaction and communication by WIFI interface and the outside communication equipment (including being electrically charged equipment) with WIFI function.
2) outside can be utilized to have the charged state of this wireless charger of communication equipment monitoring of WIFI function, the communication equipment that outside can also be utilized to have WIFI function controls the charging process of this wireless charger or arranges various charging instruction, and realizes these functions and only need to install existing corresponding software on the communication equipment that outside has WIFI function.
Accompanying drawing explanation
Fig. 1 is the composition structural representation of the wireless charger of the present invention；
Fig. 2 is the circuit theory diagrams of the microprocessor module in the wireless charger of the present invention；
Fig. 3 is the circuit theory diagrams of the WIFI chip circuit in the wireless charger of the present invention；
Fig. 4 a is the composition structural representation of the power conversion circuit in the wireless charger of the present invention；
Fig. 4 b is the circuit theory diagrams of the power conversion circuit in the wireless charger of the present invention；
Fig. 5 a is the composition structural representation of the signal pre-processing circuit in the wireless charger of the present invention；
Fig. 5 b is the circuit theory diagrams of the signal pre-processing circuit in the wireless charger of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
nullA kind of wireless charger with WIFI function that the present invention proposes，As shown in Figure 1，It includes microprocessor module 1 and supply module 6，Microprocessor module 1 connects to be had for by the power conversion circuit 2 of converting direct-current power into alternating-current power、For modulated signal being demodulated to the signal pre-processing circuit 3 of demodulated signal and being used for and the WIFI chip circuit 4 of microprocessor module 1 synchronous communication transmission data，Power conversion circuit 2 connects to be had and is electrically charged on equipment on the wireless charging receptor installed the transmitting coil FS_L that the receiving coil being connected matches，WIFI chip circuit 4 is connected by 2.4GHZ wave filter 5 the antenna TX realizing data communication for the communication equipment with outside with WIFI function，WIFI chip circuit 4 has chip selection signal input、Clock signal input terminal、Data receiver、Data sending terminal、Sleep signal input and interrupt signal outfan，Microprocessor module 1 has the most corresponding chip selection signal input with WIFI chip circuit、Clock signal input terminal、Data receiver、Data sending terminal、The sheet selected control signal output part that sleep signal input and interrupt signal outfan connect、Clock control signal outfan、Data sending terminal、Data receiver、Dormancy drives signal output part and interrupt signal input；When microprocessor module 1 is in Low-power-consumptiodormancy dormancy pattern, if microprocessor module 1 detects its task requests interiorly or exteriorly, then microprocessor module 1 will wake up up from Low-power-consumptiodormancy dormancy pattern, after microprocessor module 1 wakes up up from Low-power-consumptiodormancy dormancy pattern, after microprocessor module 1 drives signal output part output drive signal to the sleep signal input of WIFI chip circuit 4 by its dormancy, WIFI chip circuit 4 is started working；WIFI chip circuit 4 exports the interrupt signal of WIFI chip circuit 4 generation to the interrupt signal input of microprocessor module 1 by its interrupt signal outfan, and microprocessor module 1 by its sheet selected control signal output part output low level signal to the chip selection signal input of WIFI chip circuit 4 after, WIFI chip circuit 4 and microprocessor module 1 start synchronous communication and transmit data；Supply module 6 provides+3.3V voltage to microprocessor module 1, WIFI chip circuit 4 and signal pre-processing circuit 3, and supply module 6 provides+5V voltage to power conversion circuit 2.
nullDuring the work of this wireless charger，Microprocessor module 1 provides two-way pulse-width signal to power conversion circuit 2，Power conversion circuit 2 produces one after receiving two-way pulse-width signal、The high frequency ac signal of 200 KHz，The high frequency ac signal that power conversion circuit 2 produces is coupled in wireless charging receptor by transmitting coil FS_L and receiving coil，The modulated signal that it is modulated obtaining including charging status information after receiving high frequency ac signal by wireless charging receptor，Wireless charging receptor includes the modulated signal of charging status information to signal pre-processing circuit 3 by receiving coil and transmitting coil FS_L feedback，Signal pre-processing circuit 3 is demodulated to include the demodulated signal of charging status information after receiving the modulated signal including charging status information，Signal pre-processing circuit 3 provides and includes the demodulated signal of charging status information to microprocessor module 1，Microprocessor module 1 carries out processing acquisition and includes the data of charging status information the demodulated signal including charging status information，Microprocessor module 1 can adjust the dutycycle of two-way pulse-width signal or frequency according to the data one including charging status information thus automatically adjust output voltage or the size of electric current，It two can do overcurrent protection and foreign bodies detection，Its three can by its data sending terminal transmit its obtain the data including charging status information to the data receiver of WIFI chip circuit 4，WIFI chip circuit 4 is transmitted by antenna TX and includes the data of charging status information and have the communication equipment of WIFI function to outside，Outside has after the communication equipment of WIFI function sends instructions to microprocessor module 1 by WIFI chip circuit 4，Wireless charging process is controlled by microprocessor module 1，Realize the detection of charging effect.
At this, outside has the communication equipment of WIFI function and includes the equipment that is electrically charged and other communication equipments, such as mobile phone etc., the mobile phone application software of a special control charge function is customized in mobile phone, arranging charge rate or charged level by this application software, during use, application program of mobile phone sends an instruction, and this instruction is wirelessly transmitted to WIFI chip circuit 4, then WIFI chip circuit 4 is sent to microprocessor module 1 again, and microprocessor module 1 controls wireless charging according to instruction.
nullIn the present embodiment，As shown in Figure 2，Microprocessor module 1 is made up of the peripheral circuit of the single-chip microcomputer U1 that model is STM32F103C8T6 and single-chip microcomputer U1，The demodulated signal including charging status information is carried out processing obtaining and includes the data of charging status information and realized by prior art by single-chip microcomputer U1，29th foot of single-chip microcomputer U1 and the 30th foot are connected with power conversion circuit 2 respectively，11st foot of single-chip microcomputer U1、12nd foot and the 13rd foot are connected with signal pre-processing circuit 3 respectively，14th foot of single-chip microcomputer U1 is that sheet selected control signal output part is connected with the chip selection signal input of WIFI chip circuit 4，15th foot of single-chip microcomputer U1 is that clock control signal outfan is connected with the clock signal input terminal of WIFI chip circuit 4，16th foot of single-chip microcomputer U1 is that data sending terminal is connected with the data receiver of WIFI chip circuit 4，17th foot of single-chip microcomputer U1 is that data receiver is connected with the data sending terminal of WIFI chip circuit 4，21st foot of single-chip microcomputer U1 is that dormancy drives signal output part to be connected with the sleep signal input of WIFI chip circuit 4，22nd foot of single-chip microcomputer U1 is that interrupt signal input is connected with the interrupt signal outfan of WIFI chip circuit 4；The peripheral circuit of single-chip microcomputer U1 also determines that in the case of the model of single-chip microcomputer U1 determines.As shown in Figure 3, WIFI chip circuit 4 is made up of the peripheral circuit of the WIFI chip U2 that model is CC3100 and WIFI chip U2,2nd foot of WIFI chip U2 is sleep signal input, 8th foot of WIFI chip U2 is chip selection signal input, 5th foot of WIFI chip U2 is clock signal input terminal, 6th foot of WIFI chip U2 is data sending terminal, and the 7th of WIFI chip U2 is data receiver, and the 15th of WIFI chip U2 is interrupt signal outfan；The peripheral circuit of WIFI chip U2 also determines that in the case of the model of WIFI chip U2 determines.Above-mentioned, when specific design, model is that the single-chip microcomputer U1 of STM32F103C8T6 can replace with the single-chip microcomputer of 8 of existing any maturation or 16 or 32；Model is that the WIFI chip U2 of CC3100 can replace with the WIFI chip of existing any maturation.
In the present embodiment, as shown in figures 4 a and 4b, power conversion circuit 2 is made up of full bridge inverter 23 and the first field effect transistor drive circuit 21 and the second field effect transistor drive circuit 22, the input of the first field effect transistor drive circuit 21 receives the road pulse-width signal that microprocessor module 1 provides, the input of the second field effect transistor drive circuit 22 receives another road pulse-width signal that microprocessor module 1 provides, the high-voltage output end of the first field effect transistor drive circuit 21 and low-voltage output and the high-voltage output end of the second field effect transistor drive circuit 22 and low-voltage output are connected with full bridge inverter 23 respectively, full bridge inverter 23 is connected with transmitting coil FS_L.First field effect transistor drive circuit 21 includes the first field effect transistor driving chip U3 and the first resistance R1 and the second resistance R2, second field effect transistor drive circuit 22 includes the second field effect transistor driving chip U4 and the 3rd resistance R3 and the 4th resistance R4, and full bridge inverter 23 includes the first field effect transistor Q1, the second field effect transistor Q2, the 3rd field effect transistor Q3, the 4th field effect transistor Q4, the first electric capacity C1, the second electric capacity C2 and the 5th resistance R5；nullThe input of the first field effect transistor driving chip U1 is connected the road pulse-width signal receiving single-chip microcomputer U1 offer with the 29th foot of single-chip microcomputer U1，The high-voltage output end of the first field effect transistor driving chip U3 is connected by the grid of the first resistance R1 and the first field effect transistor Q1，The low-voltage output of the first field effect transistor driving chip U3 is connected by the grid of the second resistance R2 and the second field effect transistor Q2，The source electrode of the first field effect transistor Q1 and the source electrode of the second field effect transistor Q2 connect，And both public connecting ends are connected with one end of transmitting coil FS_L，The input of the second field effect transistor driving chip U4 is connected another road pulse-width signal receiving single-chip microcomputer U1 offer with the 30th foot of single-chip microcomputer U1，The high-voltage output end of the second field effect transistor driving chip U4 is connected by the grid of the 3rd resistance R3 and the 3rd field effect transistor Q3，The low-voltage output of the second field effect transistor driving chip U4 is connected by the grid of the 4th resistance R4 and the 4th field effect transistor Q4，The source electrode of the 3rd field effect transistor Q3 and the source electrode of the 4th field effect transistor Q4 connect，And both public connecting ends are connected by the other end of the second electric capacity C2 and transmitting coil FS_L，The drain electrode of the first field effect transistor Q1 all accesses+5V voltage with the drain electrode of the 3rd field effect transistor Q3，And its public connecting end is by the first electric capacity C1 ground connection，The drain electrode of the second field effect transistor Q2 is connected with the drain electrode of the 4th field effect transistor Q4，And both public connecting ends are by the 5th resistance R5 ground connection，The public connecting end that the other end of the second electric capacity C2 and transmitting coil FS_L is connected is pressure feedback port V_BACK，The public connecting end that the drain electrode of the second field effect transistor Q2 is connected with the drain electrode of the 4th field effect transistor Q4 is current feedback terminal I_BACK，Pressure feedback port V_BACK and current feedback terminal I_BACK is connected with signal pre-processing circuit 3 respectively.At this, first field effect transistor driving chip U3 and the second field effect transistor driving chip U4 all uses existing field effect transistor driving chip, owing to the first field effect transistor drive circuit 21 and the second field effect transistor drive circuit 22 all have employed field effect transistor driving chip, thus while the drive circuit that cost slightly above discrete component is built, but drive effect to be much better than the drive circuit that discrete component is built, and efficiency of transmission can be improved well.
nullIn the present embodiment，Signal pre-processing circuit 3 is first responsible for demodulating the modulated signal of about 100KHz，Obtain the demodulated signal of about 2KHz，Secondly current signal filter and amplification sampling obtained sends into single-chip microcomputer U1，Single-chip microcomputer U1 is transferred to carry out overcurrent protection，Also have the electric current obtained by single-chip microcomputer U1 to be exactly multiplied with voltage to obtain power and send into single-chip microcomputer U1 and do foreign bodies detection，As shown in Figure 5 a，Signal pre-processing circuit 3 is by bandwidth-limited circuit 31、Voltage follower 32、First active low-pass filter 33、First voltage comparator 34、Second active low-pass filter 35 and the second voltage comparator 36 form，The pressure feedback port V_BACK of power conversion circuit 2 is connected with the input of bandwidth-limited circuit 31，The outfan of bandwidth-limited circuit 31 is connected with the input of voltage follower 32，The outfan of voltage follower 32 and the input of the first active low-pass filter 33 connect，The outfan of the first active low-pass filter 33 and the input of the first voltage comparator 34 connect，The outfan of the first voltage comparator 34 is connected with microprocessor module 1，The current feedback terminal I_BACK of power conversion circuit 2 and the input of the second active low-pass filter 35 connect，The outfan of the second active low-pass filter 35 and the input of the second voltage comparator 36 connect，Second active low-pass filter 35 is connected with microprocessor module 1，The outfan of the second voltage comparator 36 is connected with microprocessor module 1.
nullIn the present embodiment，As shown in Figure 5 b，Bandwidth-limited circuit 31 includes the 27th resistance R27、28th resistance R28、29th resistance R29、30th resistance R30、31st resistance R31、First diode D1、25th electric capacity C25 and the 26th electric capacity C26，Voltage follower 32 includes the 27th electric capacity C27、28th electric capacity C28、32nd resistance R32 and the first operational amplifier Y1，First active low-pass filter 33 includes the 33rd resistance R33、34th resistance R34、35th resistance R35、36th resistance R36、29th electric capacity C29、30th electric capacity C30 and the second operational amplifier Y2，First voltage comparator 34 includes the 37th resistance R37、38th resistance R38、39th resistance R39、31st electric capacity C31 and the 3rd operational amplifier Y3，Second active low-pass filter 35 includes the 40th resistance R40、41st resistance R41、42nd resistance R42、43rd resistance R43、44th resistance R44、45th resistance R45、46th resistance R46、32nd electric capacity C32、33rd electric capacity C33、34th electric capacity C34、Four-operational amplifier Y4 and the 5th operational amplifier Y5，Second voltage comparator 36 includes the 49th resistance R49、50th resistance R50、35th electric capacity C35、36th electric capacity C36、37th electric capacity C37 and the 6th operational amplifier Y6；nullOne end of 27th resistance R27 is connected with the pressure feedback port of power conversion circuit，The other end of the 27th resistance R27 and the positive pole of the first diode D1 connect，The negative pole of the first diode D1 respectively with one end of the 26th electric capacity C26、One end of 25th electric capacity C25 and one end of the 28th resistance R28 connect，The other end of the 26th electric capacity C26 respectively with one end of the 29th resistance R29、One end of 30th resistance R30 and one end of the 31st resistance R31 connect，Another termination+3.3V voltage of 29th resistance R29，The other end of the 28th resistance R28、The other end of the 25th electric capacity C25 and the equal ground connection of the other end of the 30th resistance R30，The other end of the 31st resistance R31 passes through the 27th electric capacity C27 ground connection，The other end of the 31st resistance R31 and the in-phase input end of the first operational amplifier Y1 connect，The inverting input of the first operational amplifier Y1 and the outfan of the first operational amplifier Y1 connect，The positive power source terminal of the first operational amplifier Y1 accesses+3.3V voltage and by the 28th electric capacity C28 ground connection，The negative power end ground connection of the first operational amplifier Y1，The outfan of the first operational amplifier Y1 is connected with the in-phase input end of the second operational amplifier Y2 and one end of the 30th electric capacity C30 respectively by the 32nd resistance R32 and the 33rd resistance R33，The public connecting end that 32nd resistance R32 and the 33rd resistance R33 connects is by the 29th electric capacity C29 ground connection，And be connected with the other end of the 30th electric capacity C30 and the outfan of the second operational amplifier Y2 respectively by the 36th resistance R36，The inverting input of the second operational amplifier Y2 is connected with one end of the 35th resistance R35 and one end of the 34th resistance R34 respectively，Another termination+3.3V voltage of 35th resistance R35，The other end ground connection of the 34th resistance R34，The outfan of the second operational amplifier Y2 is connected with the in-phase input end of the 3rd operational amplifier Y3 and one end of the 39th resistance R39 respectively by the 37th resistance R37，The outfan of the second operational amplifier Y2 is connected with the inverting input of the 3rd operational amplifier Y3 and one end of the 31st electric capacity C31 respectively by the 38th resistance R38，The other end ground connection of the 31st electric capacity C31，The other end of the 39th resistance R39 and the outfan of the 3rd operational amplifier Y3 connect，The outfan of the 3rd operational amplifier Y3 is connected with the 12nd foot of single-chip microcomputer U1；nullOne end of 40th resistance R40 is connected with the current feedback terminal of power conversion circuit，The other end of the 40th resistance R40 passes through the 32nd electric capacity C32 ground connection，The other end of the 40th resistance R40 and the in-phase input end of four-operational amplifier Y4 connect，The inverting input of four-operational amplifier Y4 passes through the 41st resistance R41 ground connection，And connected by the outfan of the 42nd resistance R42 and four-operational amplifier Y4，The outfan of four-operational amplifier Y4 is connected by the 11st foot of the 43rd resistance R43 and single-chip microcomputer U1，The public connecting end that the outfan of four-operational amplifier Y4 and the 42nd resistance R42 connect is connected with the in-phase input end of the 5th operational amplifier Y5 and one end of the 33rd electric capacity C33 respectively by the 44th resistance R44 and the 45th resistance R45，The public connecting end that 44th resistance R44 and the 45th resistance R45 connects is by the 34th electric capacity C34 ground connection，And be connected with the other end of the 33rd electric capacity C33 and the outfan of the 5th operational amplifier Y5 respectively by the 46th resistance R46，The reverse inter-input-ing ending grounding of the 5th operational amplifier Y5，The outfan of the 5th operational amplifier Y5 is connected by the in-phase input end of the 49th resistance R49 and the 6th operational amplifier Y6，The in-phase input end of the 6th operational amplifier Y6 passes through the 35th electric capacity C35 ground connection，The outfan of the 5th operational amplifier Y5 is connected by the inverting input of the 50th resistance R50 and the 6th operational amplifier Y6，The inverting input of the 6th operational amplifier Y6 passes through the 37th electric capacity C37 ground connection，The positive power source terminal of the 6th operational amplifier Y6 accesses+3.3V voltage and by the 36th electric capacity C36 ground connection，The negative power end ground connection of the 6th operational amplifier Y6，The outfan of the 6th operational amplifier Y6 is connected with the 13rd foot of single-chip microcomputer U1.Here, the operational amplifier that the first operational amplifier Y1, the second operational amplifier Y2, the 3rd operational amplifier Y3, four-operational amplifier Y4, the 5th operational amplifier Y5 and the 6th operational amplifier Y6 all use existing model to be LM324.
Above-mentioned, bandwidth-limited circuit 31, voltage follower the 32, first active low-pass filter the 33, second active low-pass filter 35 can also use the circuit of other maturations existing.
Claims (8)
1. there is a wireless charger for WIFI function, including microprocessor module, it is characterised in that described micro-place
Reason device module connects the WIFI chip circuit having for described microprocessor module synchronous communication transmission data, described
WIFI chip circuit by wave filter connect have for the communication equipment with outside with WIFI function realize data lead to
News antenna, described WIFI chip circuit have chip selection signal input, clock signal input terminal, data receiver,
Data sending terminal, sleep signal input and interrupt signal outfan, described microprocessor module has sheet selected control system letter
Number outfan, clock control signal outfan, data sending terminal, data receiver, dormancy drive signal output part and in
Break signal input；After described microprocessor module wakes up up from Low-power-consumptiodormancy dormancy pattern, described microprocessor mould
Block drives signal output part output drive signal to the sleep signal input of described WIFI chip circuit by its dormancy
After, described WIFI chip circuit is started working；Described WIFI chip circuit is defeated by its interrupt signal outfan
Go out interrupt signal that described WIFI chip circuit produces to the interrupt signal input of described microprocessor module, and
Described microprocessor module gives described WIFI chip electricity by its sheet selected control signal output part output low level signal
After the chip selection signal input on road, described WIFI chip circuit and described microprocessor module start synchronous communication and pass
Transmission of data；
Described microprocessor module is also associated with for by the power conversion circuit of converting direct-current power into alternating-current power be used for
Modulated signal is demodulated to the signal pre-processing circuit of demodulated signal, and described power conversion circuit connects to have and sets with being electrically charged
The transmitting coil that the receiving coil connected on the wireless charging receptor of standby upper installation matches；Described microprocessor module carries
Receive two-way pulsewidth modulation letter to described power conversion circuit, described power conversion circuit for two-way pulse-width signal
Producing high frequency ac signal after number, the high frequency ac signal that described power conversion circuit produces is by described transmitting coil
Being coupled in described wireless charging receptor with described receiving coil, described wireless charging receptor receives high frequency
The modulated signal being modulated obtaining including charging status information to it after AC signal, described wireless charging receptor
Fed back by described receiving coil and described transmitting coil and include the modulated signal of charging status information to described
Signal pre-processing circuit, described signal pre-processing circuit demodulates after receiving the modulated signal including charging status information
Becoming to include the demodulated signal of charging status information, described signal pre-processing circuit provides and includes charging status information
Demodulated signal gives described microprocessor module, and described microprocessor module transmits what it obtained by its data sending terminal
Include the data data receiver to described WIFI chip circuit of charging status information, described WIFI chip
Circuit includes, by described antenna transmission, the communication that the data of charging status information have WIFI function to outside and sets
Standby, outside has the communication equipment of WIFI function and sends instructions to described micro-place by described WIFI chip circuit
After reason device module, described microprocessor module control wireless charging process.
A kind of wireless charger with WIFI function the most according to claim 1, it is characterised in that described is micro-
Processor module is made up of the peripheral circuit of the single-chip microcomputer that model is STM32F103C8T6 and described single-chip microcomputer, described
The 29th foot of single-chip microcomputer and the 30th foot be connected with described power conversion circuit respectively, the 11st of described single-chip microcomputer
Foot, the 12nd foot and the 13rd foot are connected with described signal pre-processing circuit respectively, and the 14th foot of described single-chip microcomputer is
Sheet selected control signal output part is connected with the chip selection signal input of described WIFI chip circuit, described single-chip microcomputer
15th foot is that clock control signal outfan is connected with the clock signal input terminal of described WIFI chip circuit, described
16th foot of single-chip microcomputer is that data sending terminal is connected with the data receiver of described WIFI chip circuit, described monolithic
17th foot of machine is that data receiver is connected with the data sending terminal of described WIFI chip circuit, described single-chip microcomputer
21st foot is that dormancy drives signal output part to be connected with the sleep signal input of described WIFI chip circuit, described
22nd foot of single-chip microcomputer is that interrupt signal input is connected with the interrupt signal outfan of described WIFI chip circuit.
A kind of wireless charger with WIFI function the most according to claim 2, it is characterised in that described merit
Rate translation circuit is made up of full bridge inverter and the first field effect transistor drive circuit and the second field effect transistor drive circuit, institute
The road pulsewidth modulation letter that the microprocessor module described in input reception of the first field effect transistor drive circuit stated provides
Number, another road pulsewidth that the microprocessor module described in input reception of the second described field effect transistor drive circuit provides
Modulated signal, the high-voltage output end of the first described field effect transistor drive circuit and low-voltage output and described second effect
High-voltage output end and the low-voltage output of answering tube drive circuit are connected with described full bridge inverter respectively, described full-bridge
Inverter circuit is connected with described transmitting coil.
A kind of wireless charger with WIFI function the most according to claim 3, it is characterised in that described
One field effect transistor drive circuit includes the first field effect transistor driving chip and the first resistance and the second resistance, described second
Effect tube drive circuit includes the second field effect transistor driving chip and the 3rd resistance and the 4th resistance, described full-bridge inverting electricity
Road include the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the first electric capacity, second
Electric capacity and the 5th resistance；The input of the first described field effect transistor driving chip connects with the 29th foot of described single-chip microcomputer
The road pulse-width signal that single-chip microcomputer described in reception provides, the high pressure of the first described field effect transistor driving chip is defeated
Going out end to be connected by the grid of the first described resistance with the first described field effect transistor, the first described field effect transistor drives
The low-voltage output of chip is connected by the grid of the second described resistance with the second described field effect transistor, described first
The source electrode of field effect transistor is connected with the source electrode of the second described field effect transistor, and both public connecting ends and described transmitting
One end of coil connects, and the input of the second described field effect transistor driving chip connects with the 30th foot of described single-chip microcomputer
Another road pulse-width signal that single-chip microcomputer described in reception provides, the high pressure of the second described field effect transistor driving chip
Outfan is connected with the grid of the 3rd described field effect transistor by the 3rd described resistance, and the second described field effect transistor is driven
The low-voltage output of dynamic chip is connected with the grid of the 4th described field effect transistor by the 4th described resistance, and described the
The source electrode of three field effect transistor is connected with the source electrode of the 4th described field effect transistor, and both public connecting ends are by described
Second electric capacity is connected with the other end of described transmitting coil, the drain electrode of the first described field effect transistor and described the 3rd
The drain electrode of effect pipe all accesses+5V voltage, and its public connecting end is by the first described capacity earth, described second
The drain electrode of field effect transistor is connected with the drain electrode of the 4th described field effect transistor, and both public connecting ends are by described the
Five resistance eutral groundings, the public connecting end that the second described electric capacity is connected with the other end of described transmitting coil is Voltage Feedback
End, the public connecting end that the drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor is electric current
Feedback end, described pressure feedback port and described current feedback terminal are connected with described signal pre-processing circuit respectively.
A kind of wireless charger with WIFI function the most according to claim 4, it is characterised in that described letter
Number pretreatment circuit by bandwidth-limited circuit, voltage follower, the first active low-pass filter, the first voltage comparator,
Second active low-pass filter and the second voltage comparator composition, the pressure feedback port of described power conversion circuit is with described
Bandwidth-limited circuit input connect, the outfan of described bandwidth-limited circuit is defeated with described voltage follower
Entering end to connect, the outfan of described voltage follower is connected with the input of the first described active low-pass filter, institute
The outfan of the first active low-pass filter stated is connected with the input of the first described voltage comparator, described first
The outfan of voltage comparator is connected with described microprocessor module, the current feedback terminal of described power conversion circuit with
The input of the second described active low-pass filter connects, and the outfan of the second described active low-pass filter is with described
The input of the second voltage comparator connect, the second described active low-pass filter and described microprocessor module are even
Connecing, the outfan of the second described voltage comparator is connected with described microprocessor module.
A kind of wireless charger with WIFI function the most according to claim 5, it is characterised in that described band
Bandpass filter circuit include the 27th resistance, the 28th resistance, the 29th resistance, the 30th resistance, the 31st
Resistance, the first diode, the 25th electric capacity and the 26th electric capacity, described voltage follower includes the 27th electricity
Appearance, the 28th electric capacity, the 32nd resistance and the first operational amplifier, the first described active low-pass filter includes
33rd resistance, the 34th resistance, the 35th resistance, the 36th resistance, the 29th electric capacity, the 30th
Electric capacity and the second operational amplifier, the first described voltage comparator include the 37th resistance, the 38th resistance,
39 resistance, the 31st electric capacity and the 3rd operational amplifier, the second described active low-pass filter includes the 40th
Resistance, the 41st resistance, the 42nd resistance, the 43rd resistance, the 44th resistance, the 45th resistance,
46th resistance, the 32nd electric capacity, the 33rd electric capacity, the 34th electric capacity, four-operational amplifier and the 5th
Operational amplifier, the second described voltage comparator include the 49th resistance, the 50th resistance, the 35th electric capacity,
36th electric capacity, the 37th electric capacity and the 6th operational amplifier；
Described one end of the 27th resistance is connected with the pressure feedback port of described power conversion circuit, described second
The other end of 17 resistance is connected with the positive pole of the first described diode, the negative pole of the first described diode respectively with institute
One end of the one end of the 26th electric capacity stated, one end of the 25th described electric capacity and the 28th described resistance is even
Connect, the other end of the 26th described electric capacity respectively with described one end of the 29th resistance, the described the 30th electricity
One end of resistance and one end of the 31st described resistance connect, another termination+3.3V electricity of the 29th described resistance
Pressure, the other end of the 28th described resistance, the other end of the 25th described electric capacity and the 30th described resistance
The equal ground connection of the other end, the other end of the 31st described resistance is by described the 27th capacity earth, described
The other end of the 31st resistance is connected with the in-phase input end of the first described operational amplifier, and the first described computing is put
The big inverting input of device is connected with the outfan of the first described operational amplifier, and the first described operational amplifier is just
Power end accesses+3.3V voltage and by the 28th described capacity earth, the negative electricity of the first described operational amplifier
Source ground connection, the outfan of the first described operational amplifier is by described the 32nd resistance and the described the 33rd
Resistance one end with the in-phase input end of the second described operational amplifier and the 30th described electric capacity respectively is connected, described
The public connecting end that is connected with the 33rd described resistance of the 32nd resistance connect by the 29th described electric capacity
Ground, and the other end and the second described computing with the 30th described electric capacity is put respectively by the 36th described resistance
The outfan of big device connects, the inverting input of the second described operational amplifier respectively with the 35th described resistance
One end of one end and the 34th described resistance connects, another termination+3.3V voltage of the 35th described resistance,
The other end ground connection of the 34th described resistance, the outfan of the second described operational amplifier is by the described the 30th
Seven resistance are connected with the in-phase input end of the 3rd described operational amplifier and one end of the 39th described resistance respectively,
The outfan of the second described operational amplifier by described the 38th resistance respectively with the 3rd described operation amplifier
The inverting input of device and one end of the 31st described electric capacity connect, another termination of the 31st described electric capacity
Ground, the other end of the 39th described resistance is connected with the outfan of the 3rd described operational amplifier, described the 3rd
The outfan of operational amplifier is connected with the 12nd foot of described single-chip microcomputer；
Described one end of the 40th resistance is connected with the current feedback terminal of described power conversion circuit, described the 40th
The other end of resistance is by the 32nd described capacity earth, the other end and the described the 4th of the 40th described resistance
The in-phase input end of operational amplifier connects, and the inverting input of described four-operational amplifier is by the described the 40th
One resistance eutral grounding, and be connected with the outfan of described four-operational amplifier by the 42nd described resistance, described
The outfan of four-operational amplifier be connected with the 11st foot of described single-chip microcomputer by the 43rd described resistance,
The public connecting end that the outfan of described four-operational amplifier is connected with the 42nd described resistance is by described
44th resistance and the 45th described resistance respectively with in-phase input end and the institute of the 5th described operational amplifier
The one end of the 33rd electric capacity stated connects, and the 44th described resistance is public with what the 45th described resistance was connected
Connect end and pass through the 34th described capacity earth, and by the 46th described resistance respectively with the described the 30th
The outfan of the other end of three electric capacity and the 5th described operational amplifier connects, the 5th described operational amplifier anti-phase
Input end grounding, the outfan of the 5th described operational amplifier is by the 49th described resistance and the described the 6th fortune
The in-phase input end calculating amplifier connects, and the in-phase input end of the 6th described operational amplifier is by the described the 35th
Capacity earth, the outfan of the 5th described operational amplifier is put with the 6th described computing by the 50th described resistance
The inverting input of big device connects, and the inverting input of the 6th described operational amplifier is by the 37th described electric capacity
Ground connection, the positive power source terminal of the 6th described operational amplifier is accessed+3.3V voltage and is connect by the 36th described electric capacity
Ground, the negative power end ground connection of the 6th described operational amplifier, the outfan of the 6th described operational amplifier is with described
13rd foot of single-chip microcomputer connects.
A kind of wireless charger with WIFI function the most according to any one of claim 1 to 6, its feature
It is that described WIFI chip circuit is by the WIFI chip that model is CC3100 and the peripheral electricity of described WIFI chip
Road forms, and the 2nd foot of described WIFI chip is sleep signal input, and the 8th foot of described WIFI chip is
Chip selection signal input, the 5th foot of described WIFI chip is clock signal input terminal, described WIFI chip
6th foot is data sending terminal, and the 7th of described WIFI chip is data receiver, the of described WIFI chip
15 is interrupt signal outfan.
A kind of wireless charger with WIFI function the most according to claim 6, it is characterised in that this wireless charging
Electrical equipment also includes supply module, and described supply module provides supply voltage to described microprocessor module, described
WIFI chip circuit, described signal pre-processing circuit and described power conversion circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410740566.8A CN104505922B (en) | 2014-12-08 | 2014-12-08 | A kind of wireless charger with WIFI function |
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| CN201410740566.8A CN104505922B (en) | 2014-12-08 | 2014-12-08 | A kind of wireless charger with WIFI function |
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| CN104840204B (en) * | 2015-04-10 | 2018-01-19 | 京东方科技集团股份有限公司 | A kind of fatigue driving monitoring method and equipment |
| CN105550061A (en) * | 2015-12-02 | 2016-05-04 | 杭州禾声科技有限公司 | Wireless charging and data storing device |
| CN106487424B (en) * | 2015-12-28 | 2017-07-18 | 无锡华润矽科微电子有限公司 | The demodulator circuit of fsk signal in wireless charging device |
| CN106487425B (en) * | 2015-12-28 | 2017-12-22 | 无锡华润矽科微电子有限公司 | The demodulation method of fsk signal in wireless charging device |
| CN109617196A (en) * | 2018-12-06 | 2019-04-12 | 深圳市纵联网络科技有限公司 | A kind of wireless charger with WIFI hot spot |
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| ATE382223T1 (en) * | 2003-08-26 | 2008-01-15 | Nxp Bv | DATA SEPARATION AND FRAGMENTATION IN A WIRELESS NETWORK TO IMPROVE VIDEO PERFORMANCE |
| CN201868931U (en) * | 2010-12-06 | 2011-06-15 | 景嘉有限公司 | Wireless charger with Bluetooth and Wi-Fi (wireless fidelity) connecting technology |
| CN203896025U (en) * | 2014-06-17 | 2014-10-22 | 邓崇敬 | Multifunctional portable charger |
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