CN204271694U - A kind of wireless charger with WIFI function - Google Patents
A kind of wireless charger with WIFI function Download PDFInfo
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- CN204271694U CN204271694U CN201420764048.5U CN201420764048U CN204271694U CN 204271694 U CN204271694 U CN 204271694U CN 201420764048 U CN201420764048 U CN 201420764048U CN 204271694 U CN204271694 U CN 204271694U
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Abstract
The utility model discloses a kind of wireless charger with WIFI function, it comprises microprocessor module, microprocessor module is connected with for transmitting the WIFI chip circuit of data with microprocessor module synchronous communication, WIFI chip circuit realizes the antenna of data communication by the filter communication equipment be connected with for having a WIFI function with outside, WIFI chip circuit has chip selection signal input, clock signal input terminal, data receiver, data sending terminal, sleep signal input and interrupt signal output, microprocessor module has sheet selected control signal output part, clock control signal output, data sending terminal, data receiver, dormancy drive singal output and interrupt signal input, advantage is that the communication equipment (comprising by charging device) making this wireless charger have WIFI function by WIFI interface and outside carries out data interaction and communication by connecting one for transmit the WIFI chip circuit of data with microprocessor module synchronous communication on microprocessor module.
Description
Technical field
The utility model relates to a kind of wireless charging technology, and especially relate to a kind of wireless charger with WIFI function, it can realize data communication by WIFI.
Background technology
Current wireless charging technology is with induction the most popular with magnetic resonance type.The feature of induction wireless charging technology is that charging distance is short, the diameter of induction coil is smaller, operating frequency is lower, and now main is main industry standard with QI standard; The feature of magnetic resonance type wireless charging technology is that charging distance is relatively long, induction coil diameter is larger, operating frequency is higher, and now main is main industry standard with A4WP standard.
But, no matter be based on the wireless charger of QI standard or the wireless charger based on A4WP standard, all have problems, namely charging device cannot carry out data communication with external communication device (comprising by charging device), the control in charging process and monitoring cannot be carried out, the use widely that have impact on wireless charger larger like this.
Summary of the invention
Technical problem to be solved in the utility model is to provide a kind of wireless charger with WIFI function, it can make charging device and comprise between the external communication device by charging device to carry out data interaction and communication, realizes the monitor and forecast to wireless charging process.
The utility model solves the problems of the technologies described above adopted technical scheme: a kind of wireless charger with WIFI function, comprise microprocessor module and supply module, it is characterized in that described microprocessor module be connected with for described microprocessor module synchronous communication transmit data WIFI chip circuit and for by the power conversion circuit of converting direct-current power into alternating-current power and the signal pre-processing circuit being used for modulation signal to be demodulated to restituted signal, described supply module provides supply voltage to described microprocessor module, described WIFI chip circuit, described signal pre-processing circuit and described power conversion circuit, described WIFI chip circuit realizes the antenna of data communication by the filter communication equipment be connected with for having a WIFI function with outside, described WIFI chip circuit has chip selection signal input, clock signal input terminal, data receiver, data sending terminal, sleep signal input and interrupt signal output, and described microprocessor module has sheet selected control signal output part, clock control signal output, data sending terminal, data receiver, dormancy drive singal output and interrupt signal input, after described microprocessor module wakes up from Low-power-consumptiodormancy dormancy pattern, after described microprocessor module gives the sleep signal input of described WIFI chip circuit by its dormancy drive singal output output drive signal, described WIFI chip circuit is started working, the interrupt signal that WIFI chip circuit described in described WIFI chip circuit is exported by its interrupt signal output produces is to the interrupt signal input of described microprocessor module, and described microprocessor module passes through its sheet selected control signal output part output low level signal to after the chip selection signal input of described WIFI chip circuit, described WIFI chip circuit and described microprocessor module start synchronous communication and transmit data, described power conversion circuit is connected with and the transmitting coil matched by the receiving coil that wireless charging receiver that charging device is installed is connected, described microprocessor module provides two-way pulse-width signal to described power conversion circuit, described power conversion circuit produces high frequency ac signal after receiving two-way pulse-width signal, the high frequency ac signal that described power conversion circuit produces is coupled in described wireless charging receiver by described transmitting coil and described receiving coil, after described wireless charging receiver receives high frequency ac signal, the modulation signal obtaining including charging status information is modulated to it, described wireless charging receiver contains the modulation signal of charging status information to described signal pre-processing circuit by described receiving coil and described transmitting coil feedback packet, described signal pre-processing circuit is demodulated to the restituted signal including charging status information after receiving the modulation signal including charging status information, described signal pre-processing circuit providing package contains the restituted signal of charging status information to described microprocessor module, described microprocessor module transmits its data including charging status information obtained to the data receiver of described WIFI chip circuit by its data sending terminal, the data that described WIFI chip circuit includes charging status information by described antenna transmission have the communication equipment of WIFI function to outside, the communication equipment that outside has WIFI function sends instruction to after described microprocessor module by described WIFI chip circuit, wireless charging process is controlled by described microprocessor module.
Described power conversion circuit is made up of full bridge inverter and the first field effect transistor drive circuit and the second field effect transistor drive circuit, the road pulse-width signal that microprocessor module described in the input of the first described field effect transistor drive circuit receives provides, another road pulse-width signal that microprocessor module described in the input of the second described field effect transistor drive circuit receives provides, the high-voltage output end of the first described field effect transistor drive circuit is connected with described full bridge inverter with low-voltage output respectively with the high-voltage output end of low-voltage output and the second described field effect transistor drive circuit, described full bridge inverter is connected with described transmitting coil.
The first described field effect transistor drive circuit comprises the first field effect transistor driving chip and the first resistance and the second resistance, the second described field effect transistor drive circuit comprises the second field effect transistor driving chip and the 3rd resistance and the 4th resistance, and described full bridge inverter comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the first electric capacity, the second electric capacity and the 5th resistance; the input of the first described field effect transistor driving chip is connected the road pulse-width signal that the microprocessor module described in receiving provides with described microprocessor module, the high-voltage output end of the first described field effect transistor driving chip is connected by the grid of the first described resistance with the first described field effect transistor, the low-voltage output of the first described field effect transistor driving chip is connected by the grid of the second described resistance with the second described field effect transistor, the source electrode of the first described field effect transistor is connected with the source electrode of the second described field effect transistor, and both public connecting ends are connected with one end of described transmitting coil, the input of the second described field effect transistor driving chip is connected another road pulse-width signal that the microprocessor module described in receiving provides with described microprocessor module, the high-voltage output end of the second described field effect transistor driving chip is connected by the grid of the 3rd described resistance with the 3rd described field effect transistor, the low-voltage output of the second described field effect transistor driving chip is connected by the grid of the 4th described resistance with the 4th described field effect transistor, the source electrode of the 3rd described field effect transistor is connected with the source electrode of the 4th described field effect transistor, and both public connecting ends are connected with the other end of described transmitting coil by the second described electric capacity, the drain electrode of the first described field effect transistor and the drain electrode of the 3rd described field effect transistor all access+5V voltage, and its public connecting end is by the first described capacity earth, the drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor, and both public connecting ends are by the 5th described grounding through resistance, the public connecting end that the second described electric capacity is connected with the other end of described transmitting coil is pressure feedback port, the public connecting end that the drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor is current feedback terminal, described pressure feedback port is connected with described signal pre-processing circuit respectively with described current feedback terminal.
Described signal pre-processing circuit is by bandwidth-limited circuit, voltage follower, first active low-pass filter, first voltage comparator, second active low-pass filter and the second voltage comparator composition, the pressure feedback port of described power conversion circuit is connected with the input of described bandwidth-limited circuit, the output of described bandwidth-limited circuit is connected with the input of described voltage follower, the output of described voltage follower is connected with the input of the first described active low-pass filter, the output of the first described active low-pass filter is connected with the input of the first described voltage comparator, the output of the first described voltage comparator is connected with described microprocessor module, the current feedback terminal of described power conversion circuit is connected with the input of the second described active low-pass filter, the output of the second described active low-pass filter is connected with the input of the second described voltage comparator, the second described active low-pass filter is connected with described microprocessor module, the output of the second described voltage comparator is connected with described microprocessor module.
Described bandwidth-limited circuit comprises the 27 resistance, 28 resistance, 29 resistance, 30 resistance, 31 resistance, first diode, 25 electric capacity and the 26 electric capacity, described voltage follower comprises the 27 electric capacity, 28 electric capacity, 32 resistance and the first operational amplifier, the first described active low-pass filter comprises the 33 resistance, 34 resistance, 35 resistance, 36 resistance, 29 electric capacity, 30 electric capacity and the second operational amplifier, the first described voltage comparator comprises the 37 resistance, 38 resistance, 39 resistance, 31 electric capacity and the 3rd operational amplifier, the second described active low-pass filter comprises the 40 resistance, 41 resistance, 42 resistance, 43 resistance, 44 resistance, 45 resistance, 46 resistance, 32 electric capacity, 33 electric capacity, 34 electric capacity, four-operational amplifier and the 5th operational amplifier, the second described voltage comparator comprises the 49 resistance, 50 resistance, 35 electric capacity, 36 electric capacity, 37 electric capacity and the 6th operational amplifier,
One end of the 27 described resistance is connected with the pressure feedback port of described power conversion circuit, the other end of the 27 described resistance is connected with the positive pole of the first described diode, the negative pole of the first described diode respectively with one end of the 26 described electric capacity, one end of the 25 described electric capacity is connected with one end of the 28 described resistance, the other end of the 26 described electric capacity respectively with one end of the 29 described resistance, one end of the 30 described resistance is connected with one end of the 31 described resistance, another termination+3.3V voltage of the 29 described resistance, the other end of the 28 described resistance, the other end of the 25 described electric capacity and the equal ground connection of the other end of the 30 described resistance, the other end of the 31 described resistance is by the 27 described capacity earth, the other end of the 31 described resistance is connected with the in-phase input end of the first described operational amplifier, the inverting input of the first described operational amplifier is connected with the output of the first described operational amplifier, the positive power source terminal of the first described operational amplifier accesses+3.3V voltage and passes through the 28 described capacity earth, the negative power end ground connection of the first described operational amplifier, the output of the first described operational amplifier is connected with the in-phase input end of the second described operational amplifier and one end of the 30 described electric capacity with the 33 described resistance respectively by the 32 described resistance, the public connecting end that the 32 described resistance is connected with the 33 described resistance is by the 29 described capacity earth, and be connected with the other end of the 30 described electric capacity and the output of the second described operational amplifier respectively by the 36 described resistance, the inverting input of the second described operational amplifier is connected with one end of the 35 described resistance and one end of the 34 described resistance respectively, another termination+3.3V voltage of the 35 described resistance, the other end ground connection of the 34 described resistance, the output of the second described operational amplifier is connected with the in-phase input end of the 3rd described operational amplifier and one end of the 39 described resistance respectively by the 37 described resistance, the output of the second described operational amplifier is connected with the inverting input of the 3rd described operational amplifier and one end of the 31 described electric capacity respectively by the 38 described resistance, the other end ground connection of the 31 described electric capacity, the other end of the 39 described resistance is connected with the output of the 3rd described operational amplifier, the output of the 3rd described operational amplifier is connected with described microprocessor module,
One end of the 40 described resistance is connected with the current feedback terminal of described power conversion circuit, the other end of the 40 described resistance is by the 32 described capacity earth, the other end of the 40 described resistance is connected with the in-phase input end of described four-operational amplifier, the inverting input of described four-operational amplifier is by the 41 described grounding through resistance, and be connected with the output of described four-operational amplifier by the 42 described resistance, the output of described four-operational amplifier is connected with described microprocessor module by the 43 described resistance, the public connecting end that the output of described four-operational amplifier is connected with the 42 described resistance is connected with the in-phase input end of the 5th described operational amplifier and one end of the 33 described electric capacity respectively by the 44 described resistance and the 45 described resistance, the public connecting end that the 44 described resistance is connected with the 45 described resistance is by the 34 described capacity earth, and be connected with the other end of the 33 described electric capacity and the output of the 5th described operational amplifier respectively by the 46 described resistance, the reverse inter-input-ing ending grounding of the 5th described operational amplifier, the output of the 5th described operational amplifier is connected with the in-phase input end of the 6th described operational amplifier by the 49 described resistance, the in-phase input end of the 6th described operational amplifier is by the 35 described capacity earth, the output of the 5th described operational amplifier is connected with the inverting input of the 6th described operational amplifier by the 50 described resistance, the inverting input of the 6th described operational amplifier is by the 37 described capacity earth, the positive power source terminal of the 6th described operational amplifier accesses+3.3V voltage and passes through the 36 described capacity earth, the negative power end ground connection of the 6th described operational amplifier, the output of the 6th described operational amplifier is connected with described microprocessor module.
Described microprocessor module is that the single-chip microcomputer of STM32F103C8T6 and the peripheral circuit of described single-chip microcomputer form by model.
29th pin of described single-chip microcomputer is connected with the input of the first field effect transistor driving chip in described power conversion circuit, 30th pin of described single-chip microcomputer is connected with the input of the second field effect transistor driving chip in described power conversion circuit, 11st pin of described single-chip microcomputer is connected with the other end of the 43 resistance in described signal pre-processing circuit, 12nd pin of described single-chip microcomputer is connected with the output of the 3rd operational amplifier in described signal pre-processing circuit, 13rd pin of described single-chip microcomputer is connected with the output of the 6th operational amplifier in described signal pre-processing circuit, 14th pin of described single-chip microcomputer is that sheet selected control signal output part is connected with the chip selection signal input of described WIFI chip circuit, 15th pin of described single-chip microcomputer is that clock control signal output is connected with the clock signal input terminal of described WIFI chip circuit, 16th pin of described single-chip microcomputer is that data sending terminal is connected with the data receiver of described WIFI chip circuit, 17th pin of described single-chip microcomputer is that data receiver is connected with the data sending terminal of described WIFI chip circuit, 21st pin of described single-chip microcomputer is that dormancy drive singal output is connected with the sleep signal input of described WIFI chip circuit, 22nd pin of described single-chip microcomputer is that interrupt signal input is connected with the interrupt signal output of described WIFI chip circuit.
Described WIFI chip circuit is that the WIFI chip of CC3100 and the peripheral circuit of described WIFI chip form by model, 2nd pin of described WIFI chip is sleep signal input, 8th pin of described WIFI chip is chip selection signal input, 5th pin of described WIFI chip is clock signal input terminal, 6th pin of described WIFI chip is data sending terminal, the 7th of described WIFI chip is data receiver, and the 15th of described WIFI chip is interrupt signal output.
compared with prior art, the utility model has the advantage of:
1) by connecting one for transmit the WIFI chip circuit of data with microprocessor module synchronous communication on microprocessor module, the communication equipment (comprising by charging device) making this wireless charger have WIFI function by WIFI interface and outside carries out data interaction and communication.
2) outside can be utilized to have the charged state of this wireless charger of communication equipment monitoring of WIFI function, the communication equipment that also outside can be utilized to have WIFI function controls the charging process of this wireless charger or arranges various charging instruction, and realizes these functions and only need install existing corresponding software on the communication equipment that outside has WIFI function.
Accompanying drawing explanation
Fig. 1 is the composition structural representation of wireless charger of the present utility model;
Fig. 2 is the circuit theory diagrams of the microprocessor module in wireless charger of the present utility model;
Fig. 3 is the circuit theory diagrams of the WIFI chip circuit in wireless charger of the present utility model;
Fig. 4 a is the composition structural representation of the power conversion circuit in wireless charger of the present utility model;
Fig. 4 b is the circuit theory diagrams of the power conversion circuit in wireless charger of the present utility model;
Fig. 5 a is the composition structural representation of the signal pre-processing circuit in wireless charger of the present utility model;
Fig. 5 b is the circuit theory diagrams of the signal pre-processing circuit in wireless charger of the present utility model.
Embodiment
Below in conjunction with accompanying drawing embodiment, the utility model is described in further detail.
A kind of wireless charger with WIFI function that the utility model proposes, as shown in Figure 1, it comprises microprocessor module 1 and supply module 6, and microprocessor module 1 is connected with for the power conversion circuit 2 by converting direct-current power into alternating-current power, for modulation signal being demodulated to the signal pre-processing circuit 3 of restituted signal and being used for transmitting with microprocessor module 1 synchronous communication the WIFI chip circuit 4 of data, power conversion circuit 2 is connected with and the transmitting coil FS_L matched by the receiving coil that wireless charging receiver that charging device is installed is connected, WIFI chip circuit 4 realizes the antenna TX of data communication by 2.4GHZ filter 5 communication equipment be connected with for having a WIFI function with outside, and WIFI chip circuit 4 has chip selection signal input, clock signal input terminal, data receiver, data sending terminal, sleep signal input and interrupt signal output, microprocessor module 1 has the chip selection signal input of correspondence and WIFI chip circuit respectively, clock signal input terminal, data receiver, data sending terminal, the sheet selected control signal output part that sleep signal input is connected with interrupt signal output, clock control signal output, data sending terminal, data receiver, dormancy drive singal output and interrupt signal input, when microprocessor module 1 is in Low-power-consumptiodormancy dormancy pattern, if when microprocessor module 1 detects its inner or outside task requests, then microprocessor module 1 will wake up from Low-power-consumptiodormancy dormancy pattern, after microprocessor module 1 wakes up from Low-power-consumptiodormancy dormancy pattern, microprocessor module 1 is by its dormancy drive singal output output drive signal to after the sleep signal input of WIFI chip circuit 4, and WIFI chip circuit 4 is started working, WIFI chip circuit 4 exports the interrupt signal of WIFI chip circuit 4 generation to the interrupt signal input of microprocessor module 1 by its interrupt signal output, and microprocessor module 1 passes through its sheet selected control signal output part output low level signal to after the chip selection signal input of WIFI chip circuit 4, WIFI chip circuit 4 and microprocessor module 1 start synchronous communication and transmit data, supply module 6 provides+3.3V voltage to microprocessor module 1, WIFI chip circuit 4 and signal pre-processing circuit 3, and supply module 6 provides+5V voltage to power conversion circuit 2.
During the work of this wireless charger, microprocessor module 1 provides two-way pulse-width signal to power conversion circuit 2, power conversion circuit 2 produces one after receiving two-way pulse-width signal, the high frequency ac signal of 200 KHz, the high frequency ac signal that power conversion circuit 2 produces is coupled in wireless charging receiver by transmitting coil FS_L and receiving coil, after wireless charging receiver receives high frequency ac signal, the modulation signal obtaining including charging status information is modulated to it, wireless charging receiver contains the modulation signal of charging status information to signal pre-processing circuit 3 by receiving coil and transmitting coil FS_L feedback packet, signal pre-processing circuit 3 is demodulated to the restituted signal including charging status information after receiving the modulation signal including charging status information, signal pre-processing circuit 3 providing package contains the restituted signal of charging status information to microprocessor module 1, microprocessor module 1 carries out the restituted signal including charging status information processing the data obtaining and include charging status information, microprocessor module 1 can adjust the duty ratio of two-way pulse-width signal or frequency according to the data one including charging status information thus the size of adjustment output voltage or electric current automatically, it two can do overcurrent protection and foreign bodies detection, its three can by its data sending terminal transmit its obtain the data including charging status information to the data receiver of WIFI chip circuit 4, WIFI chip circuit 4 transmits by antenna TX the data including charging status information to have WIFI function communication equipment to outside, the communication equipment that outside has WIFI function sends instruction to after microprocessor module 1 by WIFI chip circuit 4, wireless charging process is controlled by microprocessor module 1, realize the detection of charging effect.
At this, the communication equipment that outside has WIFI function comprises by charging device and other communication equipments, as mobile phone etc., the mobile phone application software that one controls charge function is specially customized in mobile phone, arrange charge rate or charged level by this application software, during use, application program of mobile phone sends an instruction, and this instruction is wirelessly transmitted to WIFI chip circuit 4, then WIFI chip circuit 4 is sent to microprocessor module 1 again, and microprocessor module 1 controls wireless charging according to instruction.
In the present embodiment, as shown in Figure 2, microprocessor module 1 is that the single-chip microcomputer U1 of STM32F103C8T6 and the peripheral circuit of single-chip microcomputer U1 form by model, single-chip microcomputer U1 carries out processing acquisition to the restituted signal including charging status information and includes the data of charging status information by existing techniques in realizing, 29th pin of single-chip microcomputer U1 is connected with power conversion circuit 2 respectively with the 30th pin, 11st pin of single-chip microcomputer U1, 12nd pin is connected with signal pre-processing circuit 3 respectively with the 13rd pin, 14th pin of single-chip microcomputer U1 is that sheet selected control signal output part is connected with the chip selection signal input of WIFI chip circuit 4, 15th pin of single-chip microcomputer U1 is that clock control signal output is connected with the clock signal input terminal of WIFI chip circuit 4, 16th pin of single-chip microcomputer U1 is that data sending terminal is connected with the data receiver of WIFI chip circuit 4, 17th pin of single-chip microcomputer U1 is that data receiver is connected with the data sending terminal of WIFI chip circuit 4, 21st pin of single-chip microcomputer U1 is that dormancy drive singal output is connected with the sleep signal input of WIFI chip circuit 4, 22nd pin of single-chip microcomputer U1 is that interrupt signal input is connected with the interrupt signal output of WIFI chip circuit 4, the peripheral circuit of single-chip microcomputer U1 is also determined when the model of single-chip microcomputer U1 is determined.As shown in Figure 3, WIFI chip circuit 4 is that the WIFI chip U2 of CC3100 and the peripheral circuit of WIFI chip U2 form by model, 2nd pin of WIFI chip U2 is sleep signal input, 8th pin of WIFI chip U2 is chip selection signal input, 5th pin of WIFI chip U2 is clock signal input terminal, 6th pin of WIFI chip U2 is data sending terminal, and the 7th of WIFI chip U2 is data receiver, and the 15th of WIFI chip U2 is interrupt signal output; The peripheral circuit of WIFI chip U2 is also determined when the model of WIFI chip U2 is determined.Above-mentioned, when specific design, model is that the single-chip microcomputer U1 of STM32F103C8T6 can replace with the single-chip microcomputer of 8 of existing any maturation or 16 or 32; Model is that the WIFI chip U2 of CC3100 can replace with the WIFI chip of existing any maturation.
In the present embodiment, as shown in figures 4 a and 4b, power conversion circuit 2 is made up of full bridge inverter 23 and the first field effect transistor drive circuit 21 and the second field effect transistor drive circuit 22, the input of the first field effect transistor drive circuit 21 receives the road pulse-width signal that microprocessor module 1 provides, the input of the second field effect transistor drive circuit 22 receives another road pulse-width signal that microprocessor module 1 provides, the high-voltage output end of the first field effect transistor drive circuit 21 is connected with full bridge inverter 23 with low-voltage output respectively with the high-voltage output end of low-voltage output and the second field effect transistor drive circuit 22, full bridge inverter 23 is connected with transmitting coil FS_L.First field effect transistor drive circuit 21 comprises the first field effect transistor driving chip U3 and the first resistance R1 and the second resistance R2, second field effect transistor drive circuit 22 comprises the second field effect transistor driving chip U4 and the 3rd resistance R3 and the 4th resistance R4, and full bridge inverter 23 comprises the first field effect transistor Q1, the second field effect transistor Q2, the 3rd field effect transistor Q3, the 4th field effect transistor Q4, the first electric capacity C1, the second electric capacity C2 and the 5th resistance R5; the input of the first field effect transistor driving chip U1 is connected the road pulse-width signal receiving single-chip microcomputer U1 and provide with the 29th pin of single-chip microcomputer U1, the high-voltage output end of the first field effect transistor driving chip U3 is connected with the grid of the first field effect transistor Q1 by the first resistance R1, the low-voltage output of the first field effect transistor driving chip U3 is connected with the grid of the second field effect transistor Q2 by the second resistance R2, the source electrode of the first field effect transistor Q1 is connected with the source electrode of the second field effect transistor Q2, and both public connecting ends are connected with one end of transmitting coil FS_L, the input of the second field effect transistor driving chip U4 is connected another road pulse-width signal receiving single-chip microcomputer U1 and provide with the 30th pin of single-chip microcomputer U1, the high-voltage output end of the second field effect transistor driving chip U4 is connected with the grid of the 3rd field effect transistor Q3 by the 3rd resistance R3, the low-voltage output of the second field effect transistor driving chip U4 is connected with the grid of the 4th field effect transistor Q4 by the 4th resistance R4, the source electrode of the 3rd field effect transistor Q3 is connected with the source electrode of the 4th field effect transistor Q4, and both public connecting ends are connected with the other end of transmitting coil FS_L by the second electric capacity C2, the drain electrode of the first field effect transistor Q1 and the drain electrode of the 3rd field effect transistor Q3 all access+5V voltage, and its public connecting end is by the first electric capacity C1 ground connection, the drain electrode of the second field effect transistor Q2 is connected with the drain electrode of the 4th field effect transistor Q4, and both public connecting ends are by the 5th resistance R5 ground connection, the public connecting end that second electric capacity C2 is connected with the other end of transmitting coil FS_L is pressure feedback port V_BACK, the public connecting end that the drain electrode of the second field effect transistor Q2 is connected with the drain electrode of the 4th field effect transistor Q4 is current feedback terminal I_BACK, pressure feedback port V_BACK is connected with signal pre-processing circuit 3 respectively with current feedback terminal I_BACK.At this, first field effect transistor driving chip U3 and the second field effect transistor driving chip U4 all adopts existing field effect transistor driving chip, because the first field effect transistor drive circuit 21 and the second field effect transistor drive circuit 22 all have employed field effect transistor driving chip, although the therefore drive circuit built a little more than discrete component of cost, but driving effect is much better than the drive circuit that discrete component is built, and can improve efficiency of transmission well.
In the present embodiment, first signal pre-processing circuit 3 is responsible for the modulation signal demodulation of about 100KHz, obtain the restituted signal of about 2KHz, secondly the current signal filter and amplification obtained sampling sends into single-chip microcomputer U1, single-chip microcomputer U1 is transferred to carry out overcurrent protection, the electric current obtained by single-chip microcomputer U1 exactly is in addition multiplied with voltage and obtains power and send into single-chip microcomputer U1 and do foreign bodies detection, as shown in Figure 5 a, signal pre-processing circuit 3 is by bandwidth-limited circuit 31, voltage follower 32, first active low-pass filter 33, first voltage comparator 34, second active low-pass filter 35 and the second voltage comparator 36 form, the pressure feedback port V_BACK of power conversion circuit 2 is connected with the input of bandwidth-limited circuit 31, the output of bandwidth-limited circuit 31 is connected with the input of voltage follower 32, the output of voltage follower 32 is connected with the input of the first active low-pass filter 33, the output of the first active low-pass filter 33 is connected with the input of the first voltage comparator 34, the output of the first voltage comparator 34 is connected with microprocessor module 1, the current feedback terminal I_BACK of power conversion circuit 2 is connected with the input of the second active low-pass filter 35, the output of the second active low-pass filter 35 is connected with the input of the second voltage comparator 36, second active low-pass filter 35 is connected with microprocessor module 1, the output of the second voltage comparator 36 is connected with microprocessor module 1.
In the present embodiment, as shown in Figure 5 b, bandwidth-limited circuit 31 comprises the 27 resistance R27, 28 resistance R28, 29 resistance R29, 30 resistance R30, 31 resistance R31, first diode D1, 25 electric capacity C25 and the 26 electric capacity C26, voltage follower 32 comprises the 27 electric capacity C27, 28 electric capacity C28, 32 resistance R32 and the first operational amplifier Y1, the first active low-pass filter 33 comprises the 33 resistance R33, 34 resistance R34, 35 resistance R35, 36 resistance R36, 29 electric capacity C29, 30 electric capacity C30 and the second operational amplifier Y2, the first voltage comparator 34 comprises the 37 resistance R37, 38 resistance R38, 39 resistance R39, 31 electric capacity C31 and the 3rd operational amplifier Y3, the second active low-pass filter 35 comprises the 40 resistance R40, 41 resistance R41, 42 resistance R42, 43 resistance R43, 44 resistance R44, 45 resistance R45, 46 resistance R46, 32 electric capacity C32, 33 electric capacity C33, 34 electric capacity C34, four-operational amplifier Y4 and the 5th operational amplifier Y5, the second voltage comparator 36 comprises the 49 resistance R49, 50 resistance R50, 35 electric capacity C35, 36 electric capacity C36, 37 electric capacity C37 and the 6th operational amplifier Y6, one end of 27 resistance R27 is connected with the pressure feedback port of power conversion circuit, the other end of the 27 resistance R27 is connected with the positive pole of the first diode D1, the negative pole of the first diode D1 respectively with one end of the 26 electric capacity C26, one end of 25 electric capacity C25 is connected with one end of the 28 resistance R28, the other end of the 26 electric capacity C26 respectively with one end of the 29 resistance R29, one end of 30 resistance R30 is connected with one end of the 31 resistance R31, another termination+3.3V voltage of the 29 resistance R29, the other end of the 28 resistance R28, the other end of the 25 electric capacity C25 and the equal ground connection of the other end of the 30 resistance R30, the other end of the 31 resistance R31 is by the 27 electric capacity C27 ground connection, the other end of the 31 resistance R31 is connected with the in-phase input end of the first operational amplifier Y1, the inverting input of the first operational amplifier Y1 is connected with the output of the first operational amplifier Y1, the positive power source terminal of the first operational amplifier Y1 accesses+3.3V voltage and passes through the 28 electric capacity C28 ground connection, the negative power end ground connection of the first operational amplifier Y1, the output of the first operational amplifier Y1 is connected with the in-phase input end of the second operational amplifier Y2 and one end of the 30 electric capacity C30 with the 33 resistance R33 respectively by the 32 resistance R32, the public connecting end that 32 resistance R32 is connected with the 33 resistance R33 is by the 29 electric capacity C29 ground connection, and be connected with the other end of the 30 electric capacity C30 and the output of the second operational amplifier Y2 respectively by the 36 resistance R36, the inverting input of the second operational amplifier Y2 is connected with one end of the 35 resistance R35 and one end of the 34 resistance R34 respectively, another termination+3.3V voltage of the 35 resistance R35, the other end ground connection of the 34 resistance R34, the output of the second operational amplifier Y2 is connected with the in-phase input end of the 3rd operational amplifier Y3 and one end of the 39 resistance R39 respectively by the 37 resistance R37, the output of the second operational amplifier Y2 is connected with the inverting input of the 3rd operational amplifier Y3 and one end of the 31 electric capacity C31 respectively by the 38 resistance R38, the other end ground connection of the 31 electric capacity C31, the other end of the 39 resistance R39 is connected with the output of the 3rd operational amplifier Y3, the output of the 3rd operational amplifier Y3 is connected with the 12nd pin of single-chip microcomputer U1, one end of 40 resistance R40 is connected with the current feedback terminal of power conversion circuit, the other end of the 40 resistance R40 is by the 32 electric capacity C32 ground connection, the other end of the 40 resistance R40 is connected with the in-phase input end of four-operational amplifier Y4, the inverting input of four-operational amplifier Y4 is by the 41 resistance R41 ground connection, and be connected with the output of four-operational amplifier Y4 by the 42 resistance R42, the output of four-operational amplifier Y4 is connected with the 11st pin of single-chip microcomputer U1 by the 43 resistance R43, the public connecting end that the output of four-operational amplifier Y4 is connected with the 42 resistance R42 is connected with the in-phase input end of the 5th operational amplifier Y5 and one end of the 33 electric capacity C33 respectively by the 44 resistance R44 and the 45 resistance R45, the public connecting end that 44 resistance R44 is connected with the 45 resistance R45 is by the 34 electric capacity C34 ground connection, and be connected with the other end of the 33 electric capacity C33 and the output of the 5th operational amplifier Y5 respectively by the 46 resistance R46, the reverse inter-input-ing ending grounding of the 5th operational amplifier Y5, the output of the 5th operational amplifier Y5 is connected with the in-phase input end of the 6th operational amplifier Y6 by the 49 resistance R49, the in-phase input end of the 6th operational amplifier Y6 is by the 35 electric capacity C35 ground connection, the output of the 5th operational amplifier Y5 is connected with the inverting input of the 6th operational amplifier Y6 by the 50 resistance R50, the inverting input of the 6th operational amplifier Y6 is by the 37 electric capacity C37 ground connection, the positive power source terminal of the 6th operational amplifier Y6 accesses+3.3V voltage and passes through the 36 electric capacity C36 ground connection, the negative power end ground connection of the 6th operational amplifier Y6, the output of the 6th operational amplifier Y6 is connected with the 13rd pin of single-chip microcomputer U1.At this, the first operational amplifier Y1, the second operational amplifier Y2, the 3rd operational amplifier Y3, four-operational amplifier Y4, the 5th operational amplifier Y5 and the 6th operational amplifier Y6 all adopt existing model to be the operational amplifier of LM324.
Above-mentioned, bandwidth-limited circuit 31, voltage follower 32, first active low-pass filter 33, second active low-pass filter 35 also can adopt the circuit of other maturations existing.
Claims (8)
1. one kind has the wireless charger of WIFI function, comprise microprocessor module and supply module, it is characterized in that described microprocessor module be connected with for described microprocessor module synchronous communication transmit data WIFI chip circuit and for by the power conversion circuit of converting direct-current power into alternating-current power and the signal pre-processing circuit being used for modulation signal to be demodulated to restituted signal, described supply module provides supply voltage to described microprocessor module, described WIFI chip circuit, described signal pre-processing circuit and described power conversion circuit; Described WIFI chip circuit realizes the antenna of data communication by the filter communication equipment be connected with for having a WIFI function with outside, described WIFI chip circuit has chip selection signal input, clock signal input terminal, data receiver, data sending terminal, sleep signal input and interrupt signal output, and described microprocessor module has sheet selected control signal output part, clock control signal output, data sending terminal, data receiver, dormancy drive singal output and interrupt signal input; After described microprocessor module wakes up from Low-power-consumptiodormancy dormancy pattern, after described microprocessor module gives the sleep signal input of described WIFI chip circuit by its dormancy drive singal output output drive signal, described WIFI chip circuit is started working; The interrupt signal that WIFI chip circuit described in described WIFI chip circuit is exported by its interrupt signal output produces is to the interrupt signal input of described microprocessor module, and described microprocessor module passes through its sheet selected control signal output part output low level signal to after the chip selection signal input of described WIFI chip circuit, described WIFI chip circuit and described microprocessor module start synchronous communication and transmit data; Described power conversion circuit is connected with and the transmitting coil matched by the receiving coil that wireless charging receiver that charging device is installed is connected; described microprocessor module provides two-way pulse-width signal to described power conversion circuit, described power conversion circuit produces high frequency ac signal after receiving two-way pulse-width signal, the high frequency ac signal that described power conversion circuit produces is coupled in described wireless charging receiver by described transmitting coil and described receiving coil, after described wireless charging receiver receives high frequency ac signal, the modulation signal obtaining including charging status information is modulated to it, described wireless charging receiver contains the modulation signal of charging status information to described signal pre-processing circuit by described receiving coil and described transmitting coil feedback packet, described signal pre-processing circuit is demodulated to the restituted signal including charging status information after receiving the modulation signal including charging status information, described signal pre-processing circuit providing package contains the restituted signal of charging status information to described microprocessor module, described microprocessor module transmits its data including charging status information obtained to the data receiver of described WIFI chip circuit by its data sending terminal, the data that described WIFI chip circuit includes charging status information by described antenna transmission have the communication equipment of WIFI function to outside, the communication equipment that outside has WIFI function sends instruction to after described microprocessor module by described WIFI chip circuit, wireless charging process is controlled by described microprocessor module.
2. a kind of wireless charger with WIFI function according to claim 1, it is characterized in that described power conversion circuit is made up of full bridge inverter and the first field effect transistor drive circuit and the second field effect transistor drive circuit, the road pulse-width signal that microprocessor module described in the input of the first described field effect transistor drive circuit receives provides, another road pulse-width signal that microprocessor module described in the input of the second described field effect transistor drive circuit receives provides, the high-voltage output end of the first described field effect transistor drive circuit is connected with described full bridge inverter with low-voltage output respectively with the high-voltage output end of low-voltage output and the second described field effect transistor drive circuit, described full bridge inverter is connected with described transmitting coil.
3. a kind of wireless charger with WIFI function according to claim 2, it is characterized in that the first described field effect transistor drive circuit comprises the first field effect transistor driving chip and the first resistance and the second resistance, the second described field effect transistor drive circuit comprises the second field effect transistor driving chip and the 3rd resistance and the 4th resistance, and described full bridge inverter comprises the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the first electric capacity, the second electric capacity and the 5th resistance; the input of the first described field effect transistor driving chip is connected the road pulse-width signal that the microprocessor module described in receiving provides with described microprocessor module, the high-voltage output end of the first described field effect transistor driving chip is connected by the grid of the first described resistance with the first described field effect transistor, the low-voltage output of the first described field effect transistor driving chip is connected by the grid of the second described resistance with the second described field effect transistor, the source electrode of the first described field effect transistor is connected with the source electrode of the second described field effect transistor, and both public connecting ends are connected with one end of described transmitting coil, the input of the second described field effect transistor driving chip is connected another road pulse-width signal that the microprocessor module described in receiving provides with described microprocessor module, the high-voltage output end of the second described field effect transistor driving chip is connected by the grid of the 3rd described resistance with the 3rd described field effect transistor, the low-voltage output of the second described field effect transistor driving chip is connected by the grid of the 4th described resistance with the 4th described field effect transistor, the source electrode of the 3rd described field effect transistor is connected with the source electrode of the 4th described field effect transistor, and both public connecting ends are connected with the other end of described transmitting coil by the second described electric capacity, the drain electrode of the first described field effect transistor and the drain electrode of the 3rd described field effect transistor all access+5V voltage, and its public connecting end is by the first described capacity earth, the drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor, and both public connecting ends are by the 5th described grounding through resistance, the public connecting end that the second described electric capacity is connected with the other end of described transmitting coil is pressure feedback port, the public connecting end that the drain electrode of the second described field effect transistor is connected with the drain electrode of the 4th described field effect transistor is current feedback terminal, described pressure feedback port is connected with described signal pre-processing circuit respectively with described current feedback terminal.
4. a kind of wireless charger with WIFI function according to claim 1, it is characterized in that described signal pre-processing circuit is by bandwidth-limited circuit, voltage follower, first active low-pass filter, first voltage comparator, second active low-pass filter and the second voltage comparator composition, the pressure feedback port of described power conversion circuit is connected with the input of described bandwidth-limited circuit, the output of described bandwidth-limited circuit is connected with the input of described voltage follower, the output of described voltage follower is connected with the input of the first described active low-pass filter, the output of the first described active low-pass filter is connected with the input of the first described voltage comparator, the output of the first described voltage comparator is connected with described microprocessor module, the current feedback terminal of described power conversion circuit is connected with the input of the second described active low-pass filter, the output of the second described active low-pass filter is connected with the input of the second described voltage comparator, the second described active low-pass filter is connected with described microprocessor module, the output of the second described voltage comparator is connected with described microprocessor module.
5. a kind of wireless charger with WIFI function according to claim 4, is characterized in that described bandwidth-limited circuit comprises the 27 resistance, 28 resistance, 29 resistance, 30 resistance, 31 resistance, first diode, 25 electric capacity and the 26 electric capacity, described voltage follower comprises the 27 electric capacity, 28 electric capacity, 32 resistance and the first operational amplifier, the first described active low-pass filter comprises the 33 resistance, 34 resistance, 35 resistance, 36 resistance, 29 electric capacity, 30 electric capacity and the second operational amplifier, the first described voltage comparator comprises the 37 resistance, 38 resistance, 39 resistance, 31 electric capacity and the 3rd operational amplifier, the second described active low-pass filter comprises the 40 resistance, 41 resistance, 42 resistance, 43 resistance, 44 resistance, 45 resistance, 46 resistance, 32 electric capacity, 33 electric capacity, 34 electric capacity, four-operational amplifier and the 5th operational amplifier, the second described voltage comparator comprises the 49 resistance, 50 resistance, 35 electric capacity, 36 electric capacity, 37 electric capacity and the 6th operational amplifier,
One end of the 27 described resistance is connected with the pressure feedback port of described power conversion circuit, the other end of the 27 described resistance is connected with the positive pole of the first described diode, the negative pole of the first described diode respectively with one end of the 26 described electric capacity, one end of the 25 described electric capacity is connected with one end of the 28 described resistance, the other end of the 26 described electric capacity respectively with one end of the 29 described resistance, one end of the 30 described resistance is connected with one end of the 31 described resistance, another termination+3.3V voltage of the 29 described resistance, the other end of the 28 described resistance, the other end of the 25 described electric capacity and the equal ground connection of the other end of the 30 described resistance, the other end of the 31 described resistance is by the 27 described capacity earth, the other end of the 31 described resistance is connected with the in-phase input end of the first described operational amplifier, the inverting input of the first described operational amplifier is connected with the output of the first described operational amplifier, the positive power source terminal of the first described operational amplifier accesses+3.3V voltage and passes through the 28 described capacity earth, the negative power end ground connection of the first described operational amplifier, the output of the first described operational amplifier is connected with the in-phase input end of the second described operational amplifier and one end of the 30 described electric capacity with the 33 described resistance respectively by the 32 described resistance, the public connecting end that the 32 described resistance is connected with the 33 described resistance is by the 29 described capacity earth, and be connected with the other end of the 30 described electric capacity and the output of the second described operational amplifier respectively by the 36 described resistance, the inverting input of the second described operational amplifier is connected with one end of the 35 described resistance and one end of the 34 described resistance respectively, another termination+3.3V voltage of the 35 described resistance, the other end ground connection of the 34 described resistance, the output of the second described operational amplifier is connected with the in-phase input end of the 3rd described operational amplifier and one end of the 39 described resistance respectively by the 37 described resistance, the output of the second described operational amplifier is connected with the inverting input of the 3rd described operational amplifier and one end of the 31 described electric capacity respectively by the 38 described resistance, the other end ground connection of the 31 described electric capacity, the other end of the 39 described resistance is connected with the output of the 3rd described operational amplifier, the output of the 3rd described operational amplifier is connected with described microprocessor module,
One end of the 40 described resistance is connected with the current feedback terminal of described power conversion circuit, the other end of the 40 described resistance is by the 32 described capacity earth, the other end of the 40 described resistance is connected with the in-phase input end of described four-operational amplifier, the inverting input of described four-operational amplifier is by the 41 described grounding through resistance, and be connected with the output of described four-operational amplifier by the 42 described resistance, the output of described four-operational amplifier is connected with described microprocessor module by the 43 described resistance, the public connecting end that the output of described four-operational amplifier is connected with the 42 described resistance is connected with the in-phase input end of the 5th described operational amplifier and one end of the 33 described electric capacity respectively by the 44 described resistance and the 45 described resistance, the public connecting end that the 44 described resistance is connected with the 45 described resistance is by the 34 described capacity earth, and be connected with the other end of the 33 described electric capacity and the output of the 5th described operational amplifier respectively by the 46 described resistance, the reverse inter-input-ing ending grounding of the 5th described operational amplifier, the output of the 5th described operational amplifier is connected with the in-phase input end of the 6th described operational amplifier by the 49 described resistance, the in-phase input end of the 6th described operational amplifier is by the 35 described capacity earth, the output of the 5th described operational amplifier is connected with the inverting input of the 6th described operational amplifier by the 50 described resistance, the inverting input of the 6th described operational amplifier is by the 37 described capacity earth, the positive power source terminal of the 6th described operational amplifier accesses+3.3V voltage and passes through the 36 described capacity earth, the negative power end ground connection of the 6th described operational amplifier, the output of the 6th described operational amplifier is connected with described microprocessor module.
6. a kind of wireless charger with WIFI function according to any one of claim 1 to 5, is characterized in that described microprocessor module is that the single-chip microcomputer of STM32F103C8T6 and the peripheral circuit of described single-chip microcomputer form by model.
7. a kind of wireless charger with WIFI function according to claim 6, it is characterized in that the 29th pin of described single-chip microcomputer is connected with the input of the first field effect transistor driving chip in described power conversion circuit, 30th pin of described single-chip microcomputer is connected with the input of the second field effect transistor driving chip in described power conversion circuit, 11st pin of described single-chip microcomputer is connected with the other end of the 43 resistance in described signal pre-processing circuit, 12nd pin of described single-chip microcomputer is connected with the output of the 3rd operational amplifier in described signal pre-processing circuit, 13rd pin of described single-chip microcomputer is connected with the output of the 6th operational amplifier in described signal pre-processing circuit, 14th pin of described single-chip microcomputer is that sheet selected control signal output part is connected with the chip selection signal input of described WIFI chip circuit, 15th pin of described single-chip microcomputer is that clock control signal output is connected with the clock signal input terminal of described WIFI chip circuit, 16th pin of described single-chip microcomputer is that data sending terminal is connected with the data receiver of described WIFI chip circuit, 17th pin of described single-chip microcomputer is that data receiver is connected with the data sending terminal of described WIFI chip circuit, 21st pin of described single-chip microcomputer is that dormancy drive singal output is connected with the sleep signal input of described WIFI chip circuit, 22nd pin of described single-chip microcomputer is that interrupt signal input is connected with the interrupt signal output of described WIFI chip circuit.
8. a kind of wireless charger with WIFI function according to claim 1, it is characterized in that described WIFI chip circuit is that the WIFI chip of CC3100 and the peripheral circuit of described WIFI chip form by model, 2nd pin of described WIFI chip is sleep signal input, 8th pin of described WIFI chip is chip selection signal input, 5th pin of described WIFI chip is clock signal input terminal, 6th pin of described WIFI chip is data sending terminal, the 7th of described WIFI chip is data receiver, the 15th of described WIFI chip is interrupt signal output.
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| CN201420764048.5U CN204271694U (en) | 2014-12-08 | 2014-12-08 | A kind of wireless charger with WIFI function |
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| CN201420764048.5U CN204271694U (en) | 2014-12-08 | 2014-12-08 | A kind of wireless charger with WIFI function |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994685A (en) * | 2016-10-26 | 2018-05-04 | 恩智浦美国有限公司 | Outer analyte detection |
| CN108601149A (en) * | 2018-06-07 | 2018-09-28 | 杭州优特电源有限公司 | A kind of LED driver for supporting DMX512, IP67 and NFC wireless mode setup parameter |
| RU2737415C1 (en) * | 2017-03-10 | 2020-11-30 | Просек Са | Concrete construction probing using electromagnetic waves |
| CN113031075A (en) * | 2019-12-25 | 2021-06-25 | 圣邦微电子（北京）股份有限公司 | Detection circuit and detection method based on wireless charging |
| CN116597770A (en) * | 2023-04-25 | 2023-08-15 | 深圳康易世佳科技有限公司 | Interactive wisdom LED display screen |
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2014
- 2014-12-08 CN CN201420764048.5U patent/CN204271694U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994685A (en) * | 2016-10-26 | 2018-05-04 | 恩智浦美国有限公司 | Outer analyte detection |
| CN107994685B (en) * | 2016-10-26 | 2023-11-24 | 恩智浦美国有限公司 | Foreign object detection |
| RU2737415C1 (en) * | 2017-03-10 | 2020-11-30 | Просек Са | Concrete construction probing using electromagnetic waves |
| US11275073B2 (en) | 2017-03-10 | 2022-03-15 | Proceq Sa | Probing a structure of concrete by means of electromagnetic waves |
| CN108601149A (en) * | 2018-06-07 | 2018-09-28 | 杭州优特电源有限公司 | A kind of LED driver for supporting DMX512, IP67 and NFC wireless mode setup parameter |
| CN108601149B (en) * | 2018-06-07 | 2024-03-19 | 杭州优特电源有限公司 | LED driver supporting DMX512, IP67 and NFC wireless mode setting parameters |
| CN113031075A (en) * | 2019-12-25 | 2021-06-25 | 圣邦微电子（北京）股份有限公司 | Detection circuit and detection method based on wireless charging |
| CN113031075B (en) * | 2019-12-25 | 2024-01-26 | 圣邦微电子（北京）股份有限公司 | Detection circuit and detection method based on wireless charging |
| CN116597770A (en) * | 2023-04-25 | 2023-08-15 | 深圳康易世佳科技有限公司 | Interactive wisdom LED display screen |
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