CN104505126B - A kind of dynamic memory test system and method - Google Patents
A kind of dynamic memory test system and method Download PDFInfo
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- CN104505126B CN104505126B CN201410751100.8A CN201410751100A CN104505126B CN 104505126 B CN104505126 B CN 104505126B CN 201410751100 A CN201410751100 A CN 201410751100A CN 104505126 B CN104505126 B CN 104505126B
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Abstract
The invention discloses a kind of dynamic memories to test system and method；The dynamic memory tests system：Test vector generation and update platform, are used to carry out Software Simulation Test by dynamic memory simulation model；Need the data for capturing test waveform to generate specific test vector according to current test；It controls the dynamic memory and is in vectorial more new state, execute renewal vector operation, by test vector update to dynamic memory test device；Dynamic memory test device is used to store current test test vector used, and controls dynamic memory and execute testing process.The various specific test vectors needed for comprehensive test dynamic memory instructing combination can occur in by dynamic memory test vector generation and update platform in the present invention and be transmitted to dynamic memory test device online, it realizes dynamic update test vector, supports quickly test dynamic memory comprehensively.It the composite can be widely applied to digital test field.
Description
Technical field
The present invention relates to digital test fields, it is more particularly related to which dynamic memory tests system and method.
Background technology
Among dynamic memory is widely present in computer system as a kind of general memory, and to the work(of memory
It is the necessary condition for ensureing memory energy reliability service that the progress of energy index is comprehensively tested in detail；Comprehensive test is related to dynamic
The all possible operation mode of memory, test device allow for generating corresponding test vector, and comprehensive test here is main
It is for instruction operation legal in dynamic memory, the valid instruction of dynamic memory includes common reading and writing, preliminary filling
Electricity etc., several during these are instructed combine, and different instructing combinations are occurred as soon as, such as write by reading, by writing
It reads, by reading precharge etc., the conversion of these instructions generally can be all illustrated in the handbook of dynamic memory；Existing dynamic
Memorizer test device can't go to support all possible instructing combination, general carry out dynamic memory to pursue performance
Therefore the test of the dependent instructions such as reading and writing carries out test to dynamic memory and is likely to omit certain combinations, and cannot
Support comprehensive test.
Invention content
In order to solve the above-mentioned technical problem, the object of the present invention is to provide a kind of dynamic memory test device, it can be achieved that
Dynamic memory is tested comprehensively.
The technical solution adopted in the present invention is a kind of dynamic memory test system, including：Test vector generation and more
New platform is used to carry out Software Simulation Test by dynamic memory simulation model；
According to the number of test waveform in current desired dynamic memory instructing combination crawl Software Simulation Test to be tested
Corresponding test vector is generated according to this；It controls the dynamic memory and is in vectorial more new state, execute online updating operation, it will
The test vector is updated to dynamic memory test device；
Dynamic memory test device is used to store current test test vector used, and controls dynamic memory
Execute testing process.
Preferably, the dynamic memory test device includes Logic control module, test vector memory module, judgement mould
Block；
The test vector memory module, the test vector used for storing current test, and connect it is described test to
Amount generates and update platform, needs to receive the test vector generation according to current test and update platform is currently stored to its
Test vector is updated；
The test vector memory module under the triggering for the vectorial enable signal that Logic control module is sent, will test to
The test data of amount is sent to dynamic memory；
The Logic control module is used to configure the parameter of current dynamic memory, and control dynamic memory sequence executes survey
Examination vector；
Determination module, under the triggering for the comparison enable signal that Logic control module is sent, dynamic memory to be rung
Data are answered to be compared with dynamic memory test data is written to.
Preferably, the determination module includes：Data buffer is written, reads data buffer, comparing unit；
The test vector memory module is sent to while the test data of test vector is sent to dynamic memory
Said write data buffer and the Logic control module；
The reading data buffer is for caching dynamic memory response data；
Test vector described in each, which has, identifies its vector data and vector numbers for starting and terminating；
The Logic control module sends relatively more enabled trigger signal to the comparing unit according to the mark data；
The comparing unit according to relatively enable trigger signal sequence read recorded dynamic memory response data and
The used data of test vector, and compare whether the two coincide, comparison result is returned into the Logic control module；
Vector numbers when the Logic control module record is misfitted.
Preferably, the test vector generation and update platform are computer, and the test vector of generation is via parallel interface cable
It is sent to the test vector memory module.
Another technical solution of the present invention is：A kind of dynamic memory test method, includes the following steps：
Test vector generation and update platform are created, Software Simulation Test is carried out by dynamic memory simulation model；
According to the number of test waveform in current desired dynamic memory instructing combination crawl Software Simulation Test to be tested
Corresponding test vector is generated according to this；
It controls the dynamic memory and is in vectorial more new state, execute online updating operation, more by the test vector
Newly arrive dynamic memory test device；
After online updating operates, dynamic memory test device controls dynamic memory and executes testing process.
Preferably, the dynamic memory test device control dynamic memory executes testing process and specifically includes following step
Suddenly：
S1）Dynamic memory is initialized, dynamic memory is made to be configured at desired operating mode；
S2）Read test vector in the dynamic memory test device；Test vector is executed, by the test vector
Dynamic memory is written in vector data, records used vector data and dynamic memory response data；
S3）The vector data of said write dynamic memory and dynamic memory response data are compared；
S4 step S2- step S3) are repeated, until testing all test vectors in the dynamic memory device.
Preferably, test vector described in each, which has, identifies its vector data and vector numbers for starting and terminating,
The step S2) and step S3) between further include following steps：
Y1) judge whether the vector data is to identify the vector data started；
If the vector data is the vector data that mark starts, the vector numbers are recorded, and execute step S2)；
If the vector data is not the vector data that mark starts, further judge whether the vector data is mark
Know the vector data terminated；
If the vector data is not the vector data that mark terminates, S2 is thened follow the steps)；
If the vector data is the vector data that mark terminates, Y2 is thened follow the steps)；
Y2) test vector of the dynamic memory test device is read in pause, into comparing state, executes step
S3)。
Preferably, the step S3) it specifically comprises the following steps：
S31) sequence reads the vector data and dynamic memory response data of said write dynamic memory；
S32) compare whether the two coincide；
If the two is coincide, S2 is thened follow the steps)；
If the two misfits, S33 is thened follow the steps)；
S33 vector numbers when) record is misfitted.
The present invention the first advantageous effect be：
A kind of dynamic memory test system provided by the present invention includes test vector generation and update platform；In dynamic
In memory testing system, dynamic memory test vector generation and update platform can occur in comprehensive test dynamic memory
Various specific test vectors needed for device instructing combination are simultaneously transmitted to dynamic memory test device online, realize that dynamic updates
Test vector supports quickly test dynamic memory comprehensively.
The present invention another advantageous effect be：
A kind of dynamic memory test method provided by the invention, by creating test vector generation and update platform to produce
It is raw to test the various specific test vectors needed for dynamic memory instructing combination comprehensively and be transmitted to dynamic memory survey online
Trial assembly is set, and is realized dynamic update test vector, is supported quickly test dynamic memory comprehensively.
Description of the drawings
The specific implementation mode of the present invention is described further below in conjunction with the accompanying drawings：
Fig. 1 is a kind of dynamic memory test system structure schematic diagram of the present invention；
Fig. 2 is that dynamic memory tests one specific embodiment structural schematic diagram of system；
Fig. 3 is a kind of flow diagram of dynamic memory test method of the present invention；
Fig. 4 is that dynamic memory test device controls dynamic memory execution testing process schematic diagram；
Fig. 5 is that dynamic memory test device controls dynamic memory execution one specific embodiment flow of testing process signal
Figure.
Specific implementation mode
The principle and feature of invention are described below in conjunction with attached drawing, example is served only for explaining invention, not uses
In restriction the scope of the present invention.
Fig. 1 is a kind of dynamic memory test system structure schematic diagram of the present invention；As shown in Figure 1, a kind of dynamic of the present invention
Memory testing system, including：Test vector generation and update platform are used to carry out by dynamic memory simulation model soft
Part emulation testing, according to test waveform in current desired dynamic memory instructing combination crawl Software Simulation Test to be tested
Data are to generate corresponding test vector；It controls the dynamic memory and is in vectorial more new state, execute online updating operation,
By test vector update to dynamic memory test device；Dynamic memory test device is used to store current test
Test vector used, and control dynamic memory and execute testing process.
It can generally illustrate the conversion between the valid instruction supported described in dynamic memory in the handbook of dynamic memory,
The method for testing specific instructing combination is gone using specific test vector in the present invention, is retouched according to the handbook of dynamic memory
All instructing combinations stated generate corresponding test vector and go to test to realize the performance of comprehensive test dynamic memory, and
It does not omit.In the present embodiment, test vector generation and update platform are computer, by using the dynamic memory in computer
Device simulation model generates the various specific test vectors needed for test dynamic memory comprehensively, and detailed process includes：Pass through
Software module corresponds to chip model and generates test vector initial data, and recording the data and carrying out processing generation to its format can deposit
Enter the test vector of test vector memory module, the test vector of generation is sent to the dynamic memory via parallel interface cable and surveys
Trial assembly is set；In the present embodiment, a plurality of test vector can sequentially be stored in a vectorial initial data document and be used for format
Processing and vector test.
Fig. 2 is one specific embodiment structural schematic diagram of dynamic memory test device；As shown in Fig. 2, in the present embodiment,
Dynamic memory test device includes Logic control module, test vector memory module, determination module；
Test vector memory module, the test vector used for storing current test, and connect the test vector life
At with update platform, the test vector that acceptance test vector generates and update platform is currently stored to its is needed according to current test
It is updated.
Test vector memory module is under the triggering for the vectorial enable signal that Logic control module is sent, by test vector
Test data is sent to dynamic memory.In the present embodiment, vectorial enable signal is the control signal that width is 1, main to use
In the output of control test vector memory module, vectorial memory module output data is allowed when enable signal is 1, is 0
When prohibiting vector memory module output.
Logic control module is used to configure the parameter of current dynamic memory, control dynamic memory sequence execute test to
Amount；
Determination module, under the triggering for the comparison enable signal that Logic control module is sent, dynamic memory to be rung
Data are answered to be compared with dynamic memory test data is written to；In the present embodiment, compare enable signal and above-mentioned vector
Enable signal is equally the control signal that width is 1, and effect is exactly that enabled determination module progress data compare operation.
In the present embodiment, determination module includes：Data buffer is written, reads data buffer, comparing unit；Test
Vectorial memory module be sent to while the test data of test vector is sent to dynamic memory write-in data buffer and
The Logic control module；Data buffer is read for caching dynamic memory response data；Each test vector has
Identify its vector data and vector numbers for starting and terminating；Logic control module sends relatively more enabled touch according to mark data
Send signals to the comparing unit；Comparing unit reads recorded dynamic memory sound according to trigger signal sequence is relatively enabled
Data and the used data of test vector are answered, and compare whether the two coincide, comparison result is returned into the Logic control module；
Vector numbers when Logic control module record is misfitted, vector numbers when record is misfitted contribute to follow-up poor prognostic cause
Analysis.
A kind of dynamic memory provided by the invention tests system, can be generated by test vector generation and update platform
The various specific test vectors needed for dynamic memory instructing combination are tested comprehensively and are transmitted to dynamic memory test online
Device realizes dynamic update test vector, achievees the purpose that quickly test dynamic memory comprehensively.
The present invention also provides a kind of dynamic memory test method, Fig. 3 is a kind of dynamic memory test side of the present invention
The flow diagram of method, as shown in figure 3, a kind of dynamic memory test method, includes the following steps：
Test vector generation and update platform are created, Software Simulation Test is carried out by dynamic memory simulation model；
According to the number of test waveform in current desired dynamic memory instructing combination crawl Software Simulation Test to be tested
Corresponding test vector is generated according to this；
It controls the dynamic memory and is in vectorial more new state, execute online updating operation, more by the test vector
Newly arrive dynamic memory test device.
The present invention goes the method for testing specific instructing combination using specific test vector, according to the hand of dynamic memory
All instructing combinations described in volume go to test to realize the performance of comprehensive test dynamic memory, do not omit, create
Test vector generation and update platform main purpose are various specific needed for the comprehensive test dynamic memory instructing combination of generation
Test vector, and the test vector is updated into dynamic memory test device by online updating mode, supported quick
Test dynamic memory comprehensively.
In the present embodiment, online updating operation is included the following steps by being accomplished manually：Control dynamic memory test dress
It sets in reset state, transmission test vector to dynamic memory test device, renewal vector operation terminates, and controls dynamic memory
Test device withdraws reset state, and dynamic memory test device enters normal operating conditions.
After online updating operates, dynamic memory test device controls dynamic memory and executes testing process.Fig. 4 is
Dynamic memory test device controls dynamic memory and executes testing process schematic diagram, as shown in figure 4, in the present embodiment, moving
State memorizer test device control dynamic memory executes testing process and specifically comprises the following steps：
S1）Dynamic memory is initialized, dynamic memory is made to be configured at desired operating mode；
S2）Read test vector in the dynamic memory test device；Test vector is executed, by the test vector
Dynamic memory is written in vector data, record used in vector data and dynamic memory response data, execute test to
During amount, dynamic memory refresh operation is kept.
S3）The vector data of said write dynamic memory and dynamic memory response data are compared；It is executing
During data compare, dynamic memory refresh operation is kept；When needing longer one section because of the operation for being compared the two data
Between, the length of this period has been more than the required maximum time interval of dynamic memory distributed refresh, therefore the present embodiment
In keep refresh operation during carrying out data comparison, ensure that dynamic memory internal data will not lose.
S4 step S2- step S3) are repeated, until testing all test vectors in the dynamic memory device.
Fig. 5 is that dynamic memory test device controls dynamic memory execution one specific embodiment flow of testing process signal
Figure, as shown in figure 5, in this embodiment, each test vector have mark its start with the vector data that terminates with
And vector numbers, in step S2) following steps are executed afterwards：
Y1) judge whether vector data is to identify the vector data started；
If vector data is the vector data that mark starts, the vector numbers are recorded, and execute step S2)；
If vector data is not the vector data that mark starts, further judge whether the vector data is mark knot
The vector data of beam；
If the vector data is not the vector data that mark terminates, S2 is thened follow the steps)；
If the vector data is the vector data that mark terminates, Y2 is thened follow the steps)；
Y2) test vector of the dynamic memory test device is read in pause, into comparing state, keeps dynamic
Memory refresh operation executes step S3).
Step S3 in the present embodiment) it specifically comprises the following steps：
S31) sequence reads the vector data and dynamic memory response data of said write dynamic memory；
S32) compare whether the two coincide；
If the two is coincide, S2 is thened follow the steps)；
If the two misfits, S33 is thened follow the steps)；
S33 then vector numbers when) record is misfitted execute step S2).Vector numbers when misfitting are recorded, are
Engineering staff subsequently provides strong foundation to the analysis of product poor prognostic cause, and engineering staff is contributed to more rapidly, accurately to find
Problem.
A kind of dynamic memory test method provided by the invention, by creating test vector generation and update platform to produce
It is raw to test the various specific test vectors needed for dynamic memory instructing combination comprehensively and be transmitted to dynamic memory survey online
Trial assembly is set, and is realized dynamic update test vector, is supported quickly test dynamic memory comprehensively.
It is to be illustrated to the preferable implementation of the present invention, but the invention is not limited to embodiment above, it is ripe
Various equivalent variations or replacement can also be made under the premise of without prejudice to spirit of that invention by knowing those skilled in the art, this
Equivalent deformation or replacement are all contained in the application claim limited range a bit.
Claims (6)
1. a kind of dynamic memory tests system, it is characterised in that：Including：
Test vector generation and update platform, are used to carry out Software Simulation Test by dynamic memory simulation model；According to
The data of test waveform are to generate comprehensively in current desired dynamic memory instructing combination crawl Software Simulation Test to be tested
Corresponding various test vectors；It controls the dynamic memory and is in vectorial more new state, online updating operation is executed, by institute
Test vector update is stated to dynamic memory test device；
Dynamic memory test device is used to store current test test vector used, and controls dynamic memory execution
Testing process；
The dynamic memory test device includes Logic control module, test vector memory module, determination module；
The test vector memory module, the test vector used for storing current test, and connect the test vector life
At with update platform, need to receive the test vector generation according to current test and update the platform test currently stored to its
Vector is updated；
The test vector memory module is under the triggering for the vectorial enable signal that Logic control module is sent, by test vector
Test data is sent to dynamic memory；
The Logic control module is used to configure the parameter of current dynamic memory, control dynamic memory sequence execute test to
Amount；
Determination module is used under the triggering for the comparison enable signal that Logic control module is sent, by dynamic memory number of responses
According to be written to dynamic memory test data and be compared.
2. a kind of dynamic memory tests system according to claim 1, it is characterised in that：The determination module includes：It writes
Enter data buffer, read data buffer, comparing unit；
The test vector memory module is sent to described while the test data of test vector is sent to dynamic memory
Data buffer and the Logic control module is written；
The reading data buffer is for caching dynamic memory response data；
Test vector described in each, which has, identifies its vector data and vector numbers for starting and terminating；
The Logic control module sends relatively more enabled trigger signal to the ratio according to the vector data and vector numbers
Compared with unit；
The comparing unit reads recorded dynamic memory response data and described according to trigger signal sequence is relatively enabled
The test data of test vector, and compare whether the two coincide, comparison result is returned into the Logic control module；
Vector numbers when the Logic control module record is misfitted.
3. a kind of dynamic memory tests system according to claim 2, which is characterized in that the test vector generation and more
New platform is computer, and the test vector of generation is sent to the test vector memory module via parallel interface cable.
4. a kind of dynamic memory test method, includes the following steps：
Test vector generation and update platform are created, Software Simulation Test is carried out by dynamic memory simulation model；
According to the data of test waveform in current desired dynamic memory instructing combination to be tested crawl Software Simulation Test with
Generate comprehensive corresponding various test vectors；
It controls the dynamic memory and is in vectorial more new state, execute online updating operation, test vector update is arrived
Dynamic memory test device；
After online updating operates, dynamic memory test device controls dynamic memory and executes testing process；
The dynamic memory test device control dynamic memory executes testing process and specifically comprises the following steps：
S1 dynamic memory) is initialized, dynamic memory is made to be configured at desired operating mode；
S2 test vector in the dynamic memory test device) is read；Test vector is executed, by the vector of the test vector
Dynamic memory is written in data, records used vector data and dynamic memory response data；
S3) vector data of said write dynamic memory and dynamic memory response data are compared, executing data
During comparing, dynamic memory refresh operation is kept；
S4 step S2- step S3) are repeated, until testing all test vectors in the dynamic memory device.
5. a kind of dynamic memory test method according to claim 4, it is characterised in that：Test vector described in each is all
Have mark its start with terminate vector data and vector numbers, the step S2) and step S3) between further include walking as follows
Suddenly：
Y1) judge whether the vector data is to identify the vector data started；
If the vector data is the vector data that mark starts, the vector numbers are recorded, and execute step S2)；
If the vector data is not the vector data that mark starts, further judge whether the vector data is mark knot
The vector data of beam；
If the vector data is not the vector data that mark terminates, S2 is thened follow the steps)；
If the vector data is the vector data that mark terminates, Y2 is thened follow the steps)；
Y2) test vector of the dynamic memory test device is read in pause, into comparing state, executes step S3).
6. a kind of dynamic memory test method according to claim 5, it is characterised in that：The step S3) its specific packet
Include following steps：
S31) sequence reads the vector data and dynamic memory response data of said write dynamic memory；
S32) compare whether the two coincide；
If the two is coincide, S2 is thened follow the steps)；
If the two misfits, S33 is thened follow the steps)；
S33 vector numbers when) record is misfitted.
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| CN105389237A (en) * | 2015-12-15 | 2016-03-09 | 江苏辰云信息科技有限公司 | Performance test tool for block-level storage system |
| CN107705819A (en) * | 2017-09-21 | 2018-02-16 | 深圳市致存微电子企业（有限合伙） | A kind of storage chip sorting technique, sorter and categorizing system |
| CN109725249A (en) * | 2019-01-31 | 2019-05-07 | 安庆师范大学 | A kind of testing process dynamic adjusting method and adjustment system |
| CN109817273B (en) * | 2019-02-12 | 2020-12-29 | 记忆科技(深圳)有限公司 | NAND performance test method and system |
| CN110632499B (en) * | 2019-09-23 | 2021-04-23 | 珠海格力电器股份有限公司 | Test vector generation method based on test object and storage medium |
| CN113393892A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
| CN113391184A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
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| CN101038325A (en) * | 2007-02-14 | 2007-09-19 | 北京中星微电子有限公司 | Method and device for testing chip |
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| JP2005011451A (en) * | 2003-06-19 | 2005-01-13 | Advantest Corp | Test device and program |
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| TWI221614B (en) * | 2000-07-31 | 2004-10-01 | Hitachi Ltd | Tester architecture construction data generating method, tester architecture constructing method and test circuit |
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