CN104505098A

CN104505098A - AMBE (advanced multi-band excitation) speech compression circuit based on FPGA (field programmable gate array)

Info

Publication number: CN104505098A
Application number: CN201410807900.7A
Authority: CN
Inventors: 谢建庭; 常涛; 张宇; 宋光伟; 孙光
Original assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Current assignee: Tianjin Optical Electrical Communication Technology Co Ltd
Priority date: 2014-12-23
Filing date: 2014-12-23
Publication date: 2015-04-08

Abstract

The invention relates to an AMBE (advanced multi-band excitation) speech compression circuit based on an FPGA (field programmable gate array). The AMBE speech compression circuit comprises a power supply circuit, an FPGA chip, included work procedures, an AMBE encoding chip circuit, a PCM (pulse code modulation) encoding chip circuit, a signal amplification circuit, a UART (universal asynchronous receiver/transmitter) serial port circuit, a clock circuit, an off-chip program storage circuit and a JTAG (joint test action group) program downloading debugging circuit, wherein an inside circuit structure of the FPGA chip comprises a clock management module, a PCM chip time sequence control module, an AMBE chip control module and a UART serial port communication module. The circuit realization process is flexible and reliable. When a compressed encoding algorithm is adopted, the transmission under the conditions of low code rate, real time, secrecy and the like can be realized, in addition, excellent speech quality can be obtained, and the bandwidth can be effectively saved. Through the circuit design, the speech digital information speed can be accelerated, and can be compressed to 2.4kbps from the standard 64kbps, and the data validity is improved, so that the code rate of communication data information is reduced.

Description

A kind of AMBE compress speech circuit based on FPGA

Technical field

The present invention relates to digital communication system, particularly relate to the senior multiband voice-excited vocoder of a kind of AMBE(based on FPGA) compress speech circuit.

Background technology

Speech Signal Compression coding is an importance of Speech processing, and Speech processing is then ingredient indispensable in means of communication.The object of voice compression coding obtains synthesis speech quality as well as possible with alap numeric code rate.

Transmission and the process of early stage voice signal are carried out all in an analog fashion.After pulse code modulation (pcm) theory proposes, Speech processing enters digital times.From the vocoder of the Standard PC M wave coder of the initial 64kbps parameter coding of below 4kbps till now, voice compression coding is developed rapidly in decades.The transmission of digitize voice and everyways such as being stored in reliability, anti-interference, confidentiality are much better than analog voice.

Speech coding technology produces along with the digitizing of voice, is mainly used in Digital Speech Communication at present and digital speech stores two fields.Owing to being quantized the audio digital signals obtained simply by continuous speech signal sampling, a large amount of channel resources and storage space to be taken when transmitting and store, therefore, how when reducing distortion as far as possible, expeditiously digital expression is carried out to analog voice signal, i.e. compressed encoding, just becomes the main contents of speech coding technology.

In digital mobile communication system, frequency resource is very limited.If the data signal rate of voice coding is too high, wide frequency range can be taken, can power system capacity be reduced undoubtedly.If but the speed of voice coding is too low, speech quality can be made again to reduce, so adopt a kind of speech coding technology of high-quality low rate to be very crucial.

Summary of the invention

In view of prior art Problems existing and defect, the invention provides a kind of AMBE compress speech circuit based on FPGA.By analyzing current speech signal digital development situation, recognizing Speech Signal Compression coding importance, by using dedicated voice compression chip to design, realizing a kind of AMBE compress speech circuit based on FPGA.

The technical scheme that the present invention is taked for achieving the above object is: a kind of AMBE compress speech circuit based on FPGA, is characterized in that: comprise power circuit, fpga chip and the working routine comprised, AMBE coding chip circuit, pcm encoder chip circuit, signal amplification circuit, UART serial port circuit, clock circuit, the outer program storing circuit of sheet and JTAG download program debug circuit; Wherein fpga chip is connected with AMBE coding chip circuit, pcm encoder chip circuit, UART serial port circuit, clock circuit, the outer program storing circuit of sheet and JTAG download program debug circuit respectively, pcm encoder chip circuit is connected with signal amplification circuit, signal amplification circuit is connected to outside analog voice input-output device, and UART serial port circuit is connected to external unit; Described fpga chip internal circuit configuration comprises Clock management module, PCM chip time-sequence control module, AMBE chip control module and UART serial communication modular; Wherein PCM chip time-sequence control module is connected with AMBE chip control module, AMBE chip control module is connected with UART serial communication modular, PCM chip time-sequence control module connects pcm encoder chip circuit, AMBE chip control module connects AMBE coding chip circuit, and UART serial communication modular connects UART serial port circuit.

Fpga chip working routine flow process of the present invention is: after system electrification, first fpga chip loads data, and be about to deposit digital independent in the outer FLASH of sheet in the RAM of fpga chip inside, after program has loaded, fpga chip is started working; Next step carries out initial configuration to pcm encoder chip and AMBE coding chip, after having configured, pcm encoder chip and AMBE coding chip are worked by two data paths simultaneously, wherein a data path is that equipment receives component frame data from UART serial ports termination, valid data extract and framing again by fpga chip, output to AMBE coding chip; Another data path is that equipment is received externally analogue voice signal, pcm encoder chip is given after signal amplification circuit, analog voltage signal is converted to the digital signal of 64kbps speed to AMBE coding chip by pcm encoder chip, AMBE coding chip sends to fpga chip after the high speed voice digital signal of 64kbps is compressed into low rate speech digital signal, fpga chip reformulates UART serial data frame after extracting valid data, after UART serial port chip, send to far-end.

Feature of the present invention and beneficial effect are: adopt FPGA to carry out Systematical control and data processing; Dedicated voice compression chip is used to realize Speech Signal Compression coding.UART serial ports is adopted externally to communicate; Implementation procedure flexibly, reliably.The Coding Compression Algorithm adopted can be implemented in low bit-rate, in real time, transmits under the condition such as to maintain secrecy, and can obtain excellent voice quality, and effectively can save bandwidth.This circuit design can improve the speed of voice digitization information, is compressed to 2.4kbps from the 64kbps of standard, improves the validity of data, thus reduces the code speed of communication data information.

Accompanying drawing explanation

Fig. 1 is circuit catenation principle block diagram of the present invention;

Fig. 2 is fpga chip internal circuit configuration theory diagram in Fig. 1;

Fig. 3 is FPGA workflow diagram of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described:

As shown in Figure 1, a kind of AMBE compress speech circuit based on FPGA comprises power circuit, fpga chip, AMBE coding chip circuit, pcm encoder chip circuit, signal amplification circuit, UART serial port circuit, clock circuit, the outer program storing circuit of sheet and JTAG download program debug circuit; Wherein fpga chip is connected with AMBE coding chip circuit, pcm encoder chip circuit, UART serial port circuit, clock circuit, the outer program storing circuit of sheet and JTAG download program debug circuit respectively, pcm encoder chip circuit is connected with signal amplification circuit, signal amplification circuit is connected to outside analog voice input-output device (loudspeaker and microphone), and UART serial port circuit is connected to external unit.

In figure, fpga chip is the core of whole circuit.Clock circuit provides work clock for fpga chip, power circuit provides required power supply for whole system, JTAG download program debug circuit is used for debugging and download program fpga chip, pcm encoder chip circuit is used for digital signal analog voice signal being converted to 64kbps, AMBE coding chip circuit is used for the low-speed digital information digital signal of 64kbps being compressed to 2.4kbps, signal amplification circuit is used for analog voice signal to amplify, and UART serial port circuit is for realizing the serial ports electric signal of standard.

As shown in Figure 2, fpga chip internal circuit configuration comprises Clock management module, PCM chip time-sequence control module, AMBE chip control module and UART serial communication modular; Wherein PCM chip time-sequence control module is connected with AMBE chip control module, AMBE chip control module is connected with UART serial communication modular, PCM chip time-sequence control module connects pcm encoder chip circuit, AMBE chip control module connects AMBE coding chip circuit, and UART serial communication modular connects UART serial port circuit.

In figure, Clock management module is used for carrying out frequency multiplication, scaling down processing to input clock, makes the clock needed for its output services; PCM chip time-sequence control module is used for pcm encoder chip is normally worked; The mode of operation of AMBE chip control module for control AMBE coding chip and the two-way exchange of data; UART serial communication modular is used for realizing serial port protocol, carries out external compressed voice data communication.

As shown in Figure 3, fpga chip working routine flow process is: after system electrification, first fpga chip loads data, and be about to deposit digital independent in the outer FLASH of sheet in the RAM of FPGA inside, program has loaded rear FPGA and started working, next step carries out initial configuration to pcm encoder chip and AMBE compressed encoding chip, and the parameter such as compressing data rate, check bit, data frame format is configured according to actual needs, has configured rear pcm encoder chip and AMBE coding chip is started working, because fpga chip is applicable to parallel processing work, so two data paths can work simultaneously, wherein a data path is that equipment receives component frame data (as the voice compression coding Framed Data that opposite end sends) from UART serial ports termination, valid data extract and framing (meeting the data layout of AMBE chip requirement) again by fpga chip, with the data demand of applicable AMBE coding chip, AMBE coding chip decompresses after receiving the low bit-rate data after overcompression, and the data (speed is 64kbps) after decompressing are sent to pcm encoder chip, pcm encoder chip outputs to outside loudspeaker after numerical information being converted to analog voltage signal drive singal amplifying circuit, another data path is that equipment is received externally analogue voice signal, pcm encoder chip is given after signal amplification circuit, analog voltage signal is converted to the digital signal of 64kbps speed to AMBE coding chip by pcm encoder chip, AMBE coding chip sends to fpga chip after the high speed voice digital signal of 64kbps is compressed into low rate speech digital signal, fpga chip reformulates UART serial data frame (meeting the data layout of UART serial ports requirement) after extracting valid data, after UART serial port chip, send to far-end.

Claims

1. based on an AMBE compress speech circuit of FPGA, it is characterized in that: comprise power circuit, fpga chip and the working routine comprised, AMBE coding chip circuit, pcm encoder chip circuit, signal amplification circuit, UART serial port circuit, clock circuit, the outer program storing circuit of sheet and JTAG download program debug circuit; Wherein fpga chip is connected with AMBE coding chip circuit, pcm encoder chip circuit, UART serial port circuit, clock circuit, the outer program storing circuit of sheet and JTAG download program debug circuit respectively, pcm encoder chip circuit is connected with signal amplification circuit, signal amplification circuit is connected to outside analog voice input-output device, and UART serial port circuit is connected to external unit; Described fpga chip internal circuit configuration comprises Clock management module, PCM chip time-sequence control module, AMBE chip control module and UART serial communication modular; Wherein PCM chip time-sequence control module is connected with AMBE chip control module, AMBE chip control module is connected with UART serial communication modular, PCM chip time-sequence control module connects pcm encoder chip circuit, AMBE chip control module connects AMBE coding chip circuit, and UART serial communication modular connects UART serial port circuit.

2. a kind of AMBE compress speech circuit based on FPGA according to claim 1, it is characterized in that: fpga chip working routine flow process is: after system electrification, first fpga chip loads data, be about to deposit digital independent in the outer FLASH of sheet in the RAM of fpga chip inside, after program has loaded, fpga chip is started working; Next step carries out initial configuration to pcm encoder chip and AMBE coding chip, after having configured, pcm encoder chip and AMBE coding chip are worked by two data paths simultaneously, wherein a data path is that equipment receives component frame data from UART serial ports termination, valid data extract and framing again by fpga chip, output to AMBE coding chip; Another data path is that equipment is received externally analogue voice signal, pcm encoder chip is given after signal amplification circuit, analog voltage signal is converted to the digital signal of 64kbps speed to AMBE coding chip by pcm encoder chip, AMBE coding chip sends to fpga chip after the high speed voice digital signal of 64kbps is compressed into low rate speech digital signal, fpga chip reformulates UART serial data frame after extracting valid data, after UART serial port chip, send to far-end.