CN104503930A - Stepping scanning control device and method in electromagnetic interference test receiver - Google Patents
Stepping scanning control device and method in electromagnetic interference test receiver Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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Abstract
The invention provides a stepping scanning control device and method in an electromagnetic interference test receiver. The stepping scanning control device comprises an adjusting parameter register/gating controller, a data source selector, a data parameter RAM (Random Access Memory), an RAM address counter, an HSCAN generator, an interrupt manager, an interrupt register and a starter. By the aid of the stepping scanning control device, an interrupt processing process which completely depended on the participation of a CPU (Central Processing Unit) before is commonly finished by the CPU and the stepping scanning control device; the CPU is only interacted with the stepping scanning control device so that the control working amount of the CPU is alleviated; meanwhile, the CPU does not need to recalculate scanning parameters so that the operation efficiency of procedures is improved; previous all relatively-dispersed modules are integrated into the semi-automatic stepping scanning control device and are matched with the CPU, so that the interrupt processing work can be efficiently finished.
Description
Technical Field
The invention relates to the technical field of testing, in particular to a step scanning control device in an electromagnetic interference testing receiver and a step scanning control method in the electromagnetic interference testing receiver.
Background
In the process of performing the electromagnetic compatibility certification test, in order to obtain a more accurate field strength value of a received signal, the electromagnetic interference test receiver needs to have self-adjusting capability to ensure that the receiver is in an optimal receiving state, and therefore, the electromagnetic interference test receiver needs to respond to internal interruption at any time and make corresponding adjustment according to a receiver program.
At present, a circuit control part, an HSCAN generation part, an interrupt response part and the like in an electromagnetic interference test receiver are dispersed and have no synchronous processing mechanism, and all parts completely depend on a CPU in cooperative work. The scanning process is as follows:
1) the CPU sets scanning parameters and generates HSCAN starting scanning;
2) in the scanning process, after receiving the interrupt, the CPU terminates the HSCAN signal and finishes the scanning;
3) the CPU controls each circuit to carry out corresponding adjustment;
4) the CPU checks whether the adjustment is effective, and if the adjustment is ineffective, the adjustment process is repeated;
5) the CPU recalculates and sets each scanning parameter after the interruption point;
6) and the CPU restarts the HSCAN to scan.
The defects of the prior art are as follows: after receiving the interrupt, the CPU needs to recalculate the scan parameters and reset each circuit, and then the step-by-step scan process can be continued, which results in a very long time for the scan interrupt processing process, on the other hand, increases the workload of parameter recalculation and hardware control, and reduces the software running efficiency. This approach significantly increases test time if there are multiple interruptions in the scan process.
At present, the adjustment process completely depends on a CPU, the control efficiency is low, and how to implement the receiver adjustment efficiently in the step scanning process is an urgent technical problem to be solved in the field.
Disclosure of Invention
Aiming at the defects of the prior art, the application designs a stepping scanning control device and method in an electromagnetic interference test receiver, and the interrupt processing efficiency is effectively improved.
The technical scheme of the invention is realized as follows:
a step-and-scan control apparatus in an electromagnetic interference test receiver, comprising: the system comprises an adjustment parameter register/gating controller, a data source selector, a state parameter RAM, an RAM address counter, an HSCAN generator, an interrupt manager, an interrupt register and a starter; wherein,
adjusting parameter register/gating controller: registering an adjusting parameter and a data source selector switch state transmitted by the data bus through the address A and the data bus;
the data source selector: selecting a data source according to the on-off state registered by the adjustment parameter register/gating controller, outputting data of the data source under the action of a clock, and controlling each circuit of the receiver;
a state parameter RAM: registering scanning parameters corresponding to each stepping frequency point, wherein the writing address and the writing operation of the scanning parameters are completed by a CPU through an address B and a data bus;
RAM address counter: counting the HSCAN signals, generating a read pulse of a state parameter RAM after counting, and registering a mode of an internal counter transmitted from a data bus through an address C and the data bus;
HSCAN generator: registering a mode of an internal counter transmitted by the data bus through the address D and the data bus, generating an HSCAN signal when a count value is equal to the mode of the internal counter, and controlling a counting enabling end of the internal counter of the HSCAN generator by an interrupt manager;
an interrupt manager: after receiving the interrupt generated by the interrupt register, controlling an internal counter of the HSCAN generator to stop counting;
an interrupt register: after receiving the external interrupt, registering an interrupt number and generating CPU interrupt; the registered interrupt number is transmitted to the CPU through an address E and a data bus; after receiving the reset signal, resetting the internal register to generate a reset output signal;
a starter: through the address F and data bus, an internal clock signal is generated.
Optionally, the read address of the state parameter RAM is a count value of a RAM address counter, and the read operation is completed by a pulse generated after the RAM address counter counts.
Alternatively, the RAM address counter generates a scan end signal output when the count value is equal to a modulus of the internal counter.
The invention also provides a step scanning control method in the electromagnetic interference test receiver, based on the step scanning control device, the step scanning control device comprises: the system comprises an adjustment parameter register/gating controller, a data source selector, a state parameter RAM, a RAM address counter, an HSCAN generator, an interrupt manager, an interrupt register and a starter, and comprises the following steps:
1) resetting and adjusting a parameter register/gating controller, a data source selector, a state parameter RAM, an RAM address counter, an HSCAN generator, an interrupt manager and an interrupt register;
2) through a data bus and an address B, the CPU sequentially writes control parameters corresponding to all the stepping frequency points into a state parameter RAM; through data bus and address C, CPU writes the module of the internal counter into RAM address counter; through data bus and address D, CPU writes the module of the internal counter into HSCAN generator;
3) through a data bus and an address F, a CPU sends an instruction to start a starter, the starter generates an internal clock signal, and scanning starts;
4) under the action of an internal clock, the data source selector outputs data corresponding to an address 0 in the RAM to control each circuit of the receiver;
5) a counter in the HSCAN generator counts an internal clock, and when the count value is equal to the set module of the counter, the HSCAN generator generates an HSCAN signal; one path of the HSCAN signal is output outwards, and the other path of the HSCAN signal enters an RAM address counter for counting; after counting, the RAM address is changed from 0 to 1, and the data corresponding to the address 1 is output to the data source selector;
6) under the action of an internal clock, the data source selector outputs data corresponding to an address 1 in the RAM to control each circuit of the receiver;
7) in the scanning process, if no interruption is generated, the HSCAN generator continuously generates an HSCAN signal, the RAM address is continuously increased, and the control parameters corresponding to each frequency point are continuously output;
8) when the count value of the RAM address counter is equal to the set module of the counter, the RAM address counter generates scanning ending output interrupt output, and the scanning process is ended;
9) if an interrupt signal is received in the scanning process, the interrupt register registers the interrupt number to generate CPU interrupt, on one hand, the CPU is informed, and on the other hand, the interrupt manager is informed;
10) after receiving the CPU interrupt, the interrupt manager controls the HSCAN generator to enable a counter in the HSCAN generator to stop counting, and the scanning process is suspended;
11) after receiving the interrupt, the CPU reads the interrupt number registered in the interrupt register through the data bus and the address E;
12) according to the read interrupt number and the interrupt processing rule in the whole machine program, the CPU writes an adjusting parameter into an adjusting parameter register/gating controller through a data bus and an address A;
13) the adjusting parameter register/gating controller controls the data source of the data source selector to be data in the adjusting parameter register/gating controller; under the action of the internal clock, the data source selector outputs the control parameters to control each circuit of the receiver;
14) after the whole machine program waits for a certain time, the CPU sends out a reset signal C to reset the interrupt register; after receiving the reset signal, the interrupt register generates reset output to reset each circuit outside the receiver;
15) after the whole machine program waits for a certain time, if the interrupt register does not generate CPU interrupt any more, the CPU sends a reset signal B to reset the interrupt manager, and after the interrupt manager is reset, the HSCAN generator is controlled to enable a counter in the HSCAN generator to start counting, and the scanning process is continued;
after the whole machine program waits for a certain time, if the interrupt register generates CPU interrupt, repeatedly executing the steps 9) to 14);
16) if CPU interruption is generated in the process of adjusting the parameters for multiple times, the whole machine program selects to quit the scanning process, or selects to enable the interruption register not to respond to the external interruption by sending an interruption enabling signal through the CPU so as to continue scanning.
Optionally, the step 1) specifically includes: before scanning starts, the CPU sends out a reset signal A to reset the RAM address counter, the HSCAN generator and the adjusting parameter register/gating controller; after resetting, the data source of the data source selector is the data in the RAM; the CPU sends a reset signal B to reset the interrupt manager; the CPU sends out a reset signal C to reset the interrupt register; after receiving the reset signal, the interrupt register generates reset output to reset each circuit outside the receiver.
Optionally, during debugging, the CPU directly writes the parameters into the adjustment parameter register/gating controller through the data bus and the address a, and transmits the parameters to each circuit through the data source selector, thereby directly controlling each circuit.
The invention has the beneficial effects that:
(1) the interrupt processing process completely depending on the participation of the CPU is completed by the CPU and the step scanning control device together, and the CPU only interacts with the step scanning control device, so that the control workload of the CPU is reduced; meanwhile, the CPU does not need to recalculate the scanning parameters, so that the running efficiency of the program is improved;
(2) the modules which are relatively dispersed originally are integrated into a semi-automatic step scanning control device and matched with a CPU, so that the interrupt processing work can be efficiently completed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a control block diagram of a step-and-scan control device in an emi test receiver according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the existing scanning scheme of the electromagnetic interference test receiver, after the interruption is received, the CPU needs to recalculate the scanning parameters and reset each circuit, and then the stepping scanning process can be continued, and the adjustment process completely depends on the CPU, so that the control efficiency is low. The invention discloses a step-and-scan control device and method in an electromagnetic interference test receiver, wherein the interrupt processing process completely depending on the participation of a CPU in the past is completed by the CPU and the step-and-scan control device together, and the CPU only interacts with the step-and-scan control device, thereby reducing the control workload of the CPU.
As shown in fig. 1, a step-and-scan control apparatus in an electromagnetic interference test receiver of the present invention includes: the device comprises an adjustment parameter register/gating controller, a data source selector, a state parameter RAM, an HSCAN generator, an interrupt manager, an interrupt register and a starter, and has the capability of self-stopping and restorability in the step scanning process.
Adjusting parameter register/gating controller: and registering the adjustment parameters transmitted by the data bus and the switching state of the data source selector through the address A and the data bus.
The data source selector: and selecting a data source according to the on-off state registered by the adjustment parameter register/gating controller, outputting data of the data source under the action of a clock, and controlling each circuit of the receiver.
A state parameter RAM: and registering the scanning parameters corresponding to the stepping frequency points. The writing address and writing operation are completed by the CPU through the address B and the data bus; the read address is the count value of the RAM address counter, and the read operation is completed by the pulse generated after the RAM address counter counts.
RAM address counter: and counting the HSCAN signals, and generating a read pulse of the state parameter RAM after counting. The modulus of the internal counter transmitted from the data bus is registered through the address C and the data bus. When the count value is equal to the modulus of the internal counter, an end-of-scan signal output is generated.
HSCAN generator: the modulus of the internal counter transmitted from the data bus is registered through the address D and the data bus. The HSCAN signal is generated when the count value equals the modulus of the internal counter. The count enabling end of the internal counter of the HSCAN generator is controlled by the interrupt manager.
An interrupt manager: and after receiving the interrupt generated by the interrupt register, controlling an internal counter of the HSCAN generator to stop counting.
An interrupt register: after receiving external interrupt 1, interrupt 2, … … and interrupt N, registering an interrupt number and generating CPU interrupt; the registered interrupt number can be transmitted to the CPU through an address E and a data bus; after receiving the reset signal, the reset output signal is generated besides resetting the internal register.
A starter: through the address F and data bus, an internal clock signal is generated.
The working process of the step-and-scan control device is as follows:
1) before scanning starts, the CPU sends out a reset signal A to reset the RAM address counter, the HSCAN generator and the adjusting parameter register/gating controller. After resetting, the data source of the data source selector is the data in the RAM; sending a reset signal B to reset the interrupt manager; and sending a reset signal C to reset the interrupt register. After receiving the reset signal, the interrupt register generates reset output to reset each circuit outside the receiver.
2) Through a data bus and an address B, the CPU sequentially writes the calculated control parameters corresponding to each stepping frequency point into a state parameter RAM; through data bus and address C, CPU writes the module of the internal counter into RAM address counter; through the data bus and address D, the CPU writes the modulus of the internal counter to the HSCAN generator.
3) Through the data bus and address F, the CPU issues an instruction to start the initiator. The initiator generates an internal clock signal and the scan begins.
4) Under the action of the internal clock, the data source selector outputs data (i.e., control parameters) corresponding to address 0 in the RAM, and controls each circuit of the receiver.
5) A counter within the HSCAN generator counts the internal clock. The HSCAN generator generates a HSCAN signal when the count value equals the set modulo of the counter. One path of the HSCAN signal is output externally for signal processing and external output at the rear end of the receiver, and the other path of the HSCAN signal enters an RAM address counter for counting. After the count, the RAM address changes from 0 to 1, and data (control parameter) corresponding to the address 1 is output to the data source selector.
6) Under the action of the internal clock, the data source selector outputs data (control parameters) corresponding to address 1 in the RAM, and controls each circuit of the receiver.
7) If no interruption occurs in the scanning process, the HSCAN generator continuously generates HSCAN signals, the RAM address is continuously increased, and the control parameters corresponding to the frequency points are continuously output.
8) When the count value of the RAM address counter is equal to the modulus of the set counter, the RAM address counter generates a scanning end output interrupt output, and the scanning process is ended.
9) If an interrupt signal is received during the scan, an interrupt register registers an interrupt number, e.g., 1, 2, etc., generating a CPU interrupt, notifying the CPU on the one hand and the interrupt manager on the other hand.
10) After the interrupt manager receives the CPU interrupt, the interrupt manager controls the HSCAN generator to enable a counter in the HSCAN generator to stop counting, and the scanning process is suspended.
11) After receiving the interrupt, the CPU reads the interrupt number registered in the interrupt register through the data bus and the address E.
12) And according to the read interrupt number and the interrupt processing rule in the whole machine program, the CPU writes the adjustment parameters into the adjustment parameter register/gating controller through the data bus and the address A.
13) The adjusting parameter register/gating controller controls the data source of the data source selector to be data in the adjusting parameter register/gating controller; under the action of the internal clock, the data source selector outputs control parameters to control each circuit of the receiver.
14) After the whole machine program waits for a certain time (the waiting time is set aside for adjusting time for modules and circuits, the interrupt numbers are different, the waiting time is also different, and the specific waiting time is defined in the interrupt processing program), the CPU sends a reset signal C to reset the interrupt register. After receiving the reset signal, the interrupt register generates reset output to reset each circuit outside the receiver.
15) After the whole machine program waits for a certain time (the waiting time is to check whether the parameter adjustment achieves the effect), if the interrupt register does not generate CPU interrupt any more, the parameter adjustment achieves the effect, and the CPU sends a reset signal B to reset the interrupt manager. After the interrupt manager is reset, the HSCAN generator is controlled, so that a counter in the HSCAN generator starts counting, and the scanning process continues; but after the whole machine program waits for a certain time, if the interrupt register generates CPU interrupt, the parameter adjustment does not reach the effect, and the steps 9) to 14) are repeatedly executed.
16) If the parameter adjustment process is carried out for a plurality of times and CPU interruption is generated, the whole program can not only select to quit the scanning process, but also select to send an interruption enabling signal through the CPU so that the interruption register does not respond to external interruption any more, thereby achieving the aim of continuing scanning.
In addition, during debugging or other special purposes, the CPU can directly write parameters into the parameter adjusting register/gating controller through the data bus and the address A, and transmit the parameters to each circuit through the data source selector, so that the aim of directly controlling each circuit is fulfilled.
Compared with the scanning scheme in the prior art, the invention has the advantages that the interrupt processing process completely depending on the participation of the CPU is completed by the CPU and the step-and-scan control device together, and the CPU only interacts with the step-and-scan control device, so the control workload of the CPU is reduced; meanwhile, the CPU does not need to recalculate the scanning parameters, so that the running efficiency of the program is improved; in addition, the present invention integrates the modules into semi-automatic step scan controller to cooperate with CPU for high efficiency interruption processing.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (6)
1. A step-and-scan control apparatus in an electromagnetic interference test receiver, comprising: the system comprises an adjustment parameter register/gating controller, a data source selector, a state parameter RAM, an RAM address counter, an HSCAN generator, an interrupt manager, an interrupt register and a starter; wherein,
adjusting parameter register/gating controller: registering an adjusting parameter and a data source selector switch state transmitted by the data bus through the address A and the data bus;
the data source selector: selecting a data source according to the on-off state registered by the adjustment parameter register/gating controller, outputting data of the data source under the action of a clock, and controlling each circuit of the receiver;
a state parameter RAM: registering scanning parameters corresponding to each stepping frequency point, wherein the writing address and the writing operation of the scanning parameters are completed by a CPU through an address B and a data bus;
RAM address counter: counting the HSCAN signals, generating a read pulse of a state parameter RAM after counting, and registering a mode of an internal counter transmitted from a data bus through an address C and the data bus;
HSCAN generator: registering a mode of an internal counter transmitted by the data bus through the address D and the data bus, generating an HSCAN signal when a count value is equal to the mode of the internal counter, and controlling a counting enabling end of the internal counter of the HSCAN generator by an interrupt manager;
an interrupt manager: after receiving the interrupt generated by the interrupt register, controlling an internal counter of the HSCAN generator to stop counting;
an interrupt register: after receiving the external interrupt, registering an interrupt number and generating CPU interrupt; the registered interrupt number is transmitted to the CPU through an address E and a data bus; after receiving the reset signal, resetting the internal register to generate a reset output signal;
a starter: through the address F and data bus, an internal clock signal is generated.
2. The apparatus of claim 1, wherein the read address of the state parameter RAM is a count value of a RAM address counter, and the read operation is performed by a pulse generated after the count value of the RAM address counter.
3. The apparatus of claim 1, wherein the RAM address counter generates an end-of-scan signal output when the count value equals a modulo of the internal counter.
4. A step-and-scan control method in an electromagnetic interference test receiver is characterized in that based on a step-and-scan control device, the step-and-scan control device comprises: the system comprises an adjustment parameter register/gating controller, a data source selector, a state parameter RAM, a RAM address counter, an HSCAN generator, an interrupt manager, an interrupt register and a starter, and comprises the following steps:
1) resetting and adjusting a parameter register/gating controller, a data source selector, a state parameter RAM, an RAM address counter, an HSCAN generator, an interrupt manager and an interrupt register;
2) through a data bus and an address B, the CPU sequentially writes control parameters corresponding to all the stepping frequency points into a state parameter RAM; through data bus and address C, CPU writes the module of the internal counter into RAM address counter; through data bus and address D, CPU writes the module of the internal counter into HSCAN generator;
3) through a data bus and an address F, a CPU sends an instruction to start a starter, the starter generates an internal clock signal, and scanning starts;
4) under the action of an internal clock, the data source selector outputs data corresponding to an address 0 in the RAM to control each circuit of the receiver;
5) a counter in the HSCAN generator counts an internal clock, and when the count value is equal to the set module of the counter, the HSCAN generator generates an HSCAN signal; one path of the HSCAN signal is output outwards, and the other path of the HSCAN signal enters an RAM address counter for counting; after counting, the RAM address is changed from 0 to 1, and the data corresponding to the address 1 is output to the data source selector;
6) under the action of an internal clock, the data source selector outputs data corresponding to an address 1 in the RAM to control each circuit of the receiver;
7) in the scanning process, if no interruption is generated, the HSCAN generator continuously generates an HSCAN signal, the RAM address is continuously increased, and the control parameters corresponding to each frequency point are continuously output;
8) when the count value of the RAM address counter is equal to the set module of the counter, the RAM address counter generates scanning ending output interrupt output, and the scanning process is ended;
9) if an interrupt signal is received in the scanning process, the interrupt register registers the interrupt number to generate CPU interrupt, on one hand, the CPU is informed, and on the other hand, the interrupt manager is informed;
10) after receiving the CPU interrupt, the interrupt manager controls the HSCAN generator to enable a counter in the HSCAN generator to stop counting, and the scanning process is suspended;
11) after receiving the interrupt, the CPU reads the interrupt number registered in the interrupt register through the data bus and the address E;
12) according to the read interrupt number and the interrupt processing rule in the whole machine program, the CPU writes an adjusting parameter into an adjusting parameter register/gating controller through a data bus and an address A;
13) the adjusting parameter register/gating controller controls the data source of the data source selector to be data in the adjusting parameter register/gating controller; under the action of the internal clock, the data source selector outputs the control parameters to control each circuit of the receiver;
14) after the whole machine program waits for a certain time, the CPU sends out a reset signal C to reset the interrupt register; after receiving the reset signal, the interrupt register generates reset output to reset each circuit outside the receiver;
15) after the whole machine program waits for a certain time, if the interrupt register does not generate CPU interrupt any more, the CPU sends a reset signal B to reset the interrupt manager, and after the interrupt manager is reset, the HSCAN generator is controlled to enable a counter in the HSCAN generator to start counting, and the scanning process is continued;
after the whole machine program waits for a certain time, if the interrupt register generates CPU interrupt, repeatedly executing the steps 9) to 14);
16) if CPU interruption is generated in the process of adjusting the parameters for multiple times, the whole machine program selects to quit the scanning process, or selects to enable the interruption register not to respond to the external interruption by sending an interruption enabling signal through the CPU so as to continue scanning.
5. The step-and-scan control method in an emi test receiver according to claim 4, wherein the step 1) is specifically: before scanning starts, the CPU sends out a reset signal A to reset the RAM address counter, the HSCAN generator and the adjusting parameter register/gating controller; after resetting, the data source of the data source selector is the data in the RAM; the CPU sends a reset signal B to reset the interrupt manager; the CPU sends out a reset signal C to reset the interrupt register; after receiving the reset signal, the interrupt register generates reset output to reset each circuit outside the receiver.
6. The step-and-scan control method in an emi test receiver of claim 4 wherein during debugging, the CPU writes parameters directly into the tuning parameter register/gating controller via the data bus and address a, and passes parameters to the circuits via the data source selector to directly control the circuits.
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| CN103560839A (en) * | 2013-10-28 | 2014-02-05 | 中国电子科技集团公司第四十一研究所 | Method and device for realizing high-speed scanning of electromagnetic radiation interference testing receiver |
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| US5548762A (en) * | 1992-01-30 | 1996-08-20 | Digital Equipment Corporation | Implementation efficient interrupt select mechanism |
| CN103560839A (en) * | 2013-10-28 | 2014-02-05 | 中国电子科技集团公司第四十一研究所 | Method and device for realizing high-speed scanning of electromagnetic radiation interference testing receiver |
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| 张志等: "扫频接收机中数字扫描控制器设计", 《应用天地》 * |
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