CN104485898A - Debugging method and system of double-channel power amplifier - Google Patents
Debugging method and system of double-channel power amplifier Download PDFInfo
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Abstract
The invention discloses a debugging method and system of a double-channel power amplifier. The method comprises the following steps: acquiring the index information and state information of the double-channel power amplifier; regulating the performance parameter of a first single channel into a parameter range corresponding to the index information according to the state information and the index information; switching the double-channel power amplifier from a normal mode to an internal mode through a DPD (Digital Pre-Distortion) control bus of the double-channel power amplifier; authorizing the control right of a programmable logical gate array of the first single channel to a DPD offset chip to a programmable logical gate array of a second single channel to realize channel switching; regulating the performance parameter of the second single channel into the parameter range corresponding to the index information according to the state information and the index information. By adopting the debugging method and system, the two single channels of the double-channel power amplifier can be rapidly and effectively regulated into the parameter range corresponding to the index information, so that debugging of the double-channel power amplifier is realized.
Description
[technical field]
The present invention relates to communication technical field, particularly relate to a kind of adjustment method and system of binary channels power amplifier.
[background technology]
Along with the development of wireless communication technology, 3G network construction is carried out steadily, and the pilot work of 4G network also launches on a large scale, and high-speed, high-quality radio communication coverage rate is more and more higher.Simultaneously, linear, the index such as efficiency, cost of mobile communication equipment more and more cause the attention of industry, and product of the future and technology also constantly to be proposed by people and perfect, and therefore the application of binary channels power amplifier has become a kind of trend.
Binary channels power amplifier achieves double-input double-output compared with traditional single power amplifier product, not only effectively improves power efficiency, more increases instant bandwidth, reduces equipment cost, meet the application model that market is novel.Along with the expansion of instant bandwidth and the integrated application of numerous technology, the complexity of binary channels power amplifier control flow process is improved, needs to resolve interior data and regulate and control, and verify its long-time running stability.
And existing adjustment method is debugged mainly for the radio-frequency performance of single power amplifier, and realized the object of checking by qualified rate, do not support that two paths controls separately debugging.
[summary of the invention]
Based on this, be necessary not support that two paths controls debugging problem separately for existing adjustment method, a kind of adjustment method and system of binary channels power amplifier are provided.
An adjustment method for binary channels power amplifier, comprises the following steps:
Gather the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information;
According to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information;
Reset the DPD control bus of described binary channels power amplifier, and described binary channels power amplifier is switched to internal schema by normal mode;
Described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge;
According to described second state information and described indication information, described second single pass performance parameter is regulated and controled in parameter area corresponding to described indication information.
A debug system for binary channels power amplifier, comprising:
Information acquisition module, for gathering the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information;
First debugging module, for according to described first state information and described indication information, regulates and controls in parameter area corresponding to described indication information by described first single pass performance parameter;
Mode reset module, for the DPD control bus of the described binary channels power amplifier that resets, is switched to internal schema by described binary channels power amplifier by normal mode;
Channel switching module, for described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge;
Second debugging module, for according to described second state information and described indication information, regulates and controls described second single pass performance parameter in parameter area corresponding to described indication information.
The adjustment method of above-mentioned binary channels power amplifier and system, can described first single pass performance parameter be regulated and controled after in the parameter area corresponding to described indication information, reset the DPD control bus of described binary channels power amplifier, and described binary channels power amplifier is switched to internal schema by normal mode; Described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge; According to described second state information and described indication information, described second single pass performance parameter is regulated and controled in parameter area corresponding to described indication information, fast and effectively two of binary channels power amplifier single channels can be regulated and controled in parameter area corresponding to described indication information, realize the debugging to binary channels power amplifier.
[accompanying drawing explanation]
Fig. 1 is the structural representation of the implementation environment of the adjustment method of the binary channels power amplifier of the embodiment of the present invention;
Fig. 2 is the schematic flow sheet of adjustment method first execution mode of binary channels power amplifier of the present invention;
Fig. 3 is the schematic flow sheet of adjustment method second execution mode of binary channels power amplifier of the present invention;
Fig. 4 is the structural representation of debug system first execution mode of binary channels power amplifier of the present invention;
Fig. 5 is the structural representation of debug system second execution mode of binary channels power amplifier of the present invention.
[embodiment]
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to Fig. 1, Fig. 1 is the structural representation of the implementation environment of the adjustment method of the binary channels power amplifier of the embodiment of the present invention.
Implementation environment shown in Fig. 1 is for realizing the adjustment method of the binary channels power amplifier described in any embodiment of the present invention or execution mode, comprise debugging server 2020, testing apparatus 2040, binary channels power amplifier 2060, testing apparatus 2040 is connected by wireless network or cable network with debugging server 2020 respectively with binary channels power amplifier 2060.Wherein, debugging server 2020 can comprise at least one in the terminal equipments such as desktop computer, notebook, personal digital assistant, smart phone, panel computer, portable electronic device, is equiped with the application program of the adjustment method for realizing binary channels power amplifier.
As shown in Figure 1, debugging server 2020 carries out data interaction respectively with testing apparatus 2040 and binary channels power amplifier 2060.
Debugging server 2020 pairs of binary channels power amplifiers 2060 carry out debugging control, to gather the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information, according to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information, reset the DPD control bus of described binary channels power amplifier, and described binary channels power amplifier is switched to internal schema by normal mode.Described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge.According to described second state information and described indication information, described second single pass performance parameter is regulated and controled in parameter area corresponding to described indication information.
Further, the performance parameter of two of binary channels server 2060 single channels (the first single channel and the second single channel) all regulates and controls after in parameter area corresponding to described indication information by debugging server 2020, power supply control is carried out to testing apparatus 2040, make external power source then as the direct power supply of testing apparatus 2040, indirectly for binary channels power amplifier 2060 provides voltage.Debugging server 2020 pairs of testing apparatuss 2040 carry out testing and control, to obtain detecting information and testing standard, and detecting information and testing standard are loaded into testing apparatus 2040, by testing apparatus, power amplifier simulation test is carried out to described binary channels power amplifier, test described binary channels power amplifier and whether meet described testing standard, if meet, then stop the debugging to binary channels power amplifier 2060.
Further, the indication information in debugging control can comprise monitor control index, radio-frequency (RF) index and numerical index.
Can by the performance fast debugging of binary channels power amplifier 2060 to optimum state by implementation environment shown in Fig. 1.
Refer to Fig. 2, Fig. 2 is the schematic flow sheet of adjustment method first execution mode of binary channels power amplifier of the present invention.
The adjustment method of the described binary channels power amplifier of present embodiment, preferably at debugging server end, can comprise the following steps:
Step S201, gathers the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information.
Step S202, according to described first state information and described indication information, regulates and controls described first single pass performance parameter in parameter area corresponding to described indication information.
Step S203, the DPD control bus of the described binary channels power amplifier that resets, is switched to internal schema by described binary channels power amplifier by normal mode.
Step S204, licenses to described second single pass programmable gate array by described first single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge.
Step S205, according to described second state information and described indication information, regulates and controls described second single pass performance parameter in parameter area corresponding to described indication information.
Present embodiment, can described first single pass performance parameter be regulated and controled after in the parameter area corresponding to described indication information, reset the DPD control bus of described binary channels power amplifier, and described binary channels power amplifier is switched to internal schema by normal mode; Described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge; According to described second state information and described indication information, described second single pass performance parameter is regulated and controled in parameter area corresponding to described indication information, fast and effectively two of binary channels power amplifier single channels can be regulated and controled in parameter area corresponding to described indication information, realize the debugging to binary channels power amplifier.
Wherein, for step S201, preferably directly read described indication information, described first single pass first state information and described second single pass second state information from binary channels power amplifier inside by debugging server.In other embodiments, debugging server also obtains described indication information, described first single pass first state information and described second single pass second state information indirectly by testing apparatus or other communication equipments.
Preferably, described first single pass first state information and described second single pass second state information comprise the internal state information such as the first single channel and the second single pass power amplifier state, power, alarm status, temperature, software version information respectively.
In one embodiment, before the step gathering the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information, can in advance binary channels power amplifier be established a communications link with debugging server and testing apparatus simultaneously.
For step S202, preferably, described indication information can comprise monitor control index, radio-frequency (RF) index and numerical index.
Further, described monitor control index can comprise indication information corresponding with monitoring function parameters such as power amplifier state, temperature, power, software versions respectively.
Described radio-frequency (RF) index can comprise indication information corresponding with radio-frequency enabled parameters such as grid voltage, gain, ATT respectively.
Described numerical index can comprise indication information corresponding with digital function parameters such as inphase quadrature gain, peak to average auto level control, DPD (Digital Pre-Distortion, digital pre-distortion) running statuses respectively.
In one embodiment, according to described first state information and described indication information, described first single pass performance parameter is regulated and controled and comprises the following steps to the step in parameter area corresponding to described indication information:
Detect the request that described binary channels power amplifier is debugged.
If described request detected, then according to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information.
If described request do not detected, then with the first single pass first state information and described second single pass second state information described in the time interval repeated acquisition preset.
The present embodiment, debugs single channel after receiving debug request again, otherwise repeats to upgrade each single pass state information, can ensure to collect correct effective state information.
Preferably, the described default time interval can be 1 minute.Also can be other times value.
In other embodiments, also determine whether to perform according to described first state information and described indication information by this area other technologies means, described first single pass performance parameter is regulated and controled to the operation in parameter area corresponding to described indication information.As: the regulation and control time can be set, when meeting the described regulation and control time, according to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information, when not meeting the described regulation and control time, with the first single pass first state information described in described default time interval repeated acquisition and described second single pass second state information.
In another embodiment, according to described first state information and described indication information, described first single pass performance parameter is regulated and controled and comprises the following steps to the step in parameter area corresponding to described indication information:
Described first single pass power amplifier performance parameter is regulated and controled in parameter area corresponding to the monitor control index in described indication information.
Described first single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information.
Described first single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information.
Wherein, described digital performance parameter can comprise inphase quadrature gain, peak to average auto level control and digital pre-distortion running status.Described radio-frequency performance parameter can comprise grid voltage, gain and decay.Described power amplifier performance parameter can comprise power amplifier state, temperature and threshold coefficient.
Preferably, described first single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information, radio-frequency performance parameter can be made to meet the initial adjustment index of power, linear, electric current.Described first single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information, further fine setting can be realized.
Further, when any one in corresponding power amplifier state, temperature and threshold coefficient carries out the regulation and control of power amplifier performance parameter, can query warning state, when inquiring alarm status, as gain alarm, then first obtain gain alarm thresholding, then adjust gain, make current gain lower than thresholding, then inquire about current gain alarm and whether recover, as recovered, illustrate that gain is normal.
Obtaining temperature, mainly due to some performance index of power amplifier, as grid voltage, gain, ALC etc. affect by temperature effect, for meeting index, when variations in temperature is obvious, it need be compensated, i.e. temperature compensation.
Monitoring normal regulating scope is due to indices difference, concrete scope is not identical yet, mainly based on current queries value, and adjust up or down with certain stepping on this basis, value after adjustment is not higher than threshold value, power amplifier state simultaneously, such as whether alarm status etc. also successfully indicate as adjustment.
When any one in corresponding grid voltage, gain and decay carries out the regulation and control of radio-frequency performance parameter, the same Gain tuning of adjustment process of grid voltage, attenuation effect is similar with gain, and namely gain is that forward increases, and decay is forward reduction.This part belongs to radio frequency part and regulates, and regulates primarily of single-chip microcomputer and minimum supervisory control system.
When any one in corresponding inphase quadrature gain, peak to average auto level control and digital pre-distortion running status carries out the regulation and control of digital performance parameter, IQ gain, peak to average ALC and DPD running status, mainly as regulating use further, this part belongs to numerical portion and regulates by FPGA and programmable gate array adjustment.When DPD running status exception or when there is digital alarm, need adjust respective digital parameter, wherein IQ gain, peak to average ALC etc. are stored in FPGA register, need be changed by read-write register value.
Be Digital Pre-Distortion, i.e. digital pre-distortion for step S203, DPD.The pattern of described binary channels power amplifier can comprise normal mode, internal schema and test pattern.
For step S204, described binary channels power amplifier comprises two programmable gate arrays, corresponding two single channels (the first single channel and the second single channel) respectively, one of them programmable gate array is main programmable gate array, another is from programmable gate array, and main programmable gate array has control DPD being offseted to chip.
Preferably, programmable gate array is that to offset chip be OP chip for FPGA, DPD.Described OP chip card I be OP6180 chip.
In one embodiment, described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, and the step realizing passage bridge comprises the following steps:
The control of described first single pass FPGA to OP chip is licensed to described second single pass FPGA, realizes passage bridge.
After licensing to described second single pass FPGA to the control of OP chip, described second single pass FPGA is main FPGA, effective to OP chip controls.
For step S205, interchangeable to the debugging order of described first single channel and described second channel, can random selecting first debug in described first single channel and described second single channel any one.
In one embodiment, according to described second state information and described indication information, described second single pass performance parameter is regulated and controled and comprises the following steps to the step in parameter area corresponding to described indication information:
Described second single pass power amplifier performance parameter is regulated and controled in parameter area corresponding to the monitor control index in described indication information.
Described second single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information.
Described second single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information.
Refer to Fig. 3, Fig. 3 is the schematic flow sheet of adjustment method second execution mode of binary channels power amplifier of the present invention.
The adjustment method of the binary channels power amplifier described in present embodiment and the difference of the first execution mode are: according to described second state information and described indication information, described second single pass performance parameter is regulated and controled to after the step in parameter area corresponding to described indication information, further comprising the steps of:
Step S301, obtains detecting information and testing standard.
Step S302, carries out power amplifier simulation test according to described detecting information to described binary channels power amplifier, generates test data.
Step S303, judges whether described test data meets described testing standard.
Step S304, if meet, then stops the debugging to described binary channels power amplifier.
Present embodiment, after completing two single pass debugging to described binary channels power amplifier, can carry out simulation test to described binary channels power amplifier, judges whether to meet testing standard, confirms the validity of debug results further.
Preferably, described detecting information comprises the information corresponding with project to be measured, and described project to be measured comprises the test event of the performance parameter of the corresponding described binary channels power amplifiers such as alarm test, power test, temperature test.Described testing standard comprises the canonical parameter scope of corresponding each project to be measured, as power standard scope, temperature standard scope etc.
Further, according to described detecting information, power amplifier simulation test is carried out to described binary channels power amplifier, described binary channels power amplifier can be tested and whether meet described testing standard, also can be reconfigured the interface parameters of binary channels power amplifier according to the instruction of debugging server by testing apparatus, described binary channels power amplifier is made to reach emulation mode, alarm simulation is carried out to described binary channels power amplifier, changed power is simulated, the simulation test that the test events such as temperature anomaly simulation are corresponding, and then detect inter-process mechanism and the self-healing function of described binary channels power amplifier, after simulation test, debugging server obtains test result, and test result and testing standard are compared, if meet described testing standard, then stop the debugging to described binary channels power amplifier.
Further, if test result does not meet described testing standard, then repeat the above step S201 to step S205.
Refer to Fig. 4, Fig. 4 is the structural representation of debug system first execution mode of binary channels power amplifier of the present invention.
The debug system of the described binary channels power amplifier of present embodiment preferably can be arranged on debugging server end, information acquisition module 100, first debugging module 200, mode reset module 300, channel switching module 400 and the second debugging module 500 can be comprised, wherein:
Information acquisition module 100, for gathering the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information.
First debugging module 200, for according to described first state information and described indication information, regulates and controls described first single pass performance parameter in parameter area corresponding to described indication information.
Mode reset module 300, for the DPD control bus of the described binary channels power amplifier that resets, is switched to internal schema by described binary channels power amplifier by normal mode.
Channel switching module 400, for described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge.
Second debugging module 500, for according to described second state information and described indication information, regulates and controls described second single pass performance parameter in parameter area corresponding to described indication information.
Present embodiment, can described first single pass performance parameter be regulated and controled after in the parameter area corresponding to described indication information, reset the DPD control bus of described binary channels power amplifier, and described binary channels power amplifier is switched to internal schema by normal mode; Described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge; According to described second state information and described indication information, described second single pass performance parameter is regulated and controled in parameter area corresponding to described indication information, fast and effectively two of binary channels power amplifier single channels can be regulated and controled in parameter area corresponding to described indication information, realize the debugging to binary channels power amplifier.
Wherein, for information acquisition module 100, preferably directly read described indication information, described first single pass first state information and described second single pass second state information from binary channels power amplifier inside by debugging server.In other embodiments, debugging server also obtains described indication information, described first single pass first state information and described second single pass second state information indirectly by testing apparatus or other communication equipments.
Preferably, described first single pass first state information and described second single pass second state information comprise the internal state information such as the first single channel and the second single pass power amplifier state, power, alarm status, temperature, software version information respectively.
In one embodiment, before the step gathering the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information, can in advance binary channels power amplifier be established a communications link with debugging server and testing apparatus simultaneously.
For the first debugging module 200, preferably, described indication information can comprise monitor control index, radio-frequency (RF) index and numerical index.
Further, described monitor control index can comprise indication information corresponding with monitoring function parameters such as power amplifier state, temperature, power, software versions respectively.
Described radio-frequency (RF) index can comprise indication information corresponding with radio-frequency enabled parameters such as grid voltage, gain, ATT respectively.
Described numerical index can comprise indication information corresponding with digital function parameters such as inphase quadrature gain (IQ gain), peak to average auto level control (peak to average ALC), DPD (Digital Pre-Distortion, digital pre-distortion) running statuses respectively.
In one embodiment, the first debugging module 200 can be used for:
Detect the request that described binary channels power amplifier is debugged.
If described request detected, then according to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information.
If described request do not detected, then announcement information acquisition module is with the first single pass first state information and described second single pass second state information described in the time interval repeated acquisition preset.
The present embodiment, debugs single channel after receiving debug request again, otherwise repeats to upgrade each single pass state information, can ensure to collect correct effective state information.
In another embodiment, the first debugging module 200 also can be further used for:
Described first single pass power amplifier performance parameter is regulated and controled in parameter area corresponding to the monitor control index in described indication information.
Described first single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information.
Described first single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information.
Wherein, described digital performance parameter can comprise inphase quadrature gain, peak to average auto level control and digital pre-distortion running status.Described radio-frequency performance parameter can comprise grid voltage, gain and decay.Described power amplifier performance parameter can comprise power amplifier state, temperature and threshold coefficient.
Preferably, described first single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information, radio-frequency performance parameter can be made to meet the initial adjustment index of power, linear, electric current.Described first single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information, further fine setting can be realized.
Further, when any one in corresponding power amplifier state, temperature and threshold coefficient carries out the regulation and control of power amplifier performance parameter, can query warning state, when inquiring alarm status, as gain alarm, then first obtain gain alarm thresholding, then adjust gain, make current gain lower than thresholding, then inquire about current gain alarm and whether recover, as recovered, illustrate that gain is normal.
Obtaining temperature, mainly due to some performance index of power amplifier, as grid voltage, gain, ALC etc. affect by temperature effect, for meeting index, when variations in temperature is obvious, it need be compensated, i.e. temperature compensation.
Monitoring normal regulating scope is due to indices difference, concrete scope is not identical yet, mainly based on current queries value, and adjust up or down with certain stepping on this basis, value after adjustment is not higher than threshold value, power amplifier state simultaneously, such as whether alarm status etc. also successfully indicate as adjustment.
When any one in corresponding grid voltage, gain and decay carries out the regulation and control of radio-frequency performance parameter, the same Gain tuning of adjustment process of grid voltage, attenuation effect is similar with gain, and namely gain is that forward increases, and decay is forward reduction.This part belongs to radio frequency part and regulates, and regulates primarily of single-chip microcomputer and minimum supervisory control system.
When any one in corresponding inphase quadrature gain, peak to average auto level control and digital pre-distortion running status carries out the regulation and control of digital performance parameter, IQ gain, peak to average ALC and DPD running status, mainly as regulating use further, this part belongs to numerical portion and regulates by FPGA and programmable gate array adjustment.When DPD running status exception or when there is digital alarm, need adjust respective digital parameter, wherein IQ gain, peak to average ALC etc. are stored in FPGA register, need be changed by read-write register value.
Be Digital Pre-Distortion, i.e. digital pre-distortion for mode reset module 300, DPD.The pattern of described binary channels power amplifier can comprise normal mode, internal schema and test pattern.
For channel switching module 400, described binary channels power amplifier comprises two programmable gate arrays, corresponding two single channels (the first single channel and the second single channel) respectively, one of them programmable gate array is main programmable gate array, another is from programmable gate array, and main programmable gate array has control DPD being offseted to chip.
Preferably, programmable gate array is that to offset chip be OP chip for FPGA, DPD.Described OP chip card I be OP6180 chip.
In one embodiment, channel switching module 400 also can be used for:
The control of described first single pass FPGA to OP chip is licensed to described second single pass FPGA, realizes passage bridge.
After licensing to described second single pass FPGA to the control of OP chip, described second single pass FPGA is main FPGA, effective to OP chip controls.
For the second debugging module 500, interchangeable to the debugging order of described first single channel and described second channel, can random selecting first debug in described first single channel and described second single channel any one.
In one embodiment, the second debugging module 500 also can be used for:
Described second single pass power amplifier performance parameter is regulated and controled in parameter area corresponding to the monitor control index in described indication information.
Described second single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information.
Described second single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information.
Refer to Fig. 5, Fig. 5 is the structural representation of debug system second execution mode of binary channels power amplifier of the present invention.
The debug system of the binary channels power amplifier described in present embodiment and the difference of the first execution mode are: also comprise test module 600, for:
Obtain detecting information and testing standard.
According to described detecting information, power amplifier simulation test is carried out to described binary channels power amplifier, generate test data.
Judge whether described test data meets described testing standard.
If meet, then stop the debugging to described binary channels power amplifier.
Present embodiment, after completing two single pass debugging to described binary channels power amplifier, can carry out simulation test to described binary channels power amplifier, judges whether to meet testing standard, confirms the validity of debug results further.
Preferably, described detecting information comprises the information corresponding with project to be measured, and described project to be measured comprises the test event of the performance parameter of the corresponding described binary channels power amplifiers such as alarm test, power test, temperature test.Described testing standard comprises the canonical parameter scope of corresponding each project to be measured, as power standard scope, temperature standard scope etc.
Further, test module 600 carries out power amplifier simulation test according to described detecting information to described binary channels power amplifier, described binary channels power amplifier can be tested and whether meet described testing standard, test module 600 controls testing apparatus reconfigures binary channels power amplifier interface parameters according to the instruction of debugging server, described binary channels power amplifier is made to reach emulation mode, alarm simulation is carried out to described binary channels power amplifier, changed power is simulated, the simulation test that the test events such as temperature anomaly simulation are corresponding, and then detect inter-process mechanism and the self-healing function of described binary channels power amplifier, after simulation test, the test module 600 of debugging server obtains test result, and test result and testing standard are compared, if meet described testing standard, then stop the debugging to described binary channels power amplifier.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (11)
1. an adjustment method for binary channels power amplifier, is characterized in that, comprises the following steps:
Gather the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information;
According to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information;
Reset the DPD control bus of described binary channels power amplifier, and described binary channels power amplifier is switched to internal schema by normal mode;
Described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge;
According to described second state information and described indication information, described second single pass performance parameter is regulated and controled in parameter area corresponding to described indication information.
2. the adjustment method of binary channels power amplifier according to claim 1, it is characterized in that, according to described first state information and described indication information, described first single pass performance parameter is regulated and controled and comprises the following steps to the step in parameter area corresponding to described indication information:
Detect the request that described binary channels power amplifier is debugged;
If described request detected, then according to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information;
If described request do not detected, then with the first single pass first state information and described second single pass second state information described in the time interval repeated acquisition preset.
3. the adjustment method of binary channels power amplifier according to claim 1, it is characterized in that, according to described first state information and described indication information, described first single pass performance parameter is regulated and controled and comprises the following steps to the step in parameter area corresponding to described indication information:
Described first single pass power amplifier performance parameter is regulated and controled in parameter area corresponding to the monitor control index in described indication information;
Described first single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information;
Described first single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information.
4. the adjustment method of binary channels power amplifier according to claim 3, is characterized in that, described digital performance parameter comprises inphase quadrature gain, peak to average auto level control and digital pre-distortion running status.
5. the adjustment method of binary channels power amplifier according to claim 3, is characterized in that, described radio-frequency performance parameter comprises grid voltage, gain and decay.
6. the adjustment method of binary channels power amplifier according to claim 3, is characterized in that, described power amplifier performance parameter comprises power amplifier state, temperature and threshold coefficient.
7. the adjustment method of binary channels power amplifier as claimed in any of claims 1 to 6, it is characterized in that, according to described second state information and described indication information, described second single pass performance parameter is regulated and controled to after the step in parameter area corresponding to described indication information, further comprising the steps of:
Obtain detecting information and testing standard;
According to described detecting information, power amplifier simulation test is carried out to described binary channels power amplifier, generate test data;
Judge whether described test data meets described testing standard;
If meet, then stop the debugging to described binary channels power amplifier.
8. a debug system for binary channels power amplifier, is characterized in that, comprising:
Information acquisition module, for gathering the indication information of binary channels power amplifier, the first single pass first state information and the second single pass second state information;
First debugging module, for according to described first state information and described indication information, regulates and controls in parameter area corresponding to described indication information by described first single pass performance parameter;
Mode reset module, for the DPD control bus of the described binary channels power amplifier that resets, is switched to internal schema by described binary channels power amplifier by normal mode;
Channel switching module, for described first single pass programmable gate array is licensed to described second single pass programmable gate array to the control that DPD offsets chip, realizes passage bridge;
Second debugging module, for according to described second state information and described indication information, regulates and controls described second single pass performance parameter in parameter area corresponding to described indication information.
9. the debug system of binary channels power amplifier according to claim 8, is characterized in that, described first debugging module also for:
Detect the request that described binary channels power amplifier is debugged;
If described request detected, then according to described first state information and described indication information, described first single pass performance parameter is regulated and controled in parameter area corresponding to described indication information;
If described request do not detected, then notify that described information acquisition module is with the first single pass first state information and described second single pass second state information described in the time interval repeated acquisition preset.
10. the debug system of binary channels power amplifier according to claim 8, is characterized in that, described first debugging module also for:
Described first single pass power amplifier performance parameter is regulated and controled in parameter area corresponding to the monitor control index in described indication information;
Described first single pass radio-frequency performance parameter is regulated and controled in parameter area corresponding to the radio-frequency (RF) index in described indication information;
Described first single pass digital performance parameter is regulated and controled in parameter area corresponding to the numerical index in described indication information.
The debug system of the binary channels power amplifier in 11. according to Claim 8 to 10 described in any one, is characterized in that, also comprise test module, for:
Obtain detecting information and testing standard;
According to described detecting information, power amplifier simulation test is carried out to described binary channels power amplifier, generate test data;
Judge whether described test data meets described testing standard;
If meet, then stop the debugging to described binary channels power amplifier.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114415778A (en) * | 2022-01-14 | 2022-04-29 | 中国电子科技集团公司第十研究所 | Automatic debugging method for ALC loop parameters |
| CN114839514A (en) * | 2022-07-04 | 2022-08-02 | 杭州加速科技有限公司 | Dynamic optimization method and system for chip test engineering |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201425611Y (en) * | 2009-04-14 | 2010-03-17 | 海华科技股份有限公司 | Radio frequency performance test structure with electronic switching function |
| US20100097730A1 (en) * | 2008-10-16 | 2010-04-22 | Tdk Corporation | Spin high-frequency mixer and method of manufacture thereof |
| CN103617121A (en) * | 2013-12-09 | 2014-03-05 | 北京京航计算通讯研究所 | Method for building AD/DA interface fault model on basis of NI platform |
-
2014
- 2014-12-10 CN CN201410756835.XA patent/CN104485898B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100097730A1 (en) * | 2008-10-16 | 2010-04-22 | Tdk Corporation | Spin high-frequency mixer and method of manufacture thereof |
| CN201425611Y (en) * | 2009-04-14 | 2010-03-17 | 海华科技股份有限公司 | Radio frequency performance test structure with electronic switching function |
| CN103617121A (en) * | 2013-12-09 | 2014-03-05 | 北京京航计算通讯研究所 | Method for building AD/DA interface fault model on basis of NI platform |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114415778A (en) * | 2022-01-14 | 2022-04-29 | 中国电子科技集团公司第十研究所 | Automatic debugging method for ALC loop parameters |
| CN114415778B (en) * | 2022-01-14 | 2023-06-27 | 中国电子科技集团公司第十研究所 | ALC loop parameter automatic debugging method |
| CN114839514A (en) * | 2022-07-04 | 2022-08-02 | 杭州加速科技有限公司 | Dynamic optimization method and system for chip test engineering |
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