CN104485295A - Wafer level packaging method - Google Patents
Wafer level packaging method Download PDFInfo
- Publication number
- CN104485295A CN104485295A CN201410784542.2A CN201410784542A CN104485295A CN 104485295 A CN104485295 A CN 104485295A CN 201410784542 A CN201410784542 A CN 201410784542A CN 104485295 A CN104485295 A CN 104485295A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- ball lower
- wafer
- packaging method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a wafer level packaging method. The method comprises the following steps: providing a substrate, wherein a conductive metal cushion is arranged on the surface of the substrate; forming a metal core which protrudes from the surface of the substrate on the conductive metal cushion; wrapping the top surface and the side surface of the metal core with an under bump metallization layer; forming a bump structure on the surface of the under bump metallization layer. The wafer level packaging method has the benefits that the combination strength of the bump structure and the under bump metallization layer is improved, and the stability of the structures of the bump structure and the under bump metallization layer is relatively stable, so that separation is greatly avoided, and as a result, the mechanical stability of the packaging structure is raised, and the heat conductivity and the electric conductivity of the packaging structure are improved.
Description
Technical field
The present invention relates to field of semiconductor package, be specifically related to a kind of wafer-level packaging method.
Background technology
On conventional art, the connection of IC chip and external circuit is realized by the mode of metal lead wire bonding (WireBonding).
Along with the expansion with footprint of reducing of IC chip feature sizes, Wire Bonding Technology is no longer applicable.Crystal wafer chip dimension encapsulation (Wafer Level Chip Scale Packaging, WLCSP) technology is that after carrying out packaging and testing to full wafer wafer, cutting obtains the technology of single finished product chip again, the chip size after encapsulation and nude film completely the same.Crystal wafer chip dimension encapsulation technology has thoroughly overturned the pattern of conventional package as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic Leadless Chip Carrier), has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.Chip size after the encapsulation of crystal wafer chip dimension encapsulation technology reaches highly microminiaturized, and chip cost significantly reduces along with the reduction of chip size and the increase of wafer size.Crystal wafer chip dimension encapsulation technology be IC can be designed, wafer manufacture, packaging and testing, the technology that integrates, be the focus in current encapsulation field and the trend of future development.
With reference to the structural representation that figure 1 is the encapsulating structure of crystal wafer chip dimension of the prior art, comprising: Semiconductor substrate 1; Be positioned at the conducting metal pad pad 11 on described Semiconductor substrate 1 surface, be positioned at the ball lower metal layer 3 on described conducting metal pad pad 11, be positioned at the bump structure 2 on described ball lower metal layer 3.
But this bump structure 2 is little with the contact area of ball lower metal layer 3, and this makes the bond strength of whole encapsulating structure lower, easily causes the mechanical stability of encapsulating structure to reduce.Such as, there is bump structure 2 sometimes and depart from situation about even coming off with ball lower metal layer 3 part, while the conductivity performance of whole encapsulating structure and heat-conductive characteristic also can be affected.
Therefore, how to improve the bond strength between salient point bump structure and ball lower metal layer further, become the technical problem that those skilled in the art are urgently to be resolved hurrily.
Summary of the invention
The problem that the present invention solves is to provide a kind of wafer-level packaging method, to improve the bond strength between bump structure and ball lower metal layer as far as possible.
For solving the problem, the invention provides a kind of wafer-level packaging method, comprising:
There is provided substrate, described substrate surface has conducting metal pad;
Described conducting metal pad is formed the metal core protruding from substrate surface;
At end face and the side coated ball lower metal layer of described metal core;
Bump structure is formed on described ball lower metal layer surface.
Optionally, the step of substrate is provided also to comprise:
Form passivation layer at described substrate surface, and described conducting metal pad is exposed from described passivation layer.
Optionally, the step of substrate is provided also to comprise:
Described passivation layer forms protective layer, and described conducting metal pad is exposed from described protective layer; Described conducting metal pad and described passivation layer and protective layer form opening jointly.
Optionally, the step forming metal core comprises: make described metal core be formed at described open bottom.
Optionally, the material of described protective layer is polyimides.
Optionally, the step forming metal core comprises:
Form plating seed layer over the substrate;
Described plating seed layer forms photoresist layer;
Removal unit divides photoresist to expose the plating seed layer corresponding to conducting metal pad position;
On the described plating seed layer corresponding to conducting metal pad position, described metal core is formed by plating;
Remove photoresist layer.
Optionally, comprise at the end face of described metal core and the step of side coated ball lower metal layer: adopt the mode of plating to form described ball lower metal layer.
Optionally, the step forming bump structure comprises: ball is planted in employing, reflux technique forms described bump structure.
Optionally, the material of described metal core is not identical with the material of bump structure.
Optionally, the material of ball lower metal layer is not identical with the material of ball lower metal layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
By forming the metal core protruding from substrate surface on described conducting metal pad; Then at end face and the side coated ball lower metal layer of described metal core; After this, bump structure is formed on described ball lower metal layer surface.That is, the metal core being coated with ball lower metal layer protrudes from the surface of described substrate, which increases the contact-making surface between bump structure and ball lower metal layer, because the equal coated ball lower metal layer of the end face of metal core and side, and in prior art, the upper surface contact salient point structure of ball lower metal layer.And, the part being coated with the metal core of ball lower metal layer stretches into bump structure, which increase the bond strength between bump structure and ball lower metal layer, the structure of bump structure and ball lower metal layer is more stable, not easily come off, and then improve the mechanically stable degree of encapsulating structure, and enhance heat conductivity and the electrical conductivity of encapsulating structure.
Accompanying drawing explanation
Fig. 1 is the structural representation of the encapsulating structure of existing crystal wafer chip dimension;
The structural representation of each step in Fig. 2 to Fig. 6 wafer-level packaging method one of the present invention embodiment.
Embodiment
Inadequate with bond strength between the encapsulating structure bumps structure of existing crystal wafer chip dimension and ball lower metal layer, this can cause the mechanical stability of whole encapsulating structure to reduce, and such as, causes bump structure to depart from from ball lower metal layer part and even comes off.Meanwhile, the conductivity performance of encapsulating structure and heat-conductive characteristic also can be affected.
Therefore, the invention provides a kind of wafer-level packaging method, comprising:
There is provided substrate, described substrate surface has conducting metal pad; Described conducting metal pad is formed the metal core protruding from substrate surface; At end face and the side coated ball lower metal layer of described metal core; Bump structure is formed on described ball lower metal layer surface.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Referring to figs. 2 to the structural representation of each step in Fig. 6 wafer-level packaging method one of the present invention embodiment.
First with reference to figure 2, substrate 101 is provided.Described substrate 101 is in the present embodiment for being formed with the wafer of the semiconductor device such as transistor.
Described substrate 101 surface has conducting metal pad 102, and described conducting metal pad 102 is surperficial for the circuit characteristic in substrate 101 being led to substrate 101, so that follow-up encapsulation.
In the present embodiment, provide the step of substrate to be also included in described substrate 101 surface and be also formed with passivation layer 103, described passivation layer 103 is for the protection of substrate 101 surface.
Described conducting metal pad 102 exposes from described passivation layer 103, passivation layer 103 can be avoided so as far as possible to affect conducting metal pad 102 and be electrically connected with the bump structure of follow-up encapsulation.
Concrete, the material of the passivation layer 103 in the present embodiment can be silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material.But the material of passivation layer 103 is prior art, and the present invention is not limited in any way this.
In the present embodiment, the thickness of described passivation layer 103 is in the scope of 1 ~ 2 micron.But this is only an example, the thickness of the present invention to described passivation layer 103 is not construed as limiting, but should determine according to actual conditions.
In conjunction with reference to figure 3, in the present embodiment, provide the step of substrate 101 to be also included on described passivation layer 103 and form protective layer 104.
Described protective layer 104 can be protected the passivation layer 103 on substrate 101 and substrate 101 further; because under normal circumstances; the quality of passivation layer 103 is more crisp (such as; the passivation layer 103 of silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material in the present embodiment); easy generation is damaged, so form layer protective layer 104 to be again conducive to protection substrate 101 and passivation layer 103 on passivation layer 103.
In addition, described protective layer 104 can also play the effect on planarization passivation layer 103 surface.Because generally, the thickness of passivation layer 103 is less, and the surface of substrate 101 have sometimes more concavo-convex (such as, some semiconductor device that substrate 101 surface is formed), that is, after covering passivation layer 103, substrate 101 surface still may be uneven, and this is unfavorable for the formation of follow-up ball lower metal layer and bump structure.Therefore, forming protective layer 104 can the surface of planarized substrate 101, and then facilitates follow-up ball lower metal layer and the formation of bump structure.
When forming protective layer 104, described conducting metal pad 102 being exposed from described protective layer 104, affecting conducting metal pad 102 to avoid protective layer 104 as far as possible and being electrically connected with the bump structure of follow-up encapsulation.
Described conducting metal pad 102 forms opening jointly with described passivation layer 103 and protective layer 104.
In the present embodiment, the protective layer 104 of polyimide material is formed.This material has good elasticity, and quality is comparatively hard, is conducive to protection substrate 101 and passivation layer 103 further.
In the present embodiment, forming thickness is the protective layer 104 of 4 ~ 6 microns, is conducive to filling and leading up substrate 101 surface being coated with passivation layer 103 in this thickness range, is unlikely to again blocked up simultaneously and excessively increases the volume of whole encapsulating structure.
After this, with reference to figure 4, described conducting metal pad 102 forms the metal core 105 protruding from substrate 101 surface, described metal core 105 is for increasing the bond strength between the bump structure of follow-up formation and ball lower metal layer, because described metal core 105 protrudes from substrate 101 surface, the ball lower metal layer of follow-up formation is simultaneously coated on end face and the side of described metal core 105, therefore the contact-making surface between ball lower metal layer and bump structure increases, and ball lower metal layer stretches into bump structure inside, which increase the bond strength between bump structure and ball lower metal layer, the structure of bump structure and ball lower metal layer is more stable, not easily come off, and then improve the mechanically stable degree of encapsulating structure, and enhance heat conductivity and the electrical conductivity of encapsulating structure.
Due in the present embodiment; protective layer 104 is formed on described substrate 101 surface; and described conducting metal pad 102 forms opening jointly with described passivation layer 103 and protective layer 104, so in the present embodiment, described metal core 105 should be made to be formed at described open bottom.
In the present embodiment; the surface of described metal core 105 is made to be not less than the surface of described protective layer 104; the various piece on the ball lower metal layer surface of follow-up like this formation is all unlikely to lower than the surface of protective layer 104 or flushes with the surface of protective layer 104; but the surface of protective layer 104 can be protruded from, and then reach the above-mentioned ball lower metal layer that makes and stretch into the object of bump structure inside.
Concrete, in the present embodiment, form described metal core 105 in the following ways:
Described substrate 101 forms plating seed layer; Concrete, the mode of sputtering sedimentation can be adopted to form described plating seed layer, but the present invention is not construed as limiting to this.
Described plating seed layer forms photoresist layer; Described photoresist layer is used for blocking corresponding to the plating inculating crystal layer not needing to be formed metal core 105 part.
Removal unit divides photoresist to expose the plating seed layer corresponding to conducting metal pad 102 position;
Substrate 101 surface is electroplated, to form described metal core 105 on the described plating seed layer corresponding to conducting metal pad 102 position;
After this, photoresist layer is removed.
In the present embodiment, the metal core 105 of copper, gold, silver, tin or nickel material can be formed.
With reference to figure 5, after the described metal core 105 of formation, at end face and the side coated ball lower metal layer 106 of described metal core 105; Described ball lower metal layer 106 is for defining the position of the bump structure of follow-up formation.
As mentioned before, ball lower metal layer 106 is coated on end face and the side of metal core 105, that is, the metal core 105 being coated with ball lower metal layer 106 also protrudes from the surface of described protective layer 104, which increase the contact-making surface between the bump structure of follow-up formation and ball lower metal layer 106, and the part being coated with the metal core 105 of ball lower metal layer 106 stretches into bump structure, which increase the bond strength between bump structure and ball lower metal layer 106, the structure of bump structure and ball lower metal layer 106 is more stable, not easily come off, and then improve the mechanically stable degree of encapsulating structure, and enhance heat conductivity and the electrical conductivity of encapsulating structure.
In the present embodiment, described ball lower metal layer 106 can be formed by the mode of plating.
In the present embodiment, the ball lower metal layer 106 of copper, gold, silver, tin or nickel material is formed.
Further, in the present embodiment, make the material of the ball lower metal layer 106 of formation different from the material of described metal core 105, such benefit is, different metal materials contacts, the atom meeting phase counterdiffusion of two kinds of metal materials, and then interface alloy compound layer (Intermetallic Compound altogether can be formed at the contact-making surface of two kinds of metal materials, IMC), be conducive to the bond strength between increase by two kinds of metals further, namely increase the bond strength of ball lower metal layer 106 and metal core 105 further.
With reference to figure 6, after formation ball lower metal layer 106, form bump structure 107 on described ball lower metal layer 106 surface.
In the present embodiment, described bump structure 107 is spherical male dot structure (namely soldered ball).But the present invention is not construed as limiting this, described bump structure 107 can also be other structures, such as column construction.
In the present embodiment, adopt plant ball, reflux technique forms described bump structure 107.
In the present embodiment, the bump structure 107 of copper, gold, silver, tin or nickel material is formed.
Make the material of ball lower metal layer 106 not identical with the material of bump structure 107 in the present embodiment.The reason different with metal core 105 material from ball lower metal layer 106 is above identical, the material of ball lower metal layer 106 is different from the material of bump structure 107 can form interface alloy compound layer altogether at both contact-making surfaces, and then increases bond strength between the two further.
In addition, the present invention also provides a kind of encapsulating structure, is the structural representation of encapsulating structure one embodiment of the present invention with reference to figure 6.In the present embodiment, described encapsulating structure comprises following structure:
Substrate 101, described substrate 101 surface has conducting metal pad 102; Described conducting metal pad 102 is for leading to substrate 101 surface so that encapsulation by the circuit characteristic in substrate 101.
In the present embodiment, described substrate 101 surface has passivation layer 103, and described passivation layer 103 is for the protection of substrate 101 surface.
Described conducting metal pad 102 exposes from described passivation layer 103, passivation layer 103 can be avoided so as far as possible to affect conducting metal pad 102 and be electrically connected with the bump structure 107 of follow-up encapsulation.
Concrete, the material of the passivation layer 103 in the present embodiment can be silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material.But the material of passivation layer 103 is prior art, and the present invention is not limited in any way this.
In the present embodiment, the thickness of described passivation layer 103 is in the scope of 1 ~ 2 micron.But this is only an example, the thickness of the present invention to described passivation layer 103 is not construed as limiting, but should determine according to actual conditions.
In the present embodiment; described passivation layer 103 is also formed with protective layer 104; described protective layer 104 can be protected the passivation layer 103 on substrate 101 and substrate 101 further; because under normal circumstances; the quality of passivation layer 103 is more crisp (such as; the passivation layer 103 of silicon nitride, Pyrex, phosphorosilicate glass or boron-phosphorosilicate glass material in the present embodiment); easy generation is damaged, so form layer protective layer 104 to be again conducive to protection substrate 101 and passivation layer 103 on passivation layer 103.
In addition, described protective layer 104 can also play the effect on planarization passivation layer 103 surface.Because generally, the thickness of passivation layer 103 is less, and the surface of substrate 101 have sometimes more concavo-convex (such as, some semiconductor device that substrate 101 surface is formed), that is, after covering passivation layer 103, substrate 101 surface still may be uneven, and this is unfavorable for the formation of ball lower metal layer 106 and bump structure 107.Therefore, protective layer 104 can the surface of planarized substrate 101, and then facilitates follow-up ball lower metal layer 106 and the formation of bump structure 107.
In the present embodiment, described conducting metal pad 102 exposes from described protective layer 104, affects conducting metal pad 102 be electrically connected with the bump structure 107 of follow-up encapsulation to avoid protective layer 104 as far as possible.
In the present embodiment, the material of protective layer 104 is polyimides 4.This material has good elasticity, and quality is comparatively hard, is conducive to protection substrate 101 and passivation layer 103 further.
In the present embodiment, the thickness of protective layer 104, in the scope of 4 ~ 6 microns, is conducive to filling and leading up substrate 101 surface being coated with passivation layer 103 in this thickness range, is simultaneously unlikely to again blocked up and excessively increases the volume of whole encapsulating structure.
Encapsulating structure of the present invention also comprises the metal core 105 be positioned on substrate 101, and described metal core 105 protrudes from the surface of described substrate 101, described metal core 105 is for increasing the bond strength between the bump structure 107 of follow-up formation and ball lower metal layer 106, because described metal core 105 protrudes from substrate 101 surface, the ball lower metal layer 106 of follow-up formation is simultaneously coated on described metal core 105 surface, therefore the contact-making surface between ball lower metal layer 106 and bump structure 107 increases, and ball lower metal layer 106 stretches into bump structure 107 inside, which increase the bond strength between bump structure 107 and ball lower metal layer 106, bump structure 107 is more stable with the structure of ball lower metal layer 106, not easily come off, and then improve the mechanically stable degree of encapsulating structure, and enhance heat conductivity and the electrical conductivity of encapsulating structure.
Because the surface of substrate 101 described in the present embodiment is formed with protective layer 104; therefore the surface of described metal core 105 is not less than the surface of described protective layer 104; the various piece on ball lower metal layer 106 surface of follow-up like this formation is all unlikely to lower than the surface of protective layer 104 or flushes with the surface of protective layer 104; but the surface of protective layer 104 can be protruded from, and then reach the above-mentioned ball lower metal layer 106 that makes and stretch into the object of bump structure 107 inside.
In the present embodiment, the material of metal core 105 can be copper, gold, silver, tin or nickel.
Encapsulating structure of the present invention also comprises and is coated on the end face of described metal core 105 and the ball lower metal layer 106 of side; Described ball lower metal layer 106 is for defining the position of bump structure 107.
As mentioned before, ball lower metal layer 106 is coated on end face and the side of metal core 105, that is, the metal core 105 being coated with ball lower metal layer 106 also protrudes from the surface of described protective layer 104, which increase the contact-making surface between the bump structure 107 of follow-up formation and ball lower metal layer 106, and the part being coated with the metal core 105 of ball lower metal layer 106 stretches into bump structure 107, which increase the bond strength between bump structure 107 and ball lower metal layer 106, bump structure 107 is more stable with the structure of ball lower metal layer 106, not easily come off, and then improve the mechanically stable degree of encapsulating structure, and enhance heat conductivity and the electrical conductivity of encapsulating structure.
In the present embodiment, the material of ball lower metal layer 106 can be copper, gold, silver, tin or nickel.
In the present embodiment, the material of described ball lower metal layer 106 is different from the material of described metal core 105, such benefit is, different metal materials contacts, the atom meeting phase counterdiffusion of two kinds of metal materials, and then interface alloy compound layer (IntermetallicCompound altogether can be formed at the contact-making surface of two kinds of metal materials, IMC), be conducive to the bond strength between increase by two kinds of metals further, namely increase the bond strength of ball lower metal layer 106 and metal core 105 further.
Encapsulating structure of the present invention also comprises the bump structure 107 being formed at described ball lower metal layer 106 surface.
In the present embodiment, described bump structure 107 is spherical male dot structure (namely soldered ball).But the present invention is not construed as limiting this, described bump structure 107 can also be other structures, such as column construction.
In the present embodiment, the material of bump structure 107 is copper, gold, silver, tin or nickel.
Further, in the present embodiment, the material of described ball lower metal layer 106 is not identical with the material of bump structure 107.The reason different with metal core 105 material from ball lower metal layer 106 is above identical, the material of ball lower metal layer 106 is different from the material of bump structure 107 can form interface alloy compound layer altogether at both contact-making surfaces, and then increases bond strength between the two further.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a wafer-level packaging method, is characterized in that, comprising:
There is provided substrate, described substrate surface has conducting metal pad;
Described conducting metal pad is formed the metal core protruding from substrate surface;
At end face and the side coated ball lower metal layer of described metal core;
Bump structure is formed on described ball lower metal layer surface.
2. wafer-level packaging method as claimed in claim 1, is characterized in that, provide the step of substrate also to comprise:
Form passivation layer at described substrate surface, and described conducting metal pad is exposed from described passivation layer.
3. wafer-level packaging method as claimed in claim 2, is characterized in that, provide the step of substrate also to comprise:
Described passivation layer forms protective layer, and described conducting metal pad is exposed from described protective layer;
Described conducting metal pad and described passivation layer and protective layer form opening jointly.
4. wafer-level packaging method as claimed in claim 3, is characterized in that, the step forming metal core comprises: make described metal core be formed at described open bottom.
5. wafer-level packaging method as claimed in claim 3, it is characterized in that, the material of described protective layer is polyimides.
6. wafer-level packaging method as claimed in claim 1, is characterized in that, the step forming metal core comprises:
Form plating seed layer over the substrate;
Described plating seed layer forms photoresist layer;
Removal unit divides photoresist to expose the plating seed layer corresponding to conducting metal pad position;
On the described plating seed layer corresponding to conducting metal pad position, described metal core is formed by plating;
Remove photoresist layer.
7. wafer-level packaging method as claimed in claim 1, is characterized in that, comprise at the end face of described metal core and the step of side coated ball lower metal layer: adopt the mode of plating to form described ball lower metal layer.
8. wafer-level packaging method as claimed in claim 1, is characterized in that, the step forming bump structure comprises: ball is planted in employing, reflux technique forms described bump structure.
9. wafer-level packaging method as claimed in claim 1, it is characterized in that, the material of described metal core is not identical with the material of bump structure.
10. wafer-level packaging method as claimed in claim 1, it is characterized in that, the material of described ball lower metal layer is not identical with the material of ball lower metal layer.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410784542.2A CN104485295A (en) | 2014-12-16 | 2014-12-16 | Wafer level packaging method |
US14/971,495 US9666550B2 (en) | 2014-12-16 | 2015-12-16 | Method and structure for wafer-level packaging |
US15/456,350 US9922950B2 (en) | 2014-12-16 | 2017-03-10 | Method and structure for wafer-level packaging |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410784542.2A CN104485295A (en) | 2014-12-16 | 2014-12-16 | Wafer level packaging method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104485295A true CN104485295A (en) | 2015-04-01 |
Family
ID=52759831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410784542.2A Pending CN104485295A (en) | 2014-12-16 | 2014-12-16 | Wafer level packaging method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104485295A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10861811B2 (en) | 2015-12-31 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Connector structure and method of forming same |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0689240A1 (en) * | 1994-05-06 | 1995-12-27 | Industrial Technology Research Institute | Bonded structure and methods for forming this structure |
CN1392607A (en) * | 2002-06-17 | 2003-01-22 | 威盛电子股份有限公司 | Bottom buffering metal lug structure |
JP2004247522A (en) * | 2003-02-14 | 2004-09-02 | Seiko Epson Corp | Semiconductor device and its fabricating process |
CN1604293A (en) * | 2003-10-03 | 2005-04-06 | 罗姆股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
CN101252106A (en) * | 2008-03-11 | 2008-08-27 | 日月光半导体制造股份有限公司 | Wafer structure with buffer layer |
TW200836275A (en) * | 2007-02-16 | 2008-09-01 | Chipmos Technologies Inc | Packaging conductive structure and method for manufacturing the same |
TW200849428A (en) * | 2007-06-13 | 2008-12-16 | Advanced Semiconductor Eng | Under bump metallurgy structure and die structure using the same and method of manufacturing die structure |
CN102034780A (en) * | 2009-10-01 | 2011-04-27 | 三星电子株式会社 | Integrated circuit chip and method of manufacturing the same and flip chip package having the integrated chip and method of manufacturing the same |
US20110266670A1 (en) * | 2010-04-30 | 2011-11-03 | Luke England | Wafer level chip scale package with annular reinforcement structure |
CN202394955U (en) * | 2012-01-17 | 2012-08-22 | 南通富士通微电子股份有限公司 | Wafer level package optimization structure |
CN102915986A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Chip packaging structure |
CN102931164A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Packaging element of semiconductor device |
CN102931158A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Chip packaging structure |
CN202917474U (en) * | 2012-11-08 | 2013-05-01 | 南通富士通微电子股份有限公司 | Semiconductor package structure |
CN103199027A (en) * | 2012-01-05 | 2013-07-10 | 台湾积体电路制造股份有限公司 | UBM formation for integrated circuits |
US20130256871A1 (en) * | 2012-03-29 | 2013-10-03 | Roden R. Topacio | Semiconductor chip device with fragmented solder structure pads |
-
2014
- 2014-12-16 CN CN201410784542.2A patent/CN104485295A/en active Pending
Patent Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0689240A1 (en) * | 1994-05-06 | 1995-12-27 | Industrial Technology Research Institute | Bonded structure and methods for forming this structure |
CN1392607A (en) * | 2002-06-17 | 2003-01-22 | 威盛电子股份有限公司 | Bottom buffering metal lug structure |
JP2004247522A (en) * | 2003-02-14 | 2004-09-02 | Seiko Epson Corp | Semiconductor device and its fabricating process |
CN1604293A (en) * | 2003-10-03 | 2005-04-06 | 罗姆股份有限公司 | Method for manufacturing semiconductor device and semiconductor device |
TW200836275A (en) * | 2007-02-16 | 2008-09-01 | Chipmos Technologies Inc | Packaging conductive structure and method for manufacturing the same |
TW200849428A (en) * | 2007-06-13 | 2008-12-16 | Advanced Semiconductor Eng | Under bump metallurgy structure and die structure using the same and method of manufacturing die structure |
CN101252106A (en) * | 2008-03-11 | 2008-08-27 | 日月光半导体制造股份有限公司 | Wafer structure with buffer layer |
CN102034780A (en) * | 2009-10-01 | 2011-04-27 | 三星电子株式会社 | Integrated circuit chip and method of manufacturing the same and flip chip package having the integrated chip and method of manufacturing the same |
US20110266670A1 (en) * | 2010-04-30 | 2011-11-03 | Luke England | Wafer level chip scale package with annular reinforcement structure |
CN103199027A (en) * | 2012-01-05 | 2013-07-10 | 台湾积体电路制造股份有限公司 | UBM formation for integrated circuits |
CN202394955U (en) * | 2012-01-17 | 2012-08-22 | 南通富士通微电子股份有限公司 | Wafer level package optimization structure |
US20130256871A1 (en) * | 2012-03-29 | 2013-10-03 | Roden R. Topacio | Semiconductor chip device with fragmented solder structure pads |
CN102915986A (en) * | 2012-11-08 | 2013-02-06 | 南通富士通微电子股份有限公司 | Chip packaging structure |
CN102931164A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Packaging element of semiconductor device |
CN102931158A (en) * | 2012-11-08 | 2013-02-13 | 南通富士通微电子股份有限公司 | Chip packaging structure |
CN202917474U (en) * | 2012-11-08 | 2013-05-01 | 南通富士通微电子股份有限公司 | Semiconductor package structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10861811B2 (en) | 2015-12-31 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Connector structure and method of forming same |
TWI729046B (en) * | 2015-12-31 | 2021-06-01 | 台灣積體電路製造股份有限公司 | Connector structure and method of forming same |
US11824026B2 (en) | 2015-12-31 | 2023-11-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Connector structure and method of forming same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11515288B2 (en) | Protective layer for contact pads in fan-out interconnect structure and method of forming same | |
CN105280599B (en) | Contact pad for semiconductor devices | |
CN103594441B (en) | Semiconductor package and method of manufacturing the same | |
US10679930B2 (en) | Metal core solder ball interconnector fan-out wafer level package | |
TWI502663B (en) | Semiconductor device and method of forming enhanced ubm structure for improving solder joint reliability | |
US9484291B1 (en) | Robust pillar structure for semicondcutor device contacts | |
TWI479620B (en) | Chip scale surface mounted semiconductor device package and process of manufacture | |
US9293432B2 (en) | Metal contact for chip packaging structure | |
US20150137351A1 (en) | Semiconductor device and manufacturing method thereof | |
US11810849B2 (en) | Connection structure and method of forming the same | |
TW201125073A (en) | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate | |
TWI676244B (en) | A semiconductor package and method for fabricating the same | |
CN106898596A (en) | Semiconductor structure and its manufacture method | |
JP2006261643A (en) | Semiconductor device and method of fabricating the same | |
KR20150091933A (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
TW201209977A (en) | Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis | |
KR100842921B1 (en) | Method for fabricating of semiconductor package | |
US9922950B2 (en) | Method and structure for wafer-level packaging | |
US8722467B2 (en) | Method of using bonding ball array as height keeper and paste holder in semiconductor device package | |
CN103413770B (en) | The manufacture method of salient point | |
US8981566B2 (en) | Discrete semiconductor device package and manufacturing method | |
US20100155937A1 (en) | Wafer structure with conductive bumps and fabrication method thereof | |
CN102244061A (en) | Low-k chip package structure | |
TW201642362A (en) | Chip package and manufacturing method thereof | |
CN103915397B (en) | More bare crystallines, high current wafer-level packaging |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
COR | Change of bibliographic data | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150401 |
|
RJ01 | Rejection of invention patent application after publication |