CN104485284A - Preparation methods of controllable arrayed nanowires and FET (field effect transistor) comprising controllable arrayed nanowires - Google Patents
Preparation methods of controllable arrayed nanowires and FET (field effect transistor) comprising controllable arrayed nanowires Download PDFInfo
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- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000012544 monitoring process Methods 0.000 description 4
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 4
- 238000012876 topography Methods 0.000 description 3
- 229910000238 buergerite Inorganic materials 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004549 pulsed laser deposition Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000010792 warming Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
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Abstract
The invention discloses a preparation method of controllable arrayed nanowires and a preparation method of an FET (field effect transistor) comprising the controllable arrayed nanowires. According to the preparation method of the controllable arrayed nanowires and the preparation method of the FET comprising the controllable arrayed nanowires, materials with anisotropic growth rates of growing materials in different crystal orientations in epitaxial growth are selected as substrates, so that growth of the nanowires is realized; configurations and diameters of the patterned substrates are designed, so that cycles, the number, lengths and diameters of the arrayed nanowires can be controlled accurately, and different FET requirements can be met; growth conditions of group-VI-rich or group-V-rich atoms realize the surface inhibition effect, isotropic migrations of the metal atoms on surfaces are reduced, and growth of the nanowires is facilitated; the FET comprising the controllable arrayed nanowires can be prepared with a traditional semiconductor device preparation technology, the technology is simple, the controllability is high, the cost is low, and mass production can be realized.
Description
Technical field
The present invention relates to the preparation method of field-effect transistor, particularly relate to a kind of preparation method of controlled aligned nanowires and the preparation method of controlled aligned nanowires field-effect transistor.
Background technology
One-dimensional nanometer semiconductor structure has very high crystal mass, excellent electricity and optical property, make it at nano-device, such as fieldtron, photoelectric detector, high efficiency light-emitting device, senser element, Monoelectron memory device and single photon device etc., field has a wide range of applications.Field-effect transistor FET be a kind of by semi-conducting material make by the three-terminal element of voltage control electric current, in electronic circuit, have extremely important effect, nano-wire fet is the foundation stone applied of nano electron device especially.
The development experience of FET from flat FET to fin FETs again to the differentiation of nano-wire fet.Because fin FETs is the Nanoscale channels obtained by micro-nano technology technology, inevitably can produce some extra defect and damages in the process, reduce effect of FET; But nano wire is the nanostructure of primary length, there is good surface topography and very high crystal mass, and nano-wire fet has the advantage of fin FETs concurrently.But single nano-wire FET source-drain current is relatively little, is difficult to obtain practical application.In addition, nano-wire fet can improve source-drain current and grid voltage to the ability of regulation and control of source-drain current by the quantity of nano wire in control channel, reach improve FET mutual conductance, source-drain current and on-off ratio object, so aligned nanowires FET arises at the historic moment.
The method preparing aligned nanowires FET at present mainly comprises, and extraneous method controls array arrangement and the lateral growth nanowire approach of nano wire.But the former is difficult to obtain large-area aligned nanowires, and the latter's controllability is very poor, thus controlled aligned nanowires FET is caused to be difficult to realize.
Summary of the invention
For above prior art Problems existing, the present invention proposes the preparation method of a kind of controlled aligned nanowires and field-effect transistor thereof, controlled aligned nanowires can be prepared, as cycle of nano wire, diameter, length and the equal controllable of quantity, and traditional process for fabrication of semiconductor device is utilized to prepare controlled aligned nanowires field-effect transistor FET on this basis.
One object of the present invention is the preparation method providing a kind of controlled aligned nanowires.
The preparation method of controlled aligned nanowires of the present invention, for the preparation of the aligned nanowires of II-VI group or iii-v, comprises the following steps:
1) the growth rate anisotropic material of growth material along different crystal orientations is chosen as substrate;
2) according to the preparation requirement of field-effect transistor FET, the figure of design configuration substrate, preparation patterned substrate;
3) preliminary treatment is carried out to patterned substrate, make the clean surface of patterned substrate;
4) according to the growth rate in override growth crystal orientation, the atom line of VI race or V group atom is determined;
5) according to cycle and the diameter of aligned nanowires, the atom line of II race or III atom is determined;
6) according to the condition determined above, the patterned substrate of cleaning grows aligned nanowires.
Wherein, in step 1) in, select the material require of substrate to consider, institute's growth material is anisotropy along the growth rate of different crystal orientations thereon.Crystal orientation is grown along override in the direction of the nano wire of Grown, growth material is stronger along the growth rate anisotropy of different crystal orientations, namely the override growth growth rate in crystal orientation is larger with the ratio of the growth rate in other directions, and the single linear of nano wire is more remarkable.Override growth crystal orientation is positioned at substrate surface.
In step 2) in, the figure of design configuration substrate refers to, the preparation of field-effect transistor FET requires the cycle and the diameter that determine aligned nanowires, according to cycle and the diameter of aligned nanowires, and the arrangement of the figure of design configuration substrate and diameter.The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice.The arrangement of figure can be the two-dimensional lattice of equidistantly arrangement, also can be the two-dimensional lattice of rectanglar arrangement.The row of two-dimensional lattice arrange to along override growth crystal orientation, and the distance (column pitch) between adjacent two row is the cycle of aligned nanowires, and the length of column direction determines the length of nano wire; The columns of two-dimensional lattice is the quantity of aligned nanowires.The diameter d in post or hole determines the diameter D of nano wire, and the diameter D of nano wire is slightly larger than the diameter d in post or hole, and the value of the ratio D/d of the two is between 1 ~ 3.The preparation method of patterned substrate comprises: nanometer embossing, electron beam exposure EBL and focused ion beam FIB etc.
In step 3) in, the preliminary treatment of patterned substrate is comprised: chemical cleaning is carried out to the patterned substrate prepared, then carry out high-temperature baking, the foreign atom on removing surface, thus make the clean surface of patterned substrate.
In step 4) in, the growing method of aligned nanowires determines the growth rate ν in override growth crystal orientation, and the growth rate ν in override growth crystal orientation determines the atom line F of VI race or V group atom
1, meet relation F
1=k
1ν, wherein, k
1for coefficient, relevant with the crystal structure of the material of aligned nanowires.
In step 5) in; the growth of aligned nanowires can select the growth conditions of rich VI race or rich V group atom usually; be conducive to suppressing the isotropism of metallic atom on surface to be moved, thus realize the growth of controlled aligned nanowires, concrete II race or III atom line F
2needs were determined according to the cycle of designed aligned nanowires and diameter, II race or III atom line F
2, relevant with the arrangement of the diameter D of nano wire and the figure of patterned substrate, meet relational expression: F
2=k
2d
2/ L
1 2, or F
2=k
2d
2/ (L
2l
3), wherein, k
2for coefficient, relevant with the growing method that growth aligned nanowires adopts, L
1for in the two-dimensional lattice of equidistantly arranging, the distance between adjacent 2, L
2and L
3be respectively the line space in the two-dimensional lattice of rectanglar arrangement and column pitch.
In step 6) in, the method growing controlled aligned nanowires comprises: molecular beam epitaxy MBE, metal-organic chemical vapor deposition equipment MOCVD, chemical vapour deposition (CVD) CVD, pulsed laser deposition PLD etc.Along with the increase of growth time, grow at the post of patterned substrate or Kong Shanghui the nano wire segment that length increases gradually, till nano wire segment connects into a complete straight line, growth terminates.Before nano wire segment is combined with each other, the length of nano wire segment is regulated and controled by growth time, and the length of growth time longer nano wire segment is longer.
Another object of the present invention is the preparation method providing a kind of controlled aligned nanowires field-effect transistor.
The preparation method of controlled aligned nanowires field-effect transistor FET of the present invention, for the preparation of the aligned nanowires of II-VI group or iii-v, comprises the following steps:
1) the growth rate anisotropic material of growth material along different crystal orientations is chosen as substrate;
2) according to the preparation requirement of field-effect transistor FET, the figure of design configuration substrate, preparation patterned substrate;
3) preliminary treatment is carried out to patterned substrate, make the clean surface of patterned substrate;
4) according to the growth rate in override growth crystal orientation, the atom line of VI race or V group atom is determined;
5) according to cycle and the diameter of patterned substrate, the atom line of II race or III atom is determined;
6) according to the condition determined above, the patterned substrate of cleaning grows aligned nanowires;
7) using the aligned nanowires that grown on substrate as the channel region of FET, adopt traditional semiconductor device fabrication processes, form source electrode, drain electrode, gate insulator and grid successively thereon.
Wherein, in step 7) in, when preparing aligned nanowires FET, the quantity selecting contained nano wire in channel region can be required, to meet different FET demands according to the preparation of FET.
Aligned nanowires refers to, one group of nano wire be arranged in array by equidirectional.Experiment finds that semi-conducting material presents obvious anisotropy along the growth rate of different crystal orientations, the present invention utilizes this characteristic, choose the growth rate anisotropic substrate of growth material along different crystal orientations, the nano wire that orientation is consistent can be prepared, cycle of aligned nanowires, diameter, length and quantity can be regulated and controled further by patterned substrate, thus prepare controlled aligned nanowires FET.
Advantage of the present invention:
(1) by arrangement and the diameter of design configuration substrate, can cycle of accuracy controlling aligned nanowires, quantity, length and diameter, meet different FET demands;
(2) in selective epitaxy growth growth material along the anisotropic material of growth rate of different crystal orientations as substrate, thus realize the growth of nano wire;
(3) growth conditions of rich VI race or rich V group atom reaches the effect that surface suppresses, and reduces the isotropism of metallic atom on surface and moves, be conducive to the growth of nano wire;
(4) preparation of controlled aligned nanowires FET can adopt traditional semiconductor device fabrication processes, and technique is simple, and Modulatory character is strong, with low cost, can realize batch production.
Accompanying drawing explanation
Fig. 1 be according to the embodiment one of the preparation method of controlled aligned nanowires of the present invention obtain
the partial schematic diagram of face GaN column patterned substrate, wherein, (a) is vertical view, and (b) is end view;
Fig. 2 be according to the embodiment one of the preparation method of controlled aligned nanowires of the present invention obtain
the partial schematic diagram of nano wire segment in the GaN column patterned substrate of face, wherein, (a) is vertical view, and (b) is end view;
Fig. 3 be according to the embodiment one of the preparation method of controlled aligned nanowires of the present invention obtain
the partial schematic diagram of aligned nanowires in the GaN column patterned substrate of face, wherein, (a) is vertical view, and (b) is end view;
Fig. 4 be according to the embodiment two of the preparation method of controlled aligned nanowires of the present invention obtain
the partial schematic diagram of the poroid patterned substrate of face 4H-SiC, wherein, (a) is vertical view, and (b) is the profile along A-A ' line in figure (a);
Fig. 5 be according to the embodiment two of the preparation method of controlled aligned nanowires of the present invention obtain
the partial schematic diagram of nano wire segment in the poroid patterned substrate of face 4H-SiC, wherein, (a) is vertical view, and (b) is the profile along A-A ' line in figure (a);
Fig. 6 be according to the embodiment two of the preparation method of controlled aligned nanowires of the present invention obtain
the partial schematic diagram of aligned nanowires in the poroid patterned substrate of face 4H-SiC, wherein, (a) is vertical view, and (b) is the profile along A-A ' line in figure (a);
Fig. 7 is the schematic diagram of the controlled aligned nanowires FET obtained according to the preparation method of controlled aligned nanowires field-effect transistor of the present invention, wherein, a () is vertical view, b () is the profile along B-B ' line in figure (a), (c) is end view.
Embodiment
Below in conjunction with accompanying drawing, by embodiment, the present invention will be further described.
Embodiment one
In the present embodiment, the controlled aligned nanowires of preparation GaN, substrate adopts GaN; The figure of patterned substrate is periodic column two-dimensional lattice; The growth material of aligned nanowires is GaN; The growing method of aligned nanowires adopts molecular beam epitaxy MBE to exist
face GaN patterned substrate grows; Growth course is carried out in ultra high vacuum growth chamber, and high-purity (7N) source metal is produced by K-Cell source stove; Nitrogenous source adopts radio frequency plasma nitrogenous source; Growth course reflection high energy electron diffraction RHEED in-situ monitoring.
The preparation method of the controlled aligned nanowires of the present embodiment, comprises the following steps:
1) the growth rate anisotropic material of growth material along different crystal orientations is chosen as substrate:
Buergerite GaN is along [0001] direction growth rate much larger than edge
with
the growth rate in direction, selects
face GaN as substrate, make [0001] and
direction, in substrate surface, is conducive to the growth of nano wire.
2) according to the preparation requirement of field-effect transistor FET, the figure of design configuration substrate, preparation patterned substrate:
The figure of patterned substrate is the two-dimensional lattice of cylindric equidistant arrangement, distance between adjacent 2 is 500nm, diameter d=350nm, without mask, then the column pitch of two-dimensional lattice is the distance × sin 60 ° between adjacent 2, i.e. 500 × sin, 60 °=433nm, nano-imprinting method is adopted to prepare patterned substrate, as shown in Figure 1.
3) preliminary treatment is carried out to patterned substrate, makes the clean surface of patterned substrate:
First, chemically clean patterned substrate, make the surface cleaning of patterned substrate; Then, patterned substrate is warming up to about 600 DEG C, baking 10 ~ 30min.
4) according to the growth rate in override growth crystal orientation, the atom line of V group atom is determined:
The growing method of molecular beam epitaxy MBE determines override growth, and crystal orientation---the growth rate in [0001] direction is 10nm/min, and now the line of nitrogen-atoms is about F
n=7.6 × 10
14cm
-2s
-2.
5) according to cycle and the diameter of patterned substrate, the atom line of III atom is determined:
According to cycle and the diameter of figure, the atom line of optimization is than being F
n/ F
ga=5, then the line of Ga atom is about F
ga=1.52 × 10
14cm
-2s
-2.
6) according to the condition determined above, the patterned substrate of cleaning grows aligned nanowires, along with the increase of growth time, the post of patterned substrate can grow the nano wire segment that length increases gradually, as shown in Figure 2, till nano wire segment connects into a complete straight line, aligned nanowires growth terminates, as shown in Figure 3, the cycle P of the aligned nanowires obtained is the column pitch 433nm of nano wire, the diameter of nano wire is D=400nm, for the two-dimensional lattice of equidistantly arrangement, the length L of nano wire is the distance between the counting of column × adjacent 2, the quantity of nano wire is the columns of two-dimensional lattice, the shape in the cross section of single nano-wire is regular hexagon.RHEED in-situ monitoring is used in growth course.
The controlled aligned nanowires of GaN of this method growth has good surface topography and higher crystal mass, scanning electron microscopy SEM test shows that nano wire orientation is consistent with [0001] direction, nano wire along [0001] direction growth rate apparently higher than
direction.
Embodiment two
In the present embodiment, the controlled aligned nanowires FET of preparation GaN, substrate adopts GaN; The figure of patterned substrate is periodic poroid two-dimensional lattice; The growth material of aligned nanowires is GaN; The growing method of aligned nanowires adopts molecular beam epitaxy MBE to exist
face 4H-SiC patterned substrate grows; Growth course is carried out in ultra high vacuum chamber, and high-purity (7N) source metal is produced by K-Cell source stove; Nitrogenous source adopts radio frequency plasma nitrogenous source; Growth course reflection high energy electron diffraction RHEED in-situ monitoring.
The preparation method of the controlled aligned nanowires FET of the present embodiment, comprises the following steps:
1) the growth rate anisotropic material of growth material along different crystal orientations is chosen as substrate:
Buergerite GaN is along [0001] direction growth rate much larger than edge
with
the growth rate in direction, selects
face 4H-SiC as substrate, make [0001] and
direction, in substrate surface, is conducive to the growth of nano wire.
2) according to the preparation requirement of field-effect transistor FET, the figure of design configuration substrate, preparation patterned substrate:
The figure of patterned substrate is the two-dimensional lattice of the circular hole four directions arrangement having mask, first exists
face 4H-SiC substrate 1 use plasma enhanced chemical vapor deposition PECVD method grow the thick SiO of 20nm
2as mask 21, then adopt focused ion beam FIB to prepare patterned substrate, figure is the two-dimensional lattice 2 of the four directions arrangement of circular hole, and as shown in Figure 4, prepared the different figure of three column pitch respectively at this, design parameter is as shown in the table:
| Column pitch/μm | 1.0 | 2.0 | 3.0 |
| Line space/μm | 1.0 | 2.0 | 3.0 |
| Diameter d/nm | 50 | 50 | 50 |
3) preliminary treatment is carried out to patterned substrate, makes the clean surface of patterned substrate:
First, chemically clean patterned substrate, make the surface cleaning of patterned substrate; Then, patterned substrate is warming up to about 600 DEG C, baking 10 ~ 30min.
4) according to the growth rate in override growth crystal orientation, the atom line of V group atom is determined:
The growing method of molecular beam epitaxy MBE determines override growth, and crystal orientation---the growth rate in [0001] direction is 10nm/min, and now the line of nitrogen-atoms is about F
n=7.6 × 10
14cm
-2s
-2.
5) according to cycle and the diameter of patterned substrate, the atom line of III atom is determined:
The figure that three column pitch are different, corresponding atom line is as shown in the table:
| Column pitch/μm | 1.0 | 2.0 | 3.0 |
| F N/F Ga | 5 | 10 | 15 |
| F Ga(10 14cm -2s -2) | 1.52 | 0.76 | 0.51 |
6) according to the condition determined above, the patterned substrate of cleaning grows aligned nanowires, along with the increase of growth time, the nano wire segment 31 that length increases gradually is grown at the Kong Shanghui of patterned substrate, as shown in Figure 5, till nano wire segment connects into a complete straight line, aligned nanowires 3 grows and terminates, as shown in Figure 6, the shape in the cross section of single nano-wire is regular hexagon, for the two-dimensional lattice of rectanglar arrangement, the length L of nano wire is line space × line number, the quantity of nano wire is the columns of two-dimensional lattice, the relevant parameter of the aligned nanowires obtained sees the following form:
| Column pitch/μm | 1.0 | 2.0 | 3.0 |
| The cycle P/ μm of aligned nanowires | 1.0 | 2.0 | 3.0 |
| The diameter D/nm of nano wire | 150 | 120 | 100 |
RHEED in-situ monitoring is used in growth course.The controlled aligned nanowires of GaN of this method growth has good surface topography and higher crystal mass, and SEM test shows that nano wire orientation is consistent with [0001] direction, nano wire along [0001] direction growth rate apparently higher than
direction, and nano wire segment be combined with each other before length regulated and controled by growth time.
7) using the aligned nanowires that grown on the substrate channel region as FET, require according to the preparation of FET the quantity selecting contained nano wire in channel region, to meet the demand of prepared FET; Adopt traditional semiconductor device fabrication processes, form source electrode 4, drain electrode 5, gate insulator 6 and grid 7 successively thereon, obtain controlled aligned nanowires FET, as shown in Figure 7.
More than sets forth the embodiment preparing aligned nanowires and aligned nanowires FET.Preparation method of the present invention can prepare the controlled aligned nanowires FET of II-VI group or iii-v and other semiconductors, as long as the semi-conducting material related to has anisotropic growth rate, method of the present invention can be adopted to choose substrate, design configuration is required according to FET, preparation patterned substrate, the atom line of each growth source is determined according to the parameter such as cycle and diameter of figure, realize the growth of controlled aligned nanowires, thus prepare controlled aligned nanowires, and prepare controlled aligned nanowires FET in conjunction with traditional process for fabrication of semiconductor device on this basis.
It is finally noted that, the object publicizing and implementing mode is to help to understand the present invention further, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various substitutions and modifications are all possible.Therefore, the present invention should not be limited to the content disclosed in embodiment, and the scope that the scope of protection of present invention defines with claims is as the criterion.
Claims (10)
1. a preparation method for controlled aligned nanowires, for the preparation of the aligned nanowires of II-VI group or iii-v, it is characterized in that, described preparation method comprises the following steps:
1) the growth rate anisotropic material of growth material along different crystal orientations is chosen as substrate;
2) according to the preparation requirement of field-effect transistor FET, the figure of design configuration substrate, preparation patterned substrate;
3) preliminary treatment is carried out to patterned substrate, make the clean surface of patterned substrate;
4) according to the growth rate in override growth crystal orientation, the atom line of VI race or V group atom is determined;
5) according to cycle and the diameter of aligned nanowires, the atom line of II race or III atom is determined;
6) according to the condition determined above, the patterned substrate of cleaning grows aligned nanowires.
2. preparation method as claimed in claim 1, it is characterized in that, in step 1) in, crystal orientation is grown along override in the direction of the nano wire of Grown, growth material is stronger along the growth rate anisotropy of different crystal orientations, namely the override growth growth rate in crystal orientation is larger with the ratio of the growth rate in other directions, and the single linear of nano wire is more remarkable; Override growth crystal orientation is positioned at substrate surface.
3. preparation method as claimed in claim 1, is characterized in that, in step 2) in, according to cycle and the diameter of aligned nanowires, the arrangement of the figure of design configuration substrate and diameter; The figure of patterned substrate is periodic column two-dimensional lattice, or is periodic poroid two-dimensional lattice; The arrangement of figure is the two-dimensional lattice of equidistantly arrangement, or the two-dimensional lattice of rectanglar arrangement.
4. preparation method as claimed in claim 3, is characterized in that, the row of two-dimensional lattice arrange to along override growth crystal orientation, and the distance between adjacent two row is the cycle of aligned nanowires; The columns of two-dimensional lattice is the quantity of aligned nanowires.
5. preparation method as claimed in claim 3, is characterized in that, the diameter d in post or hole determines the diameter D of nano wire, and the value of the ratio D/d of the two is between 1 ~ 3.
6. preparation method as claimed in claim 1, it is characterized in that, in step 4) in, the growing method of aligned nanowires determines the growth rate ν in override growth crystal orientation, and the growth rate ν in override growth crystal orientation determines the atom line F of VI race or V group atom
1, meet relation F
1=k
1ν, wherein, k
1for coefficient, relevant with the crystal structure of the material of aligned nanowires.
7. preparation method as claimed in claim 1, is characterized in that, in step 5) in, the growth conditions of rich VI race or rich V group atom is selected in the growth of aligned nanowires, II race or III atom line F
2, relevant with the arrangement of the diameter D of nano wire and the figure of patterned substrate, meet relational expression: F
2=k
2d
2/ L
1 2, or F
2=k
2d
2/ (L
2l
3), wherein, k
2for coefficient, relevant with the growing method adopted of growth aligned nanowires, L
1for in the two-dimensional lattice of equidistantly arranging, the distance between adjacent 2, L
2and L
3be respectively the line space in the two-dimensional lattice of rectanglar arrangement and column pitch.
8. preparation method as claimed in claim 3, is characterized in that, in step 6) in, along with the increase of growth time, grow at the post of patterned substrate or Kong Shanghui the nano wire segment that length increases gradually, till nano wire segment connects into a complete straight line, growth terminates; Before nano wire segment is combined with each other, the length of nano wire segment is regulated and controled by growth time, and the length of growth time longer nano wire segment is longer.
9. a preparation method of controlled aligned nanowires field-effect transistor FET, for the preparation of the aligned nanowires of II-VI group or iii-v, it is characterized in that, described preparation method comprises the following steps:
1) the growth rate anisotropic material of growth material along different crystal orientations is chosen as substrate;
2) according to the preparation requirement of field-effect transistor FET, the figure of design configuration substrate, preparation patterned substrate;
3) preliminary treatment is carried out to patterned substrate, make the clean surface of patterned substrate;
4) according to the growth rate in override growth crystal orientation, the atom line of VI race or V group atom is determined;
5) according to cycle and the diameter of patterned substrate, the atom line of II race or III atom is determined;
6) according to the condition determined above, the patterned substrate of cleaning grows aligned nanowires;
7) using the aligned nanowires that grown on substrate as the channel region of FET, adopt traditional semiconductor device fabrication processes, form source electrode, drain electrode, gate insulator and grid successively thereon.
10. preparation method as claimed in claim 9, is characterized in that, in step 7) in, require according to the preparation of FET the quantity selecting contained nano wire in channel region, to meet the demand of FET.
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