CN104485083B - The chip system of imput output circuit and its control method and liquid crystal display - Google Patents
The chip system of imput output circuit and its control method and liquid crystal display Download PDFInfo
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- CN104485083B CN104485083B CN201410857343.XA CN201410857343A CN104485083B CN 104485083 B CN104485083 B CN 104485083B CN 201410857343 A CN201410857343 A CN 201410857343A CN 104485083 B CN104485083 B CN 104485083B
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Abstract
A kind of chip system of imput output circuit and its control method and liquid crystal display, wherein, the size of first PMOS and the second NMOS tube is 1/15~1/7 than scope；The size of first NMOS tube and the second PMOS is 1/15~1/7 than scope；Described control unit is suitable to control first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube to be in cut-off state, either control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the second PMOS are in cut-off state or controls that first PMOS and the second NMOS tube are in cut-off state and the first NMOS tube and the second PMOS are in the conduction state.
Description
Technical field
The present invention relates to electronic applications, more particularly to a kind of imput output circuit and its control method and liquid crystal display
Chip system.
Background technology
Imput output circuit is chip and the bridge that other chips are interacted in system, is responsible for reception main control chip and sends over
Control signal, or to master signal feedback status information.
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display,
TFT-LCD) in driving chip, control instruction and image data that main control chip is sent can pass through imput output circuit
Reception comes；It is also that master control is fed back to by imput output circuit when main control chip reads the information of TFT-LCD driving chips
Chip.The quality of imput output circuit design, directly influences the speed of chip reception or feedback information.Further, since input
What output circuit sent or received is an AC signal that constantly height changes, and designs unreasonable, can produce electromagnetic interference
The normal work of other chips in (Electro Magnetic Interference, EMI), influence system.
Fig. 1 is a kind of existing imput output circuit, including：PMOS P1, NMOS tube N1, the first phase inverter INV1, second
It is phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th anti-
Phase device INV7, NAND gate NAND1, nor gate NOR1, total input DB and output end DOUT.
Existing imput output circuit has two kinds of mode of operations：When enabling signal EN=0, under input pattern, from total
The signal inputted on input DB, core is input to by hex inverter INV6 and the 7th phase inverter INV7 by output end DOUT
Inside piece.At that time can signal EN=1 when, under output mode, the data-signal Data sent from chip internal is with enabling
Signal EN is by combinational logic NAND gate NAND1, nor gate NOR1, the first phase inverter INV1, the second phase inverter INV2, the 3rd anti-
Phase device INV3, the 4th phase inverter INV4 and the 5th phase inverter INV5, control PMOS P1 and NMOS tube N1, realize data-signal
Data signal outputs are on total input DB.
However, existing input brings out circuit, because PMOS P1 and NMOS tube N1 will do ESD protection circuit, institute simultaneously
It is made big with their size, but under output mode, overshoot phenomenon often occurs on total input DB, such as Fig. 2 institute
Show, quickly overshoot signal, be one of source of electromagnetic interference.
In addition, under general LCD driving chip techniques, PMOS P1 profile, as shown in Figure 3.In the profile
It is middle to there is a parasitic triode, as shown in Figure 4.Because total input DB is connected on pin, under extraneous interference, meeting
The voltage for total input DB occur is more than the situation of mono- PN junction voltage of supply voltage VDD, causes parasitic triode to turn on, total defeated
Path is formed between the substrate for entering to hold DB to connection low-voltage VGL, the stability of whole driving chip is influenceed.
The content of the invention
The problem of present invention is solved is that existing input brings out circuit and is vulnerable to electromagnetic interference.
To solve the above problems, technical solution of the present invention provides a kind of imput output circuit, including：First PMOS,
One NMOS tube, the second PMOS, the second NMOS tube, drive end and control unit；
The drain electrode of the source electrode of first PMOS and second NMOS tube is adapted to input supply voltage, described first
The drain electrode of the source electrode of NMOS tube and second PMOS is adapted to input ground voltage, the drain electrode connection institute of first PMOS
State source electrode, the drain electrode of the first NMOS tube, the source electrode and drive end of the second PMOS of the second NMOS tube；
The size of first PMOS and the second NMOS tube is 1/15~1/7 than scope；
The size of first NMOS tube and the second PMOS is 1/15~1/7 than scope；
Described control unit is suitable to control first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube
In cut-off state, or control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and
Second PMOS is in cut-off state, or controls first PMOS and the second NMOS tube to be in cut-off state and first
NMOS tube and the second PMOS are in the conduction state.
Optionally, described control unit is suitable to control first PMOS, first when enabling signal for the first level
NMOS tube, the second PMOS and the second NMOS tube are in cut-off state, are second electrical level and data-signal in the enable signal
First PMOS is controlled during for second electrical level and the second NMOS tube is in the conduction state and first NMOS tube and second
PMOS is in cut-off state, is that second electrical level and data-signal control described first when being the first level in the enable signal
PMOS and the second NMOS tube are in cut-off state and the first NMOS tube and the second PMOS are in the conduction state.
Optionally, described control unit includes：With arithmetic element or arithmetic element, the first phase inverter and the second phase inverter；
It is described to be suitable to arithmetic element to the data-signal and enable signal progress and calculation process, described and computing list
The output end of member connects the input of first phase inverter and the grid of the second NMOS tube；
Described or arithmetic element is suitable to carry out NOR-operation to the inversion signal of the data-signal and the enable signal
Processing, described or arithmetic element output end connects the input of second phase inverter and the grid of the second PMOS；
The output end of first phase inverter connects the grid of first PMOS；
The output end of second phase inverter connects the grid of first NMOS tube.
Optionally, it is described to include with arithmetic element：NAND gate and the 3rd phase inverter；
The first input end of the NAND gate is suitable to input the enable signal, and the second input of the NAND gate is suitable to
The data-signal is inputted, the output end of the NAND gate connects the input of the 3rd phase inverter；
The output end of 3rd phase inverter connects the input of first phase inverter.
Optionally, described or arithmetic element includes：4th phase inverter, nor gate and the 5th phase inverter；
The input of 4th phase inverter is suitable to input the enable signal, the output end connection of the 4th phase inverter
The first end of the nor gate；
Second input of the nor gate is suitable to input the data-signal, and the output end connection of the nor gate is described
The input of 5th phase inverter；
The output end of 5th phase inverter connects the input of second phase inverter.
Optionally, the imput output circuit also includes：Output end, hex inverter and the 7th phase inverter；
The input of the hex inverter connects the source electrode of second NMOS tube, the output end of the hex inverter
Connect the input of the 7th phase inverter；
The output end of 7th phase inverter connects the output end.
Technical solution of the present invention also provides a kind of chip system of liquid crystal display, including：Main control chip and driving chip；
The driving chip includes：Above-mentioned imput output circuit and logical gate circuit, the drive of the imput output circuit
Moved end connects the main control chip, and the output end of the imput output circuit connects the logical gate circuit of the driving chip
Input, the output end of the logical gate circuit of the driving chip is suitable to export the enable signal and data-signal.
Technical solution of the present invention also provides a kind of imput output circuit, including：First PMOS, the first NMOS tube, second
PMOS, the second NMOS tube, drive end and control unit；
The source electrode of first PMOS is suitable to input supply voltage, and the source electrode of first NMOS tube is suitable to input ground electricity
Pressure, the drain electrode of drain electrode connection second NMOS tube of first PMOS, the source electrode connection of second NMOS tube is described
The source electrode and drive end of second PMOS, the drain electrode of drain electrode connection first NMOS tube of second PMOS；
The size of first PMOS and the second NMOS tube is 1/15~1/7 than scope；
The size of first NMOS tube and the second PMOS is 1/15~1/7 than scope；
Described control unit be suitable to enable signal be the first level when control first PMOS, the first NMOS tube,
Second PMOS and the second NMOS tube are in cut-off state, and in the enable signal be second electrical level and data-signal is the second electricity
Usually control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the second PMOS at
In cut-off state, the enable signal be controlled when second electrical level and data-signal are the first level first PMOS and
Second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in the conduction state.
Optionally, described control unit is suitable to control first PMOS, first when enabling signal for the first level
NMOS tube, the second PMOS and the second NMOS tube are in cut-off state, are second electrical level and data-signal in the enable signal
First PMOS is controlled during for second electrical level and the second NMOS tube is in the conduction state and first NMOS tube and second
PMOS is in cut-off state, is that second electrical level and data-signal control described first when being the first level in the enable signal
PMOS and the second NMOS tube are in cut-off state and the first NMOS tube and the second PMOS are in the conduction state.
Optionally, described control unit includes：With arithmetic element or arithmetic element, the first phase inverter and the second phase inverter；
It is described to be suitable to arithmetic element to data-signal and enable signal progress and calculation process, described and arithmetic element
Output end connects the input of first phase inverter and the grid of the second NMOS tube；
Described or arithmetic element is suitable to carry out NOR-operation to the inversion signal of the data-signal and the enable signal
Processing, described or arithmetic element output end connects the input of second phase inverter and the grid of the second PMOS；
The output end of first phase inverter connects the grid of first PMOS；
The output end of second phase inverter connects the grid of first NMOS tube.
Optionally, it is described to include with arithmetic element：NAND gate and the 3rd phase inverter；
The first input end of the NAND gate is suitable to input the enable signal, and the second input of the NAND gate is suitable to
The data-signal is inputted, the output end of the NAND gate connects the input of the 3rd phase inverter；
The output end of 3rd phase inverter connects the input of first phase inverter.
Optionally, described or arithmetic element includes：4th phase inverter, nor gate and the 5th phase inverter；
The input of 4th phase inverter is suitable to input the enable signal, the output end connection of the 4th phase inverter
The first end of the nor gate；
Second input of the nor gate is suitable to input the data-signal, and the output end connection of the nor gate is described
The input of 5th phase inverter；
The output end of 5th phase inverter connects the input of second phase inverter.
Optionally, the imput output circuit also includes：Output end, hex inverter and the 7th phase inverter；
The input of the hex inverter connects the source electrode of second NMOS tube, the output end of the hex inverter
Connect the input of the 7th phase inverter；
The output end of 7th phase inverter connects the output end.
Technical solution of the present invention also provides a kind of chip system of liquid crystal display, including：Main control chip and driving chip；
The driving chip includes：Above-mentioned imput output circuit and logical gate circuit, the drive of the imput output circuit
Moved end connects the main control chip, and the output end of the imput output circuit connects the logical gate circuit of the driving chip
Input, the output end of the logical gate circuit of the driving chip is suitable to export the enable signal and data-signal.
Technical solution of the present invention also provides a kind of control method of imput output circuit, and the imput output circuit includes：
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube, the source electrode of first PMOS and described second
The drain electrode of NMOS tube is adapted to input supply voltage, and the drain electrode of the source electrode of first NMOS tube and second PMOS is fitted
In input ground voltage, the source electrode of drain electrode connection second NMOS tube of first PMOS, the drain electrode of the first NMOS tube and
The size of the source electrode of second PMOS, first PMOS and the second NMOS tube is 1/15~1/7, described first than scope
The size of NMOS tube and the second PMOS is 1/15~1/7 than scope, and the control method of the imput output circuit includes：
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube is controlled to be in cut-off state；
Control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the 2nd PMOS
Pipe is in cut-off state；
First PMOS and the second NMOS tube is controlled to be at cut-off state and the first NMOS tube and the second PMOS
In conducting state.
Technical solution of the present invention also provides a kind of control method of imput output circuit, and the imput output circuit includes：
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube, the source electrode of first PMOS are suitable to input power
Voltage, the source electrode of first NMOS tube is suitable to input ground voltage, and the drain electrode of first PMOS connects the 2nd NMOS
The drain electrode of pipe, the source electrode of second NMOS tube connects the source electrode of second PMOS, and the drain electrode of second PMOS connects
Connect the drain electrode of first NMOS tube, the size of first PMOS and the second NMOS tube is 1/15~1/7 than scope, described
The size of first NMOS tube and the second PMOS is 1/15~1/7 than scope, and the control method of the imput output circuit includes：
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube is controlled to be in cut-off state；
Control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the 2nd PMOS
Pipe is in cut-off state；
First PMOS and the second NMOS tube is controlled to be at cut-off state and the first NMOS tube and the second PMOS
In conducting state.
Compared with prior art, the imput output circuit of technical solution of the present invention will be used in existing imput output circuit
Large scale PMOS and NMOS split into the NMOS tube and PMOS of proper ratio, and utilize small size PMOS and NMOS tube
Undertake the final stage of output voltage pullup or pulldown, it is therefore prevented that output signal overshooting problem, effectively avoid electromagnetic interference
Problem.Also, the size of parasitic triode is reduced, the underlayer voltage shake that output voltage shake is caused can be also substantially reduced,
Chip is more stablized.
Brief description of the drawings
Fig. 1 is existing inputting and outputting circuit structure schematic diagram；
Fig. 2 is the signal output waveform schematic diagram of existing imput output circuit；
Fig. 3 is the profile of PMOS in existing imput output circuit；
Fig. 4 is parasitic triode schematic diagram in existing imput output circuit；
Fig. 5 is the structural representation of imput output circuit one of the embodiment of the present invention；
Fig. 6 is the signal output waveform schematic diagram of the imput output circuit of the embodiment of the present invention；
Fig. 7 is another structural representation of imput output circuit of the embodiment of the present invention；
Fig. 8 is the structural representation of imput output circuit one of another embodiment of the present invention；
Fig. 9 is another structural representation of imput output circuit of another embodiment of the present invention.
Embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
As shown in figure 5, the embodiment of the present invention provides a kind of imput output circuit, including：First PMOS P1, the first NMOS
Pipe N1, the second PMOS P2, the second NMOS tube N2, drive end DB and control unit.Described control unit includes：With arithmetic element
1 or arithmetic element 2, the first phase inverter INV1 and the second phase inverter INV2.
The drain electrode of the source electrode of the first PMOS P1 and the second NMOS tube N2 is adapted to input supply voltage VDD,
The source electrode of the first NMOS tube N1 and the second PMOS P2 drain electrode are adapted to input ground voltage GND, described first
PMOS P1 drain electrode connection the second NMOS tube N2 source electrode, the first NMOS tube N1 drain electrode, the second PMOS P2 source
Pole and drive end DB.
The first PMOS P1 and the second NMOS tube N2 size are 1/15~1/7, first NMOS tube than scope
N1 and the second PMOS P2 size are 1/15~1/7 than scope.For example, the first PMOS P1 and the second NMOS tube N2
Size is 1/9 than scope, and the first NMOS tube N1 and the second PMOS P2 size is also 1/9 than scope.
Described control unit is suitable to control the first PMOS P1, the first NMOS tube N1, the second PMOS P2 and second
NMOS tube N2 is in cut-off state, or controls the first PMOS P1 and the second NMOS tube N2 in the conduction state and described
First NMOS tube N1 and the second PMOS P2 is in cut-off state, or controls the first PMOS P1 and the second NMOS tube N2
In cut-off state and the first NMOS tube N1 and the second PMOS P2 are in the conduction state.
Specifically, described control unit be suitable to enable signal EN be the first level when control the first PMOS P1,
First NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 are in cut-off state, are the second electricity in the enable signal EN
Flat and data-signal DATA controls the first PMOS P1 and the second NMOS tube N2 to manage when being second electrical level in the conduction state
It is second electrical level and data in the enable signal EN and the first NMOS tube N1 and the second PMOS P2 is in cut-off state
Signal DATA controls the first PMOS P1 and the second NMOS tube N2 to be in cut-off state and the first NMOS when being the first level
Pipe N1 and the second PMOS P2 are in the conduction state.
In the present embodiment, described control unit can include：With arithmetic element 1 or arithmetic element 2, the first phase inverter
INV1 and the second phase inverter INV2.It is described to be suitable to arithmetic element 1 to data-signal DATA and enable signal EN progress and computing
Processing, the output end with arithmetic element 1 is connected the input of the first phase inverter INV1 and the second NMOS tube N2 grid
Pole.
Described or arithmetic element 2 be suitable to carry out the data-signal DATA and enable signal EN inversion signal or
Inverse processing, described or arithmetic element 2 output end connects the input and the second PMOS of the second phase inverter INV2
P2 grid.
The output end of the first phase inverter INV1 connects the grid of the first PMOS P1, second phase inverter
INV2 output end connects the grid of the first NMOS tube N1.
The output imput output circuit can also include：Output end DOUT.The output end DOUT connections described second
NMOS tube N2 source electrode.
Following examples are using the first level as low level signal " 0 ", and second electrical level is progress exemplified by high level signal " 1 "
Explanation.
When enabling signal EN=0, the imput output circuit is in input pattern：
No matter Data=1 or 0, export low level signal to the second NMOS tube N2 grids, the first phase inverter with arithmetic element 1
INV1 exports high level signal to the first PMOS P1 grids, or arithmetic element and exports high level signal to the second PMOS P2 grid
Pole, the second phase inverter INV2 exports low level signal to the first NMOS tube N1 grids, the first PMOS P1, the first NMOS tube N1,
Second PMOS P2 and the second NMOS tube N2 are in cut-off state；The signal inputted from drive end DB is defeated by output end DOUT
Go out.
When enabling signal EN=1, the imput output circuit is in output mode：
In Data=1, high level signal is exported to the second NMOS tube N2 grids, the first phase inverter with arithmetic element 1
INV1 exports low level signal to the first PMOS P1 grids, and the first PMOS P1 and the second NMOS tube N2 are in turning on shape
State；Also, or arithmetic element exports high level signal to the second PMOS P2 grids, the second phase inverter INV2 output low level letters
Number cut-off state is in the first NMOS tube N1 grids, the first NMOS tube N1 and the second PMOS P2；
In Data=0, low level signal is exported to the second NMOS tube N2 grids, the first phase inverter with arithmetic element 1
INV1 exports high level signal to the first PMOS P1 grids, and the first PMOS P1 and the second NMOS tube N2 are in ending shape
State；Also, or arithmetic element exports low level signal to the second PMOS P2 grids, the second phase inverter INV2 output high level letters
Number conducting state is in the first NMOS tube N1 grids, the first NMOS tube N1 and the second PMOS P2.
In the output mode of the present embodiment, during Data=1, the voltage on drive end DB changes from low to high, initial rank
Duan Shi, because the first PMOS P1 and large-sized second NMOS tube N2 (size is 1/15~1/7 than scope) of small size are equal
It is in the conduction state, so drive end DB voltage rapid increase.But the second NMOS tube N2 can only be driven into drive end DB
The amplitude for a threshold value that supply voltage VDD subtracts one, i.e. (VDD represents the magnitude of voltage of supply voltage to VDD-VTH1, and VTH1 represents second
NMOS tube N2 threshold voltage value), and VDD-VTH1 to the VDD stages can only lean on the first PMOS P1 of small size to drive.Due to
First PMOS P1's is small-sized, and the phenomenon overshooted upwards will not be caused on drive end DB.
Similarly, the voltage worked as on Data=0, drive end DB changes from high to low, during the starting stage, due to the of small size
One NMOS tube N1 and large-sized second PMOS P2 (size is 1/15~1/7 than scope) are in conducting state, so driving
Moved end DB voltage rapid decrease.But because the second PMOS P2 can only pull down to drive end DB poor one of liftoff voltage GND
Threshold value VTH2 current potential (VTH2 represents the second PMOS P2 threshold voltage value), VTH2 can only lean on first to ground voltage GND
NMOS tube N1 come complete drop-down.It is small-sized due to the first NMOS tube N1, it will not cause what is overshooted downwards on drive end DB
Phenomenon.
Fig. 6 gives the present embodiment imput output circuit under output mode, the waveform of output signal on drive end DB, by
Waveform, which can be seen that output signal, is not having overshoot phenomenon, so as to effectively avoid electromagnetic interference (EMI) problem.
Simultaneously as the first PMOS P1 sizes diminish compared with prior art, the size of parasitic triode substantially diminishes, so
Under external interference, the underlayer voltage shake that drive end DB shakes are caused can be also substantially reduced, and chip is more stablized.
As shown in fig. 7, can include with arithmetic element 1 described in the present embodiment：NAND gate NAND and the 3rd phase inverter
INV3。
The first input end of the NAND gate NAND is suitable to input the enable signal EN, the second of the NAND gate NAND
Input is suitable to input the data-signal DATA, and the output end of the NAND gate NAND connects the 3rd phase inverter INV3's
Input.The output end of the 3rd phase inverter INV3 connects the input of the first phase inverter INV1.
Described or arithmetic element 2 includes：4th phase inverter INV4, nor gate NOR and the 5th phase inverter INV5.
The input of the 4th phase inverter INV4 is suitable to input the enable signal EN, the 4th phase inverter INV4's
Output end connects the first end of the nor gate NOR.The second input of the nor gate NOR is suitable to input the data-signal
DATA, the nor gate NOR output end connect the input of the 5th phase inverter INV5.The 5th phase inverter INV5's
Output end connects the input of the second phase inverter INV2.
The imput output circuit can also include：Hex inverter INV6 and the 7th phase inverter INV7.The output end
Hex inverter INV6 and the 7th phase inverter INV7 the second NMOS tubes of connection N2 that DOUT passes through series connection source electrode.Specifically, institute
The input for stating hex inverter INV6 connects the source electrode of the second NMOS tube N2, the output end of the hex inverter INV6
The input of the 7th phase inverter INV7 is connected, the output end of the 7th phase inverter INV7 connects the output end DOUT.
As shown in figure 8, another implementation of the invention also provides a kind of imput output circuit, the imput output circuit bag
Include：First PMOS P1, the first NMOS tube N1, the second PMOS P2, the second NMOS tube N2, drive end DB and control unit.
The source electrode of the first PMOS P1 is suitable to input supply voltage VDD, and the source electrode of the first NMOS tube N1 is suitable to
Input ground voltage GND, the first PMOS P1 drain electrode connection the second NMOS tube N2 drain electrode, second NMOS tube
N2 source electrode connects the drain electrode connection described the of the source electrode and drive end DB, the second PMOS P2 of the second PMOS P2
One NMOS tube N1 drain electrode.
The first PMOS P1 and the second NMOS tube N2 size are 1/15~1/7, first NMOS tube than scope
N1 and the second PMOS P2 size are 1/15~1/7 than scope.For example, the first PMOS P1 and the second NMOS tube N2
Size is 1/9 than scope, and the first NMOS tube N1 and the second PMOS P2 size is also 1/9 than scope.
Described control unit is suitable to control the first PMOS P1, the first NMOS when enabling signal EN for the first level
Pipe N1, the second PMOS P2 and the second NMOS tube N2 are in cut-off state, are second electrical level and data in the enable signal EN
Signal DATA controls the first PMOS P1 and the second NMOS tube N2 in the conduction state and described first when being second electrical level
NMOS tube N1 and the second PMOS P2 is in cut-off state, is second electrical level in the enable signal EN and data-signal DATA is
The first PMOS P1 and the second NMOS tube N2 is controlled to be in cut-off state and the first NMOS tube N1 and second during the first level
PMOS P2 is in the conduction state.
Specifically, described control unit be suitable to enable signal EN be the first level when control the first PMOS P1,
First NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 are in cut-off state, are the second electricity in the enable signal EN
Flat and data-signal DATA control the first PMOS P1 and the second NMOS tube N2 in the conduction state when being second electrical level and
The first NMOS tube N1 and the second PMOS P2 is in cut-off state, and in the enable signal EN be second electrical level and data are believed
Number DATA controls the first PMOS P1 and the second NMOS tube N2 to be in cut-off state and the first NMOS tube when being the first level
N1 and the second PMOS P2 are in the conduction state.
In the present embodiment, described control unit can include：With arithmetic element 1 or arithmetic element 2, the first phase inverter
INV1 and the second phase inverter INV2.
It is described to be suitable to arithmetic element 1 to data-signal DATA and enable signal EN progress and calculation process, described and fortune
The output end for calculating unit 1 connects the input of the first phase inverter INV1 and the second NMOS tube N2 grid.
Described or arithmetic element 2 be suitable to carry out the data-signal DATA and enable signal EN inversion signal or
Inverse processing, described or arithmetic element 2 output end connects the input and the second PMOS of the second phase inverter INV2
P2 grid.
The output end of the first phase inverter INV1 connects the grid of the first PMOS P1, second phase inverter
INV2 output end connects the grid of the first NMOS tube N1.
The output imput output circuit can also include：With output end DOUT.Output end DOUT connections described second
NMOS tube N2 source electrode.
When enabling signal EN=0, the imput output circuit is in input pattern：
No matter Data=1 or 0, export low level signal to the second NMOS tube N2 grids, the first phase inverter with arithmetic element 1
INV1 exports high level signal to the first PMOS P1 grids, or arithmetic element and exports high level signal to the second PMOS P2 grid
Pole, the second phase inverter INV2 exports low level signal to the first NMOS tube N1 grids, the first PMOS P1, the first NMOS tube N1,
Second PMOS P2 and the second NMOS tube N2 are in cut-off state；The signal inputted from drive end DB is defeated by output end DOUT
Go out.
When enabling signal EN=1, the imput output circuit is in output mode：
In Data=1, high level signal is exported to the second NMOS tube N2 grids, the first phase inverter with arithmetic element 1
INV1 exports low level signal to the first PMOS P1 grids, and the first PMOS P1 and the second NMOS tube N2 are in turning on shape
State；Also, or arithmetic element exports high level signal to the second PMOS P2 grids, the second phase inverter INV2 output low level letters
Number cut-off state is in the first NMOS tube N1 grids, the first NMOS tube N1 and the second PMOS P2；
In Data=0, low level signal is exported to the second NMOS tube N2 grids, the first phase inverter with arithmetic element 1
INV1 exports high level signal to the first PMOS P1 grids, and the first PMOS P1 and the second NMOS tube N2 are in ending shape
State；Also, or arithmetic element exports low level signal to the second PMOS P2 grids, the second phase inverter INV2 output high level letters
Number conducting state is in the first NMOS tube N1 grids, the first NMOS tube N1 and the second PMOS P2.
It is similar with a upper embodiment, in the output mode of the present embodiment, either Data=1 or 0, by size very
Small the first PMOS P1 and the first NMOS tube N1 undertakes last voltage pullup or pulldown, so will not be made on drive end DB
Into the phenomenon overshooted up or down.Equally, the size of parasitic triode substantially diminishes, so under external interference, drive end DB
Shaking the underlayer voltage shake caused can also be substantially reduced, and chip is more stablized.
As shown in figure 9, described include with arithmetic element 1：NAND gate NAND and the 3rd phase inverter INV3.
The first input end of the NAND gate NAND is suitable to input the enable signal EN, the second of the NAND gate NAND
Input is suitable to input the data-signal DATA, and the output end of the NAND gate NAND connects the 3rd phase inverter INV3's
Input；The output end of the 3rd phase inverter INV3 connects the input of the first phase inverter INV1.
Described or arithmetic element 2 includes：4th phase inverter INV4, nor gate NOR and the 5th phase inverter INV5.
The input of the 4th phase inverter INV4 is suitable to input the enable signal EN, the 4th phase inverter INV4's
Output end connects the first end of the nor gate NOR；The second input of the nor gate NOR is suitable to input the data-signal
DATA, the nor gate NOR output end connect the input of the 5th phase inverter INV5；The 5th phase inverter INV5's
Output end connects the input of the second phase inverter INV2.
Described imput output circuit also includes：Hex inverter INV6 and the 7th phase inverter INV7.The output end
Hex inverter INV6 and the 7th phase inverter INV7 the second NMOS tubes of connection N2 that DOUT passes through series connection source electrode.Specifically, institute
The input for stating hex inverter INV6 connects the source electrode of the second NMOS tube N2, the output end of the hex inverter INV6
The input of the 7th phase inverter INV7 is connected, the output end of the 7th phase inverter INV7 connects the output end DOUT.
The embodiment of the present invention also provides a kind of chip system of liquid crystal display, including：Main control chip and driving chip.
The driving chip includes：The imput output circuit and logical gate circuit of above-described embodiment, the input and output
The drive end DB connections main control chip of circuit, the output end DOUT connections driving chip of the imput output circuit
The input of logical gate circuit, the output end of the logical gate circuit of the driving chip is suitable to export the enable signal EN
With data-signal DATA.Other parts embodiment on main control chip and driving chip may be referred to prior art,
Here is omitted.
The embodiment of the present invention also provides a kind of control method of imput output circuit, and the imput output circuit includes：The
One PMOS P1, the first NMOS tube N1, the second PMOS P2, the second NMOS tube N2, the source electrode of the first PMOS P1 and institute
The drain electrode for stating the second NMOS tube N2 is adapted to input supply voltage VDD, the source electrode and described second of the first NMOS tube N1
The drain electrode that PMOS P2 drain electrode is adapted to input ground voltage GND, the first PMOS P1 connects the second NMOS tube N2
Source electrode, the first NMOS tube N1 drain electrode, the second PMOS P2 source electrode, the first PMOS P1 and the second NMOS tube N2's
Size is 1/15~1/7 than scope, and the first NMOS tube N1 and the second PMOS P2 size is 1/15~1/7 than scope,
The control method of the imput output circuit includes：
The first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 pipes is controlled to be in and cut
Only state；
Control the first PMOS P1 and the second NMOS tube N2 in the conduction state and the first NMOS tube N1 and
Two PMOS P2 are in cut-off state；
The first PMOS P1 and the second NMOS tube N2 is controlled to be in cut-off state and the first NMOS tube N1 and second
PMOS P2 is in the conduction state.
The embodiment of the present invention also provides a kind of control method of imput output circuit, and the imput output circuit includes：The
One PMOS P1, the first NMOS tube N1, the second PMOS P2, the second NMOS tube N2, the source electrode of the first PMOS P1 are suitable to
Input supply voltage VDD, the first NMOS tube N1 source electrode are suitable to input ground voltage GND, the leakage of the first PMOS P1
Pole connects the drain electrode of the second NMOS tube N2, and the source electrode of the second NMOS tube N2 connects the source of the second PMOS P2
Pole, drain electrode connection the first NMOS tube N1 of the second PMOS P2 drain electrode, the first PMOS P1 and second
NMOS tube N2 size is 1/15~1/7 than scope, and the first NMOS tube N1 and the second PMOS P2 size is than scope
1/15~1/7, the control method of the imput output circuit includes：
The first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 is controlled to be in cut-off
State；
Control the first PMOS P1 and the second NMOS tube N2 in the conduction state and the first NMOS tube N1 and
Two PMOS P2 are in cut-off state；
The first PMOS P1 and the second NMOS tube N2 is controlled to be in cut-off state and the first NMOS tube N1 and second
PMOS P2 is in the conduction state.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (16)
1. a kind of imput output circuit, it is characterised in that including：First PMOS, the first NMOS tube, the second PMOS, second
NMOS tube, drive end and control unit；
The drain electrode of the source electrode of first PMOS and second NMOS tube is adapted to input supply voltage, the first NMOS
The drain electrode of the source electrode of pipe and second PMOS is adapted to input ground voltage, the drain electrode connection described the of first PMOS
The source electrode of two NMOS tubes, the drain electrode of the first NMOS tube, the source electrode and drive end of the second PMOS；
The size of first PMOS and the second NMOS tube is 1/15~1/7 than scope；
The size of first NMOS tube and the second PMOS is 1/15~1/7 than scope；
Described control unit is suitable to control first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube to be in
Cut-off state, or control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and second
PMOS is in cut-off state, or controls first PMOS and the second NMOS tube to be in cut-off state and the first NMOS tube
It is in the conduction state with the second PMOS.
2. imput output circuit as claimed in claim 1, it is characterised in that it is that described control unit, which is suitable to enabling signal,
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube is controlled to be in cut-off state during one level, in institute
It is to control first PMOS and the second NMOS tube to be in when second electrical level and data-signal are second electrical level to state enable signal
Conducting state and first NMOS tube and the second PMOS are in cut-off state, are second electrical level and number in the enable signal
It is believed that controlling first PMOS and the second NMOS tube to be in cut-off state and the first NMOS tube and the when number being the first level
Two PMOSs are in the conduction state.
3. imput output circuit as claimed in claim 2, it is characterised in that described control unit includes：With arithmetic element or
Arithmetic element, the first phase inverter and the second phase inverter；
It is described to be suitable to arithmetic element to the data-signal and enable signal progress and calculation process, described and arithmetic element
Output end connects the input of first phase inverter and the grid of the second NMOS tube；
Described or arithmetic element is suitable to carry out NOR-operation processing to the inversion signal of the data-signal and the enable signal,
Described or arithmetic element output end connects the input of second phase inverter and the grid of the second PMOS；
The output end of first phase inverter connects the grid of first PMOS；
The output end of second phase inverter connects the grid of first NMOS tube.
4. imput output circuit as claimed in claim 3, it is characterised in that described to include with arithmetic element：NAND gate and
Three phase inverters；
The first input end of the NAND gate is suitable to input the enable signal, and the second input of the NAND gate is suitable to input
The data-signal, the output end of the NAND gate connects the input of the 3rd phase inverter；
The output end of 3rd phase inverter connects the input of first phase inverter.
5. imput output circuit as claimed in claim 3, it is characterised in that described or arithmetic element includes：4th phase inverter,
Nor gate and the 5th phase inverter；
The input of 4th phase inverter is suitable to input the enable signal, and the output end connection of the 4th phase inverter is described
The first end of nor gate；
Second input of the nor gate is suitable to input the data-signal, the output end connection the described 5th of the nor gate
The input of phase inverter；
The output end of 5th phase inverter connects the input of second phase inverter.
6. the imput output circuit as described in claim 1 to 5 any claim, it is characterised in that also include：Output end,
Hex inverter and the 7th phase inverter；
The input of the hex inverter connects the source electrode of second NMOS tube, the output end connection of the hex inverter
The input of 7th phase inverter；
The output end of 7th phase inverter connects the output end.
7. a kind of chip system of liquid crystal display, it is characterised in that including：Main control chip and driving chip；
The driving chip includes：Imput output circuit described in logical gate circuit and claim 6, the input and output electricity
The drive end on road connects the main control chip, and the output end of the imput output circuit connects the logical gate of the driving chip
The input of circuit, the output end of the logical gate circuit of the driving chip be suitable to export the enable signal sum it is believed that
Number.
8. a kind of imput output circuit, it is characterised in that including：First PMOS, the first NMOS tube, the second PMOS, second
NMOS tube, drive end and control unit；
The source electrode of first PMOS is suitable to input supply voltage, and the source electrode of first NMOS tube is suitable to input ground voltage,
The drain electrode of drain electrode connection second NMOS tube of first PMOS, the source electrode connection described second of second NMOS tube
The source electrode and drive end of PMOS, the drain electrode of drain electrode connection first NMOS tube of second PMOS；
The size of first PMOS and the second NMOS tube is 1/15~1/7 than scope；
The size of first NMOS tube and the second PMOS is 1/15~1/7 than scope；
Described control unit is suitable to control first PMOS, the first NMOS tube, second when enabling signal for the first level
PMOS and the second NMOS tube are in cut-off state, when the enable signal is second electrical level and data-signal is second electrical level
Control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the second PMOS are in and cut
Only state, is to control first PMOS and second when second electrical level and data-signal are the first level in the enable signal
NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in the conduction state.
9. imput output circuit as claimed in claim 8, it is characterised in that it is that described control unit, which is suitable to enabling signal,
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube is controlled to be in cut-off state during one level, in institute
It is to control first PMOS and the second NMOS tube to be in when second electrical level and data-signal are second electrical level to state enable signal
Conducting state and first NMOS tube and the second PMOS are in cut-off state, are second electrical level and number in the enable signal
It is believed that controlling first PMOS and the second NMOS tube to be in cut-off state and the first NMOS tube and the when number being the first level
Two PMOSs are in the conduction state.
10. imput output circuit as claimed in claim 9, it is characterised in that described control unit includes：With arithmetic element,
Or arithmetic element, the first phase inverter and the second phase inverter；
It is described to be suitable to arithmetic element to data-signal and enable signal progress and calculation process, the output with arithmetic element
The input of end connection first phase inverter and the grid of the second NMOS tube；
Described or arithmetic element is suitable to carry out NOR-operation processing to the inversion signal of the data-signal and the enable signal,
Described or arithmetic element output end connects the input of second phase inverter and the grid of the second PMOS；
The output end of first phase inverter connects the grid of first PMOS；
The output end of second phase inverter connects the grid of first NMOS tube.
11. imput output circuit as claimed in claim 10, it is characterised in that described to include with arithmetic element：NAND gate and
3rd phase inverter；
The first input end of the NAND gate is suitable to input the enable signal, and the second input of the NAND gate is suitable to input
The data-signal, the output end of the NAND gate connects the input of the 3rd phase inverter；
The output end of 3rd phase inverter connects the input of first phase inverter.
12. imput output circuit as claimed in claim 10, it is characterised in that described or arithmetic element includes：4th is anti-phase
Device, nor gate and the 5th phase inverter；
The input of 4th phase inverter is suitable to input the enable signal, and the output end connection of the 4th phase inverter is described
The first end of nor gate；
Second input of the nor gate is suitable to input the data-signal, the output end connection the described 5th of the nor gate
The input of phase inverter；
The output end of 5th phase inverter connects the input of second phase inverter.
13. the imput output circuit as described in claim 8 to 12 any claim, it is characterised in that also include：Output
End, hex inverter and the 7th phase inverter；
The input of the hex inverter connects the source electrode of second NMOS tube, the output end connection of the hex inverter
The input of 7th phase inverter；
The output end of 7th phase inverter connects the output end.
14. a kind of chip system of liquid crystal display, it is characterised in that including：Main control chip and driving chip；
The driving chip includes：Imput output circuit described in logical gate circuit and claim 13, the input and output
The drive end of circuit connects the main control chip, and the output end of the imput output circuit connects the logic section of the driving chip
The input of parallel circuit, the output end of the logical gate circuit of the driving chip be suitable to export the enable signal sum it is believed that
Number.
15. a kind of control method of imput output circuit, it is characterised in that the imput output circuit includes：First PMOS,
First NMOS tube, the second PMOS and the second NMOS tube, the drain electrode of the source electrode of first PMOS and second NMOS tube
It is adapted to input supply voltage, the drain electrode of the source electrode of first NMOS tube and second PMOS is adapted to input ground electricity
Pressure, source electrode, the drain electrode of the first NMOS tube and the second PMOS of drain electrode connection second NMOS tube of first PMOS
Source electrode, the size of first PMOS and the second NMOS tube is 1/15~1/7, first NMOS tube and second than scope
The size of PMOS is 1/15~1/7 than scope, and the control method of the imput output circuit includes：
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube is controlled to be in cut-off state；
Control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the second PMOS at
In cut-off state；
Control that first PMOS and the second NMOS tube are in cut-off state and the first NMOS tube and the second PMOS are in and led
Logical state.
16. a kind of control method of imput output circuit, it is characterised in that the imput output circuit includes：First PMOS,
First NMOS tube, the second PMOS and the second NMOS tube, the source electrode of first PMOS are suitable to input supply voltage, and described the
The source electrode of one NMOS tube is suitable to input ground voltage, the drain electrode of drain electrode connection second NMOS tube of first PMOS, institute
The source electrode for stating the second NMOS tube connects the source electrode of second PMOS, the drain electrode connection described first of second PMOS
The size of the drain electrode of NMOS tube, first PMOS and the second NMOS tube is 1/15~1/7, first NMOS tube than scope
Than scope it is 1/15~1/7 with the size of the second PMOS, the control method of the imput output circuit includes：
First PMOS, the first NMOS tube, the second PMOS and the second NMOS tube is controlled to be in cut-off state；
Control first PMOS and the second NMOS tube is in the conduction state and first NMOS tube and the second PMOS at
In cut-off state；
Control that first PMOS and the second NMOS tube are in cut-off state and the first NMOS tube and the second PMOS are in and led
Logical state.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410857343.XA CN104485083B (en) | 2014-12-30 | 2014-12-30 | The chip system of imput output circuit and its control method and liquid crystal display |
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| CN201410857343.XA CN104485083B (en) | 2014-12-30 | 2014-12-30 | The chip system of imput output circuit and its control method and liquid crystal display |
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| JP4992359B2 (en) * | 2006-09-15 | 2012-08-08 | 富士電機株式会社 | Display drive device |
| JP2008158226A (en) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | Output circuit and liquid crystal display device |
| CN102662426B (en) * | 2012-05-07 | 2013-11-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Output driving circuit with self electrostatic discharge (ESD) protection function |
| CN102969703B (en) * | 2012-10-31 | 2015-04-22 | 中国航天科技集团公司第九研究院第七七一研究所 | Input/output circuit with self electronic static discharge (ESD) protection function |
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