CN104485083A - Input-output circuit, control method of input-output circuit and liquid crystal display chip system - Google Patents
Input-output circuit, control method of input-output circuit and liquid crystal display chip system Download PDFInfo
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- CN104485083A CN104485083A CN201410857343.XA CN201410857343A CN104485083A CN 104485083 A CN104485083 A CN 104485083A CN 201410857343 A CN201410857343 A CN 201410857343A CN 104485083 A CN104485083 A CN 104485083A
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Abstract
The invention discloses an input-output circuit, a control method of the input-output circuit and a liquid crystal display chip system. The dimension ratio of a first PMOS transistor to a second NMOS transistor ranges from 1/15 to 1/7. The dimension ratio of a first NMOS transistor to a second PMOS transistor ranges from 1/15 to 1/7. A control unit is applicable to controlling the first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor to be in the off state, or controlling the first PMOS transistor and the second NMOS transistor to be in the on state and controlling the first NMOS transistor and the second PMOS transistor to be in the off state, or controlling the first PMOS transistor and the second NMOS transistor to be in the off state and controlling the first NMOS transistor and the second PMOS transistor to be in the on state.
Description
Technical field
The present invention relates to electronic applications, particularly relate to the chip system of a kind of imput output circuit and control method and liquid crystal display.
Background technology
Imput output circuit is the bridge that in chip and system, other chip is mutual, is responsible for receiving the control signal that main control chip sends over, or to main signal feedback status information.
At Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) in driving chip, the steering order that main control chip sends and image data, can be received by imput output circuit and come; When main control chip reads the information of TFT-LCD driving chip, be also feed back to main control chip by imput output circuit.The quality of imput output circuit design, directly has influence on the speed of chip reception or feedback information.In addition, what send due to imput output circuit or receive is an AC signal constantly just changed, and designs unreasonable, can produce electromagnetic interference (EMI) (Electro MagneticInterference, EMI), the normal work of other chip in influential system.
Fig. 1 is a kind of existing imput output circuit, comprising: PMOS P1, NMOS tube N1, the first phase inverter INV1, the second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4, the 5th phase inverter INV5, hex inverter INV6, the 7th phase inverter INV7, Sheffer stroke gate NAND1, rejection gate NOR1, total input end DB and output terminal DOUT.
Existing imput output circuit has two kinds of mode of operations: as enable signal EN=0, under being in input pattern, from the signal that total input end DB inputs, is input to chip internal through hex inverter INV6 and the 7th phase inverter INV7 by output terminal DOUT.At that time can signal EN=1 time, under being in output mode, the data-signal Data sent from chip internal and enable signal EN is through combinational logic Sheffer stroke gate NAND1, rejection gate NOR1, the first phase inverter INV1, the second phase inverter INV2, the 3rd phase inverter INV3, the 4th phase inverter INV4 and the 5th phase inverter INV5, control PMOS P1 and NMOS tube N1, realize data-signal Data signal to output on total input end DB.
But; existing input brings out circuit; because PMOS P1 and NMOS tube N1 will do ESD protection circuit simultaneously; so their size do very large; but under output mode, total input end DB often there will be overshoot phenomenon, as shown in Figure 2; overshoot signal is fast one of source of electromagnetic interference (EMI).
In addition, under general LCD driving chip technique, the sectional view of PMOS P1, as shown in Figure 3.The triode that existence one is parasitic in this sectional view, as shown in Figure 4.Because total input end DB is connected on pin, under the interference in the external world, the voltage that there will be total input end DB is greater than the situation of a supply voltage VDD PN junction voltage, cause parasitic triode conducting, form path between the substrate of total input end DB to connection low-voltage VGL, affect the stability of whole driving chip.
Summary of the invention
The problem that the present invention solves is that existing input brings out circuit and is vulnerable to electromagnetic interference (EMI).
For solving the problem, technical solution of the present invention provides a kind of imput output circuit, comprising: the first PMOS, the first NMOS tube, the second PMOS, the second NMOS tube, drive end and control module;
The source electrode of described first PMOS and the drain electrode of described second NMOS tube are all suitable for input supply voltage, the source electrode of described first NMOS tube and the drain electrode of described second PMOS are all suitable for inputting ground voltage, and the drain electrode of described first PMOS connects the source electrode of described second NMOS tube, the drain electrode of the first NMOS tube, the source electrode of the second PMOS and drive end;
The size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope;
The size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope;
Described control module is suitable for controlling described first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube and is in cut-off state, or control described first PMOS and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state, or control described first PMOS and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state.
Optionally, described control module is suitable for controlling described first PMOS when enable signal is the first level, first NMOS tube, second PMOS and the second NMOS tube are in cut-off state, described first PMOS is controlled and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state when described enable signal is second electrical level and data-signal is second electrical level, described first PMOS is controlled and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state when described enable signal is second electrical level and data-signal is the first level.
Optionally, described control module comprises: with arithmetic element or arithmetic element, the first phase inverter and the second phase inverter;
Describedly be suitable for carrying out and calculation process described data-signal and enable signal with arithmetic element, be describedly connected the input end of described first phase inverter and the grid of the second NMOS tube with the output terminal of arithmetic element;
Described or arithmetic element is suitable for carrying out NOR-operation process to the inversion signal of described data-signal and described enable signal, and output terminal that is described or arithmetic element connects the input end of described second phase inverter and the grid of the second PMOS;
The output terminal of described first phase inverter connects the grid of described first PMOS;
The output terminal of described second phase inverter connects the grid of described first NMOS tube.
Optionally, describedly to comprise with arithmetic element: Sheffer stroke gate and the 3rd phase inverter;
The first input end of described Sheffer stroke gate is suitable for inputting described enable signal, and the second input end of described Sheffer stroke gate is suitable for inputting described data-signal, and the output terminal of described Sheffer stroke gate connects the input end of described 3rd phase inverter;
The output terminal of described 3rd phase inverter connects the input end of described first phase inverter.
Optionally, described or arithmetic element comprises: the 4th phase inverter, rejection gate and the 5th phase inverter;
The input end of described 4th phase inverter is suitable for inputting described enable signal, and the output terminal of described 4th phase inverter connects the first end of described rejection gate;
Second input end of described rejection gate is suitable for inputting described data-signal, and the output terminal of described rejection gate connects the input end of described 5th phase inverter;
The output terminal of described 5th phase inverter connects the input end of described second phase inverter.
Optionally, described imput output circuit also comprises: output terminal, hex inverter and the 7th phase inverter;
The input end of described hex inverter connects the source electrode of described second NMOS tube, and the output terminal of described hex inverter connects the input end of described 7th phase inverter;
The output terminal of described 7th phase inverter connects described output terminal.
Technical solution of the present invention also provides a kind of chip system of liquid crystal display, comprising: main control chip and driving chip;
Described driving chip comprises: above-mentioned imput output circuit and logical gate circuit, the drive end of described imput output circuit connects described main control chip, the output terminal of described imput output circuit connects the input end of the logical gate circuit of described driving chip, and the output terminal of the logical gate circuit of described driving chip is suitable for exporting described enable signal and data-signal.
Technical solution of the present invention also provides a kind of imput output circuit, comprising: the first PMOS, the first NMOS tube, the second PMOS, the second NMOS tube, drive end and control module;
The source electrode of described first PMOS is suitable for input supply voltage, the source electrode of described first NMOS tube is suitable for inputting ground voltage, the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, the source electrode of described second NMOS tube connects source electrode and the drive end of described second PMOS, and the drain electrode of described second PMOS connects the drain electrode of described first NMOS tube;
The size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope;
The size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope;
Described control module is suitable for controlling described first PMOS when enable signal is the first level, first NMOS tube, second PMOS and the second NMOS tube are in cut-off state, described first PMOS is controlled and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state when described enable signal is second electrical level and data-signal is second electrical level, described first PMOS is controlled and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state when described enable signal is second electrical level and data-signal is the first level.
Optionally, described control module is suitable for controlling described first PMOS when enable signal is the first level, first NMOS tube, second PMOS and the second NMOS tube are in cut-off state, described first PMOS is controlled and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state when described enable signal is second electrical level and data-signal is second electrical level, described first PMOS is controlled and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state when described enable signal is second electrical level and data-signal is the first level.
Optionally, described control module comprises: with arithmetic element or arithmetic element, the first phase inverter and the second phase inverter;
Describedly be suitable for carrying out and calculation process data-signal and enable signal with arithmetic element, be describedly connected the input end of described first phase inverter and the grid of the second NMOS tube with the output terminal of arithmetic element;
Described or arithmetic element is suitable for carrying out NOR-operation process to the inversion signal of described data-signal and described enable signal, and output terminal that is described or arithmetic element connects the input end of described second phase inverter and the grid of the second PMOS;
The output terminal of described first phase inverter connects the grid of described first PMOS;
The output terminal of described second phase inverter connects the grid of described first NMOS tube.
Optionally, describedly to comprise with arithmetic element: Sheffer stroke gate and the 3rd phase inverter;
The first input end of described Sheffer stroke gate is suitable for inputting described enable signal, and the second input end of described Sheffer stroke gate is suitable for inputting described data-signal, and the output terminal of described Sheffer stroke gate connects the input end of described 3rd phase inverter;
The output terminal of described 3rd phase inverter connects the input end of described first phase inverter.
Optionally, described or arithmetic element comprises: the 4th phase inverter, rejection gate and the 5th phase inverter;
The input end of described 4th phase inverter is suitable for inputting described enable signal, and the output terminal of described 4th phase inverter connects the first end of described rejection gate;
Second input end of described rejection gate is suitable for inputting described data-signal, and the output terminal of described rejection gate connects the input end of described 5th phase inverter;
The output terminal of described 5th phase inverter connects the input end of described second phase inverter.
Optionally, described imput output circuit also comprises: output terminal, hex inverter and the 7th phase inverter;
The input end of described hex inverter connects the source electrode of described second NMOS tube, and the output terminal of described hex inverter connects the input end of described 7th phase inverter;
The output terminal of described 7th phase inverter connects described output terminal.
Technical solution of the present invention also provides a kind of chip system of liquid crystal display, comprising: main control chip and driving chip;
Described driving chip comprises: above-mentioned imput output circuit and logical gate circuit, the drive end of described imput output circuit connects described main control chip, the output terminal of described imput output circuit connects the input end of the logical gate circuit of described driving chip, and the output terminal of the logical gate circuit of described driving chip is suitable for exporting described enable signal and data-signal.
Technical solution of the present invention also provides a kind of control method of imput output circuit, described imput output circuit comprises: the first PMOS, first NMOS tube, second PMOS and the second NMOS tube, the source electrode of described first PMOS and the drain electrode of described second NMOS tube are all suitable for input supply voltage, the source electrode of described first NMOS tube and the drain electrode of described second PMOS are all suitable for inputting ground voltage, the drain electrode of described first PMOS connects the source electrode of described second NMOS tube, the drain electrode of the first NMOS tube and the source electrode of the second PMOS, the size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope, the size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope, the control method of described imput output circuit comprises:
Control described first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube and be in cut-off state;
Control described first PMOS and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state;
Control described first PMOS and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state.
Technical solution of the present invention also provides a kind of control method of imput output circuit, described imput output circuit comprises: the first PMOS, first NMOS tube, second PMOS and the second NMOS tube, the source electrode of described first PMOS is suitable for input supply voltage, the source electrode of described first NMOS tube is suitable for inputting ground voltage, the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, the source electrode of described second NMOS tube connects the source electrode of described second PMOS, the drain electrode of described second PMOS connects the drain electrode of described first NMOS tube, the size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope, the size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope, the control method of described imput output circuit comprises:
Control described first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube and be in cut-off state;
Control described first PMOS and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state;
Control described first PMOS and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state.
Compared with prior art, the large scale PMOS adopted in existing imput output circuit and NMOS are all split into NMOS tube and the PMOS of proper ratio by the imput output circuit of technical solution of the present invention, and utilize small size PMOS and NMOS tube to bear the final stage of output voltage pullup or pulldown, prevent output signal overshooting problem, effectively avoid electromagnetic interference problem.Further, reduce the size of parasitic triode, output voltage is shaken the underlayer voltage shake caused and also can significantly be reduced, and chip is more stable.
Accompanying drawing explanation
Fig. 1 is existing inputting and outputting circuit structure schematic diagram;
Fig. 2 is the signal output waveform schematic diagram of existing imput output circuit;
Fig. 3 is the sectional view of PMOS in existing imput output circuit;
Fig. 4 is parasitic triode schematic diagram in existing imput output circuit;
Fig. 5 is imput output circuit one structural representation of the embodiment of the present invention;
Fig. 6 is the signal output waveform schematic diagram of the imput output circuit of the embodiment of the present invention;
Fig. 7 is another structural representation of imput output circuit of the embodiment of the present invention;
Fig. 8 is imput output circuit one structural representation of another embodiment of the present invention;
Fig. 9 is another structural representation of imput output circuit of another embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
As shown in Figure 5, the embodiment of the present invention provides a kind of imput output circuit, comprising: the first PMOS P1, the first NMOS tube N1, the second PMOS P2, the second NMOS tube N2, drive end DB and control module.Described control module comprises: with arithmetic element 1 or arithmetic element 2, first phase inverter INV1 and the second phase inverter INV2.
The source electrode of described first PMOS P1 and the drain electrode of described second NMOS tube N2 are all suitable for input supply voltage VDD, the source electrode of described first NMOS tube N1 and the drain electrode of described second PMOS P2 are all suitable for input ground voltage GND, and the drain electrode of described first PMOS P1 connects the source electrode of described second NMOS tube N2, the drain electrode of the first NMOS tube N1, the source electrode of the second PMOS P2 and drive end DB.
The size of described first PMOS P1 and the second NMOS tube N2 is 1/15 ~ 1/7 than scope, and the size of described first NMOS tube N1 and the second PMOS P2 is 1/15 ~ 1/7 than scope.Such as, the size of described first PMOS P1 and the second NMOS tube N2 is the 1/9, first NMOS tube N1 with the size of the second PMOS P2 than scope than scope is also 1/9.
Described control module is suitable for controlling described first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 and is in cut-off state, or control described first PMOS P1 and the second NMOS tube N2 and be in conducting state and described first NMOS tube N1 and the second PMOS P2 is in cut-off state, or control described first PMOS P1 and the second NMOS tube N2 and be in cut-off state and the first NMOS tube N1 and the second PMOS P2 is in conducting state.
Concrete, described control module is suitable for controlling described first PMOS P1 when enable signal EN is the first level, first NMOS tube N1, second PMOS P2 and the second NMOS tube N2 is in cut-off state, described first PMOS P1 is controlled and the second NMOS tube N2 pipe is in conducting state and described first NMOS tube N1 and the second PMOS P2 is in cut-off state when described enable signal EN is second electrical level and data-signal DATA is second electrical level, control described first PMOS P1 and the second NMOS tube N2 when described enable signal EN is second electrical level and data-signal DATA is the first level and be in cut-off state and the first NMOS tube N1 and the second PMOS P2 is in conducting state.
In the present embodiment, described control module can comprise: with arithmetic element 1 or arithmetic element 2, first phase inverter INV1 and the second phase inverter INV2.Describedly be suitable for carrying out and calculation process data-signal DATA and enable signal EN with arithmetic element 1, be describedly connected the described input end of the first phase inverter INV1 and the grid of the second NMOS tube N2 with the output terminal of arithmetic element 1.
Described or arithmetic element 2 is suitable for carrying out NOR-operation process to the inversion signal of described data-signal DATA and described enable signal EN, and output terminal that is described or arithmetic element 2 connects the described input end of the second phase inverter INV2 and the grid of the second PMOS P2.
The output terminal of described first phase inverter INV1 connects the grid of described first PMOS P1, and the output terminal of described second phase inverter INV2 connects the grid of described first NMOS tube N1.
Described output imput output circuit can also comprise: output terminal DOUT.Described output terminal DOUT connects the source electrode of described second NMOS tube N2.
Following examples all with the first level for low level signal " 0 ", second electrical level is high level signal " 1 " for example is described.
As enable signal EN=0, described imput output circuit is in input pattern:
No matter Data=1 or 0, with arithmetic element 1 output low level signal to the second NMOS tube N2 grid, first phase inverter INV1 exports high level signal to the first PMOS P1 grid, or arithmetic element exports high level signal to the second PMOS P2 grid, second phase inverter INV2 output low level signal to the first NMOS tube N1 grid, the first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 are all in cut-off state; The signal inputted from drive end DB is exported by output terminal DOUT.
As enable signal EN=1, described imput output circuit is in output mode:
When Data=1, export high level signal to the second NMOS tube N2 grid with arithmetic element 1, the first phase inverter INV1 output low level signal to the first PMOS P1 grid, the first PMOS P1 and the second NMOS tube N2 is all in conducting state; Further, or arithmetic element exports high level signal to the second PMOS P2 grid, the second phase inverter INV2 output low level signal to the first NMOS tube N1 grid, and the first NMOS tube N1 and the second PMOS P2 is all in cut-off state;
When Data=0, with arithmetic element 1 output low level signal to the second NMOS tube N2 grid, the first phase inverter INV1 exports high level signal to the first PMOS P1 grid, and the first PMOS P1 and the second NMOS tube N2 is all in cut-off state; Further, or arithmetic element output low level signal to the second PMOS P2 grid, the second phase inverter INV2 exports high level signal to the first NMOS tube N1 grid, and the first NMOS tube N1 and the second PMOS P2 is all in conducting state.
In the output mode of the present embodiment, during Data=1, voltage on drive end DB changes from low to high, during the starting stage, because undersized first PMOS P1 and large-sized second NMOS tube N2 (size is 1/15 ~ 1/7 than scope) is all in conducting state, so the voltage of drive end DB rises fast.But the second NMOS tube N2 can only be driven into drive end DB the amplitude that supply voltage VDD subtracts a threshold value, namely (VDD represents the magnitude of voltage of supply voltage to VDD-VTH1, VTH1 represents the threshold voltage value of the second NMOS tube N2), and VDD-VTH1 to the VDD stage can only lean on undersized first PMOS P1 to drive.Small-sized due to the first PMOS P1, can not cause the phenomenon of upwards overshoot on drive end DB.
In like manner, work as Data=0, the voltage on drive end DB changes from high to low, during the starting stage, because undersized first NMOS tube N1 and large-sized second PMOS P2 (size is 1/15 ~ 1/7 than scope) is all in conducting state, so the voltage of drive end DB declines fast.But because the second PMOS P2 can only pull down to drive end DB the current potential (VTH2 represents the threshold voltage value of the second PMOS P2) that liftoff voltage GND differs from a threshold value VTH2, VTH2 to ground voltage GND can only lean on the first NMOS tube N1 drop-down to complete.Small-sized due to the first NMOS tube N1, can not cause the phenomenon of downward overshoot on drive end DB.
Fig. 6 gives the present embodiment imput output circuit under output mode, the waveform of output signal on drive end DB, and as can be seen from waveform, output signal is not having overshoot phenomenon, thus effectively avoids electromagnetic interference (EMI) (EMI) problem.
Meanwhile, due to the first PMOS P1 size comparatively prior art diminish, the size of parasitic triode obviously diminishes, so under external interference, drive end DB shake cause underlayer voltage shake also can significantly reduce, chip is more stable.
As shown in Figure 7, can comprise with arithmetic element 1 described in the present embodiment: Sheffer stroke gate NAND and the 3rd phase inverter INV3.
The first input end of described Sheffer stroke gate NAND is suitable for inputting described enable signal EN, and second input end of described Sheffer stroke gate NAND is suitable for inputting described data-signal DATA, and the output terminal of described Sheffer stroke gate NAND connects the input end of described 3rd phase inverter INV3.The output terminal of described 3rd phase inverter INV3 connects the input end of described first phase inverter INV1.
Described or arithmetic element 2 comprises: the 4th phase inverter INV4, rejection gate NOR and the 5th phase inverter INV5.
The input end of described 4th phase inverter INV4 is suitable for inputting described enable signal EN, and the output terminal of described 4th phase inverter INV4 connects the first end of described rejection gate NOR.Second input end of described rejection gate NOR is suitable for inputting described data-signal DATA, and the output terminal of described rejection gate NOR connects the input end of described 5th phase inverter INV5.The output terminal of described 5th phase inverter INV5 connects the input end of described second phase inverter INV2.
Described imput output circuit can also comprise: hex inverter INV6 and the 7th phase inverter INV7.Described output terminal DOUT to be connected the source electrode of the second NMOS tube N2 by the hex inverter INV6 of series connection with the 7th phase inverter INV7.Concrete, the input end of described hex inverter INV6 connects the source electrode of described second NMOS tube N2, the output terminal of described hex inverter INV6 connects the input end of described 7th phase inverter INV7, and the output terminal of described 7th phase inverter INV7 connects described output terminal DOUT.
As shown in Figure 8, another this enforcement of the present invention also provides a kind of imput output circuit, and described imput output circuit comprises: the first PMOS P1, the first NMOS tube N1, the second PMOS P2, the second NMOS tube N2, drive end DB and control module.
The source electrode of described first PMOS P1 is suitable for input supply voltage VDD, the source electrode of described first NMOS tube N1 is suitable for input ground voltage GND, the drain electrode of described first PMOS P1 connects the drain electrode of described second NMOS tube N2, the source electrode of described second NMOS tube N2 connects the drain electrode of the source electrode of described second PMOS P2 and the described first NMOS tube N1 of drain electrode connection of drive end DB, described second PMOS P2.
The size of described first PMOS P1 and the second NMOS tube N2 is 1/15 ~ 1/7 than scope, and the size of described first NMOS tube N1 and the second PMOS P2 is 1/15 ~ 1/7 than scope.Such as, the size of described first PMOS P1 and the second NMOS tube N2 is the 1/9, first NMOS tube N1 with the size of the second PMOS P2 than scope than scope is also 1/9.
Described control module is suitable for controlling described first PMOS P1 when enable signal EN is the first level, first NMOS tube N1, second PMOS P2 and the second NMOS tube N2 is in cut-off state, control described first PMOS P1 and the second NMOS tube N2 when described enable signal EN is second electrical level and data-signal DATA is second electrical level and be in conducting state and described first NMOS tube N1 and the second PMOS P2 is in cut-off state, control described first PMOS P1 and the second NMOS tube N2 when described enable signal EN is second electrical level and data-signal DATA is the first level and be in cut-off state and the first NMOS tube N1 and the second PMOS P2 is in conducting state.
Concrete, described control module is suitable for controlling described first PMOS P1 when enable signal EN is the first level, first NMOS tube N1, second PMOS P2 and the second NMOS tube N2 is in cut-off state, control described first PMOS P1 and the second NMOS tube N2 when described enable signal EN is second electrical level and data-signal DATA is second electrical level and be in conducting state and described first NMOS tube N1 and the second PMOS P2 is in cut-off state, control described first PMOS P1 and the second NMOS tube N2 when described enable signal EN is second electrical level and data-signal DATA is the first level and be in cut-off state and the first NMOS tube N1 and the second PMOS P2 is in conducting state.
In the present embodiment, described control module can comprise: with arithmetic element 1 or arithmetic element 2, first phase inverter INV1 and the second phase inverter INV2.
Describedly be suitable for carrying out and calculation process data-signal DATA and enable signal EN with arithmetic element 1, be describedly connected the described input end of the first phase inverter INV1 and the grid of the second NMOS tube N2 with the output terminal of arithmetic element 1.
Described or arithmetic element 2 is suitable for carrying out NOR-operation process to the inversion signal of described data-signal DATA and described enable signal EN, and output terminal that is described or arithmetic element 2 connects the described input end of the second phase inverter INV2 and the grid of the second PMOS P2.
The output terminal of described first phase inverter INV1 connects the grid of described first PMOS P1, and the output terminal of described second phase inverter INV2 connects the grid of described first NMOS tube N1.
Described output imput output circuit can also comprise: with output terminal DOUT.Output terminal DOUT connects the source electrode of described second NMOS tube N2.
As enable signal EN=0, described imput output circuit is in input pattern:
No matter Data=1 or 0, with arithmetic element 1 output low level signal to the second NMOS tube N2 grid, first phase inverter INV1 exports high level signal to the first PMOS P1 grid, or arithmetic element exports high level signal to the second PMOS P2 grid, second phase inverter INV2 output low level signal to the first NMOS tube N1 grid, the first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 are all in cut-off state; The signal inputted from drive end DB is exported by output terminal DOUT.
As enable signal EN=1, described imput output circuit is in output mode:
When Data=1, export high level signal to the second NMOS tube N2 grid with arithmetic element 1, the first phase inverter INV1 output low level signal to the first PMOS P1 grid, the first PMOS P1 and the second NMOS tube N2 is all in conducting state; Further, or arithmetic element exports high level signal to the second PMOS P2 grid, the second phase inverter INV2 output low level signal to the first NMOS tube N1 grid, and the first NMOS tube N1 and the second PMOS P2 is all in cut-off state;
When Data=0, with arithmetic element 1 output low level signal to the second NMOS tube N2 grid, the first phase inverter INV1 exports high level signal to the first PMOS P1 grid, and the first PMOS P1 and the second NMOS tube N2 is all in cut-off state; Further, or arithmetic element output low level signal to the second PMOS P2 grid, the second phase inverter INV2 exports high level signal to the first NMOS tube N1 grid, and the first NMOS tube N1 and the second PMOS P2 is all in conducting state.
Similar with a upper embodiment, in the output mode of the present embodiment, no matter be Data=1 or 0, bear last voltage pullup or pulldown by the first small-sized PMOS P1 and the first NMOS tube N1, so the phenomenon of overshoot up or down can not be caused on drive end DB.Equally, the size of parasitic triode obviously diminishes, so under external interference, drive end DB shakes the underlayer voltage shake caused and also can significantly reduce, and chip is more stable.
As shown in Figure 9, describedly to comprise with arithmetic element 1: Sheffer stroke gate NAND and the 3rd phase inverter INV3.
The first input end of described Sheffer stroke gate NAND is suitable for inputting described enable signal EN, and second input end of described Sheffer stroke gate NAND is suitable for inputting described data-signal DATA, and the output terminal of described Sheffer stroke gate NAND connects the input end of described 3rd phase inverter INV3; The output terminal of described 3rd phase inverter INV3 connects the input end of described first phase inverter INV1.
Described or arithmetic element 2 comprises: the 4th phase inverter INV4, rejection gate NOR and the 5th phase inverter INV5.
The input end of described 4th phase inverter INV4 is suitable for inputting described enable signal EN, and the output terminal of described 4th phase inverter INV4 connects the first end of described rejection gate NOR; Second input end of described rejection gate NOR is suitable for inputting described data-signal DATA, and the output terminal of described rejection gate NOR connects the input end of described 5th phase inverter INV5; The output terminal of described 5th phase inverter INV5 connects the input end of described second phase inverter INV2.
Described imput output circuit also comprises: hex inverter INV6 and the 7th phase inverter INV7.Described output terminal DOUT to be connected the source electrode of the second NMOS tube N2 by the hex inverter INV6 of series connection with the 7th phase inverter INV7.Concrete, the input end of described hex inverter INV6 connects the source electrode of described second NMOS tube N2, the output terminal of described hex inverter INV6 connects the input end of described 7th phase inverter INV7, and the output terminal of described 7th phase inverter INV7 connects described output terminal DOUT.
The embodiment of the present invention also provides a kind of chip system of liquid crystal display, comprising: main control chip and driving chip.
Described driving chip comprises: the imput output circuit of above-described embodiment and logical gate circuit, the drive end DB of described imput output circuit connects described main control chip, the output terminal DOUT of described imput output circuit connects the input end of the logical gate circuit of described driving chip, and the output terminal of the logical gate circuit of described driving chip is suitable for exporting described enable signal EN and data-signal DATA.Other part embodiments about main control chip and driving chip with reference to prior art, can repeat no more herein.
The embodiment of the present invention also provides a kind of control method of imput output circuit, described imput output circuit comprises: the first PMOS P1, first NMOS tube N1, second PMOS P2, second NMOS tube N2, the source electrode of described first PMOS P1 and the drain electrode of described second NMOS tube N2 are all suitable for input supply voltage VDD, the source electrode of described first NMOS tube N1 and the drain electrode of described second PMOS P2 are all suitable for input ground voltage GND, the drain electrode of described first PMOS P1 connects the source electrode of described second NMOS tube N2, the drain electrode of the first NMOS tube N1, the source electrode of the second PMOS P2, the size of described first PMOS P1 and the second NMOS tube N2 is 1/15 ~ 1/7 than scope, the size of described first NMOS tube N1 and the second PMOS P2 is 1/15 ~ 1/7 than scope, the control method of described imput output circuit comprises:
Control described first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 pipe and be in cut-off state;
Control described first PMOS P1 and the second NMOS tube N2 and be in conducting state and described first NMOS tube N1 and the second PMOS P2 is in cut-off state;
Control described first PMOS P1 and the second NMOS tube N2 and be in cut-off state and the first NMOS tube N1 and the second PMOS P2 is in conducting state.
The embodiment of the present invention also provides a kind of control method of imput output circuit, described imput output circuit comprises: the first PMOS P1, first NMOS tube N1, second PMOS P2, second NMOS tube N2, the source electrode of described first PMOS P1 is suitable for input supply voltage VDD, the source electrode of described first NMOS tube N1 is suitable for input ground voltage GND, the drain electrode of described first PMOS P1 connects the drain electrode of described second NMOS tube N2, the source electrode of described second NMOS tube N2 connects the source electrode of described second PMOS P2, the drain electrode of described second PMOS P2 connects the drain electrode of described first NMOS tube N1, the size of described first PMOS P1 and the second NMOS tube N2 is 1/15 ~ 1/7 than scope, the size of described first NMOS tube N1 and the second PMOS P2 is 1/15 ~ 1/7 than scope, the control method of described imput output circuit comprises:
Control described first PMOS P1, the first NMOS tube N1, the second PMOS P2 and the second NMOS tube N2 and be in cut-off state;
Control described first PMOS P1 and the second NMOS tube N2 and be in conducting state and described first NMOS tube N1 and the second PMOS P2 is in cut-off state;
Control described first PMOS P1 and the second NMOS tube N2 and be in cut-off state and the first NMOS tube N1 and the second PMOS P2 is in conducting state.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (16)
1. an imput output circuit, is characterized in that, comprising: the first PMOS, the first NMOS tube, the second PMOS, the second NMOS tube, drive end and control module;
The source electrode of described first PMOS and the drain electrode of described second NMOS tube are all suitable for input supply voltage, the source electrode of described first NMOS tube and the drain electrode of described second PMOS are all suitable for inputting ground voltage, and the drain electrode of described first PMOS connects the source electrode of described second NMOS tube, the drain electrode of the first NMOS tube, the source electrode of the second PMOS and drive end;
The size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope;
The size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope;
Described control module is suitable for controlling described first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube and is in cut-off state, or control described first PMOS and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state, or control described first PMOS and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state.
2. imput output circuit as claimed in claim 1, it is characterized in that, described control module is suitable for controlling described first PMOS when enable signal is the first level, first NMOS tube, second PMOS and the second NMOS tube are in cut-off state, described first PMOS is controlled and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state when described enable signal is second electrical level and data-signal is second electrical level, described first PMOS is controlled and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state when described enable signal is second electrical level and data-signal is the first level.
3. imput output circuit as claimed in claim 2, it is characterized in that, described control module comprises: with arithmetic element or arithmetic element, the first phase inverter and the second phase inverter;
Describedly be suitable for carrying out and calculation process described data-signal and enable signal with arithmetic element, be describedly connected the input end of described first phase inverter and the grid of the second NMOS tube with the output terminal of arithmetic element;
Described or arithmetic element is suitable for carrying out NOR-operation process to the inversion signal of described data-signal and described enable signal, and output terminal that is described or arithmetic element connects the input end of described second phase inverter and the grid of the second PMOS;
The output terminal of described first phase inverter connects the grid of described first PMOS;
The output terminal of described second phase inverter connects the grid of described first NMOS tube.
4. imput output circuit as claimed in claim 3, is characterized in that, describedly comprises with arithmetic element: Sheffer stroke gate and the 3rd phase inverter;
The first input end of described Sheffer stroke gate is suitable for inputting described enable signal, and the second input end of described Sheffer stroke gate is suitable for inputting described data-signal, and the output terminal of described Sheffer stroke gate connects the input end of described 3rd phase inverter;
The output terminal of described 3rd phase inverter connects the input end of described first phase inverter.
5. imput output circuit as claimed in claim 3, it is characterized in that, described or arithmetic element comprises: the 4th phase inverter, rejection gate and the 5th phase inverter;
The input end of described 4th phase inverter is suitable for inputting described enable signal, and the output terminal of described 4th phase inverter connects the first end of described rejection gate;
Second input end of described rejection gate is suitable for inputting described data-signal, and the output terminal of described rejection gate connects the input end of described 5th phase inverter;
The output terminal of described 5th phase inverter connects the input end of described second phase inverter.
6. the imput output circuit as described in claim as arbitrary in claim 1 to 5, is characterized in that, also comprise: output terminal, hex inverter and the 7th phase inverter;
The input end of described hex inverter connects the source electrode of described second NMOS tube, and the output terminal of described hex inverter connects the input end of described 7th phase inverter;
The output terminal of described 7th phase inverter connects described output terminal.
7. a chip system for liquid crystal display, is characterized in that, comprising: main control chip and driving chip;
Described driving chip comprises: imput output circuit according to claim 6 and logical gate circuit, the drive end of described imput output circuit connects described main control chip, the output terminal of described imput output circuit connects the input end of the logical gate circuit of described driving chip, and the output terminal of the logical gate circuit of described driving chip is suitable for exporting described enable signal and data-signal.
8. an imput output circuit, is characterized in that, comprising: the first PMOS, the first NMOS tube, the second PMOS, the second NMOS tube, drive end and control module;
The source electrode of described first PMOS is suitable for input supply voltage, the source electrode of described first NMOS tube is suitable for inputting ground voltage, the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, the source electrode of described second NMOS tube connects source electrode and the drive end of described second PMOS, and the drain electrode of described second PMOS connects the drain electrode of described first NMOS tube;
The size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope;
The size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope;
Described control module is suitable for controlling described first PMOS when enable signal is the first level, first NMOS tube, second PMOS and the second NMOS tube are in cut-off state, described first PMOS is controlled and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state when described enable signal is second electrical level and data-signal is second electrical level, described first PMOS is controlled and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state when described enable signal is second electrical level and data-signal is the first level.
9. imput output circuit as claimed in claim 8, it is characterized in that, described control module is suitable for controlling described first PMOS when enable signal is the first level, first NMOS tube, second PMOS and the second NMOS tube are in cut-off state, described first PMOS is controlled and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state when described enable signal is second electrical level and data-signal is second electrical level, described first PMOS is controlled and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state when described enable signal is second electrical level and data-signal is the first level.
10. imput output circuit as claimed in claim 9, it is characterized in that, described control module comprises: with arithmetic element or arithmetic element, the first phase inverter and the second phase inverter;
Describedly be suitable for carrying out and calculation process data-signal and enable signal with arithmetic element, be describedly connected the input end of described first phase inverter and the grid of the second NMOS tube with the output terminal of arithmetic element;
Described or arithmetic element is suitable for carrying out NOR-operation process to the inversion signal of described data-signal and described enable signal, and output terminal that is described or arithmetic element connects the input end of described second phase inverter and the grid of the second PMOS;
The output terminal of described first phase inverter connects the grid of described first PMOS;
The output terminal of described second phase inverter connects the grid of described first NMOS tube.
11. imput output circuits as claimed in claim 10, is characterized in that, describedly comprise with arithmetic element: Sheffer stroke gate and the 3rd phase inverter;
The first input end of described Sheffer stroke gate is suitable for inputting described enable signal, and the second input end of described Sheffer stroke gate is suitable for inputting described data-signal, and the output terminal of described Sheffer stroke gate connects the input end of described 3rd phase inverter;
The output terminal of described 3rd phase inverter connects the input end of described first phase inverter.
12. imput output circuits as claimed in claim 10, it is characterized in that, described or arithmetic element comprises: the 4th phase inverter, rejection gate and the 5th phase inverter;
The input end of described 4th phase inverter is suitable for inputting described enable signal, and the output terminal of described 4th phase inverter connects the first end of described rejection gate;
Second input end of described rejection gate is suitable for inputting described data-signal, and the output terminal of described rejection gate connects the input end of described 5th phase inverter;
The output terminal of described 5th phase inverter connects the input end of described second phase inverter.
Imput output circuit as described in 13. claims as arbitrary in claim 8 to 12, is characterized in that, also comprise: output terminal, hex inverter and the 7th phase inverter;
The input end of described hex inverter connects the source electrode of described second NMOS tube, and the output terminal of described hex inverter connects the input end of described 7th phase inverter;
The output terminal of described 7th phase inverter connects described output terminal.
The chip system of 14. 1 kinds of liquid crystal display, is characterized in that, comprising: main control chip and driving chip;
Described driving chip comprises: imput output circuit according to claim 13 and logical gate circuit, the drive end of described imput output circuit connects described main control chip, the output terminal of described imput output circuit connects the input end of the logical gate circuit of described driving chip, and the output terminal of the logical gate circuit of described driving chip is suitable for exporting described enable signal and data-signal.
The control method of 15. 1 kinds of imput output circuits, it is characterized in that, described imput output circuit comprises: the first PMOS, first NMOS tube, second PMOS and the second NMOS tube, the source electrode of described first PMOS and the drain electrode of described second NMOS tube are all suitable for input supply voltage, the source electrode of described first NMOS tube and the drain electrode of described second PMOS are all suitable for inputting ground voltage, the drain electrode of described first PMOS connects the source electrode of described second NMOS tube, the drain electrode of the first NMOS tube and the source electrode of the second PMOS, the size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope, the size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope, the control method of described imput output circuit comprises:
Control described first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube and be in cut-off state;
Control described first PMOS and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state;
Control described first PMOS and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state.
The control method of 16. 1 kinds of imput output circuits, it is characterized in that, described imput output circuit comprises: the first PMOS, first NMOS tube, second PMOS and the second NMOS tube, the source electrode of described first PMOS is suitable for input supply voltage, the source electrode of described first NMOS tube is suitable for inputting ground voltage, the drain electrode of described first PMOS connects the drain electrode of described second NMOS tube, the source electrode of described second NMOS tube connects the source electrode of described second PMOS, the drain electrode of described second PMOS connects the drain electrode of described first NMOS tube, the size of described first PMOS and the second NMOS tube is 1/15 ~ 1/7 than scope, the size of described first NMOS tube and the second PMOS is 1/15 ~ 1/7 than scope, the control method of described imput output circuit comprises:
Control described first PMOS, the first NMOS tube, the second PMOS and the second NMOS tube and be in cut-off state;
Control described first PMOS and the second NMOS tube is in conducting state and described first NMOS tube and the second PMOS are in cut-off state;
Control described first PMOS and the second NMOS tube is in cut-off state and the first NMOS tube and the second PMOS are in conducting state.
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| CN104485083B (en) | 2017-09-08 |
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