CN104481503B - A kind of acquisition control circuit and well logging apparatus applied to acoustic logging while drilling instrument - Google Patents
A kind of acquisition control circuit and well logging apparatus applied to acoustic logging while drilling instrument Download PDFInfo
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- CN104481503B CN104481503B CN201410641095.5A CN201410641095A CN104481503B CN 104481503 B CN104481503 B CN 104481503B CN 201410641095 A CN201410641095 A CN 201410641095A CN 104481503 B CN104481503 B CN 104481503B
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- dsp
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Classifications
-
- E—FIXED CONSTRUCTIONS
- E21—EARTH DRILLING; MINING
- E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B47/00—Survey of boreholes or wells
-
- E—FIXED CONSTRUCTIONS
- E21—EARTH DRILLING; MINING
- E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B47/00—Survey of boreholes or wells
- E21B47/12—Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling
- E21B47/14—Means for transmitting measuring-signals or control signals from the well to the surface, or from the surface to the well, e.g. for logging while drilling using acoustic waves
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- E—FIXED CONSTRUCTIONS
- E21—EARTH DRILLING; MINING
- E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B49/00—Testing the nature of borehole walls; Formation testing; Methods or apparatus for obtaining samples of soil or well fluids, specially adapted to earth drilling or wells
Abstract
The present invention relates to a kind of acquisition control circuit and well logging apparatus applied to acoustic logging while drilling, the circuit includes：Digital signal processor DSP, at least one programmable gate array device FPGA, simulation and digital quantizer ADC and memory cell；Wherein, DSP is by controlling FPGA to be controlled ADC；FPGA is sampled the ADC data gathered, and sampled data is transferred into DSP, and sampled data is analyzed and processed DSP and the setting of agreement, then the data that protocol is carried after processing are arrived into memory cell by FPGA storages.Acquisition control circuit of the present invention has not only given full play to the strong advantage of DSP data processing functions, and by FPGA control sequentials precisely, rich interface the characteristics of show, improve the control accuracy of time, significantly reduce the space-consuming of circuit board.
Description
Technical field
The present invention relates to acoustic logging while drilling instrument technology, more particularly to a kind of collection control applied to acoustic logging while drilling instrument
Circuit and well logging apparatus processed.
Background technology
Oil gas drilling measurement in oil complex environment is with well logging, including the well logging ratio tradition of acoustic logging while drilling
Wireline logging there are more advantages, it be drilling well simultaneously measurement stratum petrophysical parameter, reduce log-time；Survey
Well data measures before mud immerses stratum or when immersing very shallow, can more realistically reflect that the geology of undisturbed formation is special
Sign, while the information of drilled strata can be predicted, uncertainty is substantially reduced, help engineer is timely, effectively carries out decision-making,
Drilling well is preferably instructed, drill bit is crept on favourable stratum, reduces drilling risk.
At present, well logging can carry out almost all of wireline logging project, and its application is constantly expanding.State
Outside, at sea, almost all of bore hole logging operation all uses logging while drilling technology；On land, particularly high angle hole and
Horizontal well, based on use logging while drilling technology.In addition, the variation of well logging method, such as with brill sound, electricity, nuclear-magnetism, stratum
The methods of test, has all occurred, and is inevitable outcome with the comprehensive replacement cables well logging of formation evaluation is bored thus.
The world is with the brill market share and technology by Schlumberger, the absolute ridge of Halliburton and Bake Hughes Deng Ji major companies
Disconnected, especially the market share of Schlumberger is always 50% or so, next to that Halliburton, hovers 30% or so, Bake
Hughes also has 14% or so share, and the market for leaving the country for is only left less than 1%.And domestic logging while drilling technology also not into
It is ripe, thus the R＆D intensity for increasing this technology is imperative.
Most domestic acoustic logging while drilling circuit design is generally separated with storing by acquisition control, so not only increases
Control complexity is added, while the design of more plates connection occupies larger space.Also there is individually setting using DSP or FPGA
Meter, wherein DSP is skillful in the realization of algorithm, but interface is more fixed；FPGA can conveniently realize the conversion of interface communication, but related
The integrating process of algorithm is complex, is not easy to realize.
The content of the invention
The present invention in view of the above-mentioned problems existing in the prior art, with acoustic logging while drilling instrument acquisition control circuit design and
It is embodied as point of penetration, has researched and analysed its realization principle, and provides a kind of more succinct acoustic logging while drilling instrument collection control
The design of circuit processed, the space-consuming of circuit can be significantly saved, while cause control logic more simple and clear, also easily
In realization.
To achieve the above object, on the one hand, the invention provides a kind of acquisition control electricity applied to acoustic logging while drilling
Road, the phone include：Digital signal processor (Digital Signal Process, abbreviation DSP), at least one may be programmed are patrolled
Collect gate array device (Field-Programmable Gate Array, abbreviation FPGA), simulation and digital quantizer
(Analog-to-digital converter, abbreviation ADC) and memory cell；Wherein, DSP is by controlling FPGA to carry out ADC
Control；FPGA is sampled the ADC data gathered, and sampled data is transferred into DSP, and DSP is analyzed sampled data
Processing and the setting of agreement, and the data that protocol is carried after processing are arrived into memory cell by FPGA storages.
Preferably, DSP and FPGA is communicated by HPI interfaces and/or MCBSP interfaces.
Preferably, memory cell design uses NAND Flash chip of the two panels capacity for 2G.
Preferably, DSP includes dynamic random access memory DRAM, DRAM and is used for the hits that storage is sent by FPGA
According to.
Preferably, FPGA includes fifo data buffer, and for ADC while gathered data, data are directly placed into FIFO
Data buffer；FPGA voluntarily detects the state of fifo data buffer, when for non-null states when, data are delayed from data fifo
Rush in device and read and write in the DRAM addresses that DSP is specified.
Preferably, DSP is used to sampled data be identified, and DSP will identify the maximum of every road signal, when maximum height
When upper threshold ident value, will be turned down by automatically controlling gain code by one grade；When maximum is less than lower threshold ident value, one is tuned up
Shelves.
Preferably, ADC is used to gather 4 tunnel analog signals simultaneously, and per pass waveform produces 3000*16 bits in each cycle
Data volume, 4 all produce the data volume of 4*3000*16 bits, and collection is passed these data by the FPGA after completing
It is defeated into the DSP.
Preferably, the data write storage unit that logical sequence gathers ADC is write in FPGA controls, in write storage unit
During, control the interval of write-in.
Preferably, the circuit also includes host computer, and DSP is when receiving the reading order that host computer issues, under FPGA
The read command of memory cell is sent out, FPGA controls read logical sequence and read out the data in memory cell by page.
Preferably, DSP is specifically used for, and data phase is extracted on ground, and DSP receives related command, and control FPGA will be stored
Digital independent in unit is out and synchronous transfer is to host computer real-time display.
On the other hand, the invention provides a kind of well logging apparatus, the device to include receiving circuit, receive transducer, transmitting
Circuit, transmitting transducer and power circuit, in addition to the above-mentioned acquisition control circuit applied to acoustic logging while drilling.
Acquisition control circuit of the present invention has not only given full play to the strong advantage of DSP data processing functions, and FPGA is controlled
The characteristics of sequential processed is accurate, rich interface shows, and improves the control accuracy of time, significantly reduces accounting for for circuit board
Use space.
Brief description of the drawings
Fig. 1 is a kind of well logging apparatus structural representation provided in an embodiment of the present invention；
Fig. 2 is that a kind of acquisition control circuit structure applied to acoustic logging while drilling circuit provided in an embodiment of the present invention is shown
It is intended to；
Fig. 3 is ADC portion control sequential figure of the present invention；
The basic structure schematic diagram that Fig. 4 is communicated between DSP of the present invention and ADC；
Fig. 5 is the FPGA and NAND Flash attachment structure schematic diagrams that invention is related to；
Embodiment
After embodiments of the present invention are described in detail by way of example below in conjunction with accompanying drawing, of the invention its
His characteristics, features and advantages will be more obvious.
Fig. 1 is a kind of well logging apparatus structural representation provided in an embodiment of the present invention.As shown in figure 1, the well logging apparatus is certainly
Include acquisition control circuit 10, receiving circuit 80, radiating circuit 81, receive transducer 82, the and of power circuit 83 under above successively
The core that radiating circuit transducer 84, wherein acquisition control circuit 10 work as whole circuit, passes through serial order etc.
Mode controls the working condition of whole device.Receiving circuit 80 is connected with receive transducer 82, completes analog filtering, gain control
The functions such as system.Radiating circuit 81 is directly connected with transmitting transducer 84, regularly provides high-voltage pulse, power supply for transmitting transducer 84
Circuit 83 connects acquisition control circuit 10, and power supply is provided for it.
Fig. 2 is that a kind of acquisition control circuit structure applied to acoustic logging while drilling circuit provided in an embodiment of the present invention is shown
It is intended to, as shown in Fig. 2 the circuit includes DSP20, FPGA21, FPGA22, ADC23, NAND flash24 and host computer 25, should
Circuit uses DSP and FPGA joint framework, and both advantages carry out complementation, pass through the parallel interface (Host with main-machine communication
Port Interface, abbreviation HPI) and multichannel buffer serial port (Multichannel buffered serial
Port, abbreviation MCBSP) interface communicated, realize synchronous acquisition, storage, the function such as control and preliminary data processing.
Resource is expanded in periphery includes ADC23, NAND flash24 chips etc., and wherein DSP20 completes order control, time control as main
Work, FPGA21 and the FPGA22 such as the preliminary treatment of system and data are mainly as the communication bridge between DSP20 and other chips
Beam, it is integrated with universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, abbreviation
UART), the kernel such as HPI, MCBSP and controller local area network (Controller Area Network, CAN), complete corresponding
Interface conversion and command interpretation.Memory cell of the NAND Flash24 as data, it is big with memory capacity, it is not easy to be lost,
The advantages that speed is fast, design use chip of the two panels capacity for 2G.Various pieces cooperate, complete from collection, storage, from
Reason arrives all processes that packing uploads again, can select different mode of operations according to demand.
First, DSP20 is sampled the signal received by controlling FPGA21 to be controlled ADC23, simultaneously should
Sampled data is transferred in DSP20 DRAM by HPI interfaces, and then DSP20 reads data from DRAM and data are carried out
The setting of analyzing and processing and related protocol；Afterwards, these are passed through into FPGA21 by handling and carrying the data of protocol
NAND flash24 chips are stored, thus complete the control circulation of underground work period.And data phase is extracted on ground,
DSP20 reception related commands, out simultaneously synchronous transfer is short to number biography by the digital independent in NAND flash24 by control FPGA21
Section or the real-time display of host computer 25.
Fig. 3 is ADC portion control sequential figure of the present invention.As shown in figure 3, according to ADC23 logic-controlled sequential,
After the order that FPGA21 receives that DSP20 is issued, corresponding logical-sequential control function is completed, at the same time, it should be noted that
The interval time of chip requirement, ensure its transmission speed in the case where ensureing certain surplus.
The basic structure schematic diagram that Fig. 4 is communicated between DSP of the present invention and ADC.As shown in figure 4, DSP20 with
Command word is transmitted by MCBSP between FPGA21, DSP20 transmitting order to lower levels controls FPGA21 working condition, completes command interpretation
Corresponding collecting work；Secondly, DSP20 and FPGA21 can carry out the transmission of data by HPI mouths therebetween, and ADC23 is adopted
In the data syn-chronization write-in DSP20 collected DRAM, in the circuit collecting work incipient stage, the transmitting order to lower levels of host computer 25 causes well
Lower acquisition control circuit 10 is started working, and acquisition control circuit 10 sends ignition signal according to the agreement timing of agreement, and passes through
Drive circuit excitation-emission transducer 84 is launched, and at the same time acquisition control circuit 10 completes initialization, is completed in transmitting certain
The agreement of gathered data, sample rate and sampling length also according to agreement controlling it by acquisition control circuit 10 after time
Order setting, while ADC23 is gathered, data are directly placed into the fifo data buffer built in FPGA21, and FPGA21 is certainly
Row detection fifo data buffer state, when for non-null states when, data are read and passed through from fifo data buffer
In HPI interfaces write-in DSP20 specified DRAM addresses.So, the gatherer process of a cycle is completed.
In embodiments of the present invention, the road signal of 10 synchronous acquisition of acquisition control circuit 4, sampling precision are 16, data wire
Parallel input, writes in FPGA21 fifo data buffer while ADC23 data are read, when fifo data buffer
State is non-NULL, and CONVSTA, B (ADC controlling switch) signal in Fig. 3 are put high enabled simultaneously, and then signal is read in control successively
Line RD (ADC reads enabled pin), reads 4 tunnel gathered datas, completes digital signal acquiring.DSP20 carries out the data collected
The processing such as automatic growth control and filtering compression, data are packed store according to agreement.
The data that adopted will be identified by DSP20, realize automatic growth control.Control command word is sent out in a manner of code by going here and there
The string and decoder of receiving circuit are given, to control the state of gain switch.Because every road signal includes 3000 16 data,
Therefore DSP20 will identify the maximum of every road signal, and when maximum is higher than upper threshold ident value, automatically controlling gain code will
Turn one grade down；Conversely, when maximum is less than lower threshold ident value, to tune up one grade (needs the upper threshold magnitude of voltage of appropriate regulation
And the difference of lower threshold magnitude of voltage).It can so ensure that the signal received under set gain mode is unlikely to too small and divided
Resolution is too low, at the same ensure that signal gain will not be excessive and cause to overflow and distort so that the size for receiving waveform is stable at certain
In one value range.
Fig. 5 is the FPGA21 and NAND Flash24 attachment structure schematic diagrams that invention is related to.As shown in figure 5, still with
FPGA21 controls NAND as the transmission bridge between DSP20 and NAND flash24, DSP20 with the situation of command word
Flash24 working condition is in underground acquisition phase, NAND flash24 write state opening, while data enter RAM
Non-NULL marking signal triggers, and FPGA21 controls write the data that logical sequence gathers ADC23 and write NAND flash24, are writing
During NAND flash24, the interval of write-in is controlled, because NAND flash24 construction limits, every page of amount of storage is
(2048+64) individual byte, and the maximum number of byte write in a continuous mode is 2048, it is therefore, necessary in the beginning of write-in data
Counted, each data arrive just to carry out counting and added up, when reaching monocycle maximum write-in value, it is necessary to re-write 5 weeks
The control command word (the page storage address and the block storage address in 3 cycles that include 2 cycles) of phase is to carry out writing for lower one page
Enter.And under a default mode, the data that monocycle per pass collects are 6k bytes, and four have 24k bytes altogether, so being deposited in data
During storage, page turn over operation occurs among every track data, in order to synchronize, in every page two memory cell of beginning
It is fixed to write two identifiers (it is 0xAA that identifier is fixed tentatively in the embodiment of the present invention), so on the one hand data are carried out necessarily
Interruption sign, on the other hand also bad block management afterwards is provided conveniently.When the collection of a cycle finishes, area to be buffered
After data write, RAM not empty signals are reset, and FPGA controls stop write-in, wait the arrival of next group of data.
The stage is read in ground data, DSP20 receives the reading order that host computer 25 issues, NAND is issued to FPGA22
Flash24 read commands, FPGA controls read logical sequence and read out the data in NAND flash24 by page, still will first
The data that each cycle is read are put into fifo data buffer as buffering, while the UART modules being integrated in FPGA22 enable
Start working, receive the parallel data exported by fifo data buffer, be then output to serial mode according to UART protocol
On the outer driving chip of piece, host computer is transmitted to by RS485 interfaces, completes digital independent flow.Herein, we are connect using RS-485
Mouthful, because it is the combination using balance driver and differential receiver, anti-common mode disturbances ability enhancing, agreement is simple, is easy to
Realize, be widely used in the data communication at PC ends.
It is pointed out that because RS485 interfaces are semiduplex, the interface conduct always in the continuous upload procedure of data
Receive occupied, can not now receive the order that host computer issues, consequently only that after total data could be carried out after reading
Operation, the caused unnecessary trouble this avoid data break.
When the bad block to NAND Flash24 is managed, due to having certain essence in NAND flash24 production technologies
Degree, it is impossible to which it is all intact to ensure all memory cell, thus before writing, bad block inspection is carried out to each memory cell
Survey.Its specific method is：FPGA reads the information of the 2049th memory cell of every piece of upper first page, if 0xFF, explanation
The block is intact, can carry out normal read-write operation, if it is not, explanation is bad block, skips the block and examines in this approach
Survey next piece of quality.In view of the feature, more judgements in data write-in and page erasing operation of the embodiment of the present invention are
No the step of being bad block, before a certain piece is operated, first the information of the block homepage is extracted, that is, see that this page is marked
Know whether information is 0xFF, if by checking, continue to operate the block, if not by the way that block address adds 1 to next piece
Operation, and circulate above step.
Acquisition control circuit provided in an embodiment of the present invention has not only given full play to the strong advantage of DSP data processing functions,
And by FPGA control sequentials precisely, rich interface the characteristics of show, improve the control accuracy of time, significantly reduce
The space-consuming of circuit board.
It is clear that on the premise of without departing from true spirit and scope of the present invention, invention described herein can be with
There are many changes.Therefore, it is all it will be apparent to those skilled in the art that change, be intended to be included in present claims
Within the scope of book is covered.Scope of the present invention is only defined by described claims.
Claims (8)
- A kind of 1. acquisition control circuit applied to acoustic logging while drilling, it is characterised in that including：Digital signal processor DSP, At least one programmable gate array device FPGA, simulation and digital quantizer ADC and memory cell,The DSP is by controlling the FPGA to be controlled the ADC and memory cell；The FPGA is sampled the ADC data gathered, and sampled data is transferred into the DSP, and the DSP is to institute The sampled data stated is analyzed and processed and the setting of agreement, and the data that protocol is carried after processing are passed through into the FPGA Store the memory cell；The memory cell design uses NAND Flash chip of the two panels capacity for 2GByte, when logic is write in the FPGA controls The data that sequence gathers the ADC write the NAND Flash chips, during the NAND Flash chips are write, The bad block management of the NAND Flash is carried out, while controls the interval of write-in；The circuit also includes host computer, and the DSP is when receiving the reading order that the host computer issues, to the FPGA The read command of memory cell is issued, the FPGA automatic identification bad blocks simultaneously control reading logical sequence by the number in the memory cell Read according to by page；The host computer and the FPGA are communicated by RS485 interfaces.
- 2. circuit according to claim 1, it is characterised in that the DSP and FPGA by HPI interfaces and/or MCBSP interfaces are communicated.
- 3. circuit according to claim 1, it is characterised in that the DSP includes dynamic random access memory DRAM, institute State DRAM be used for store the sampled data that is sent by the FPGA.
- 4. circuit according to claim 1, it is characterised in that the FPGA includes fifo data buffer, and the ADC exists While gathered data, data are directly placed into the fifo data buffer；The FPGA voluntarily detects the data fifo The state of buffer, when for non-null states when, data are read from the fifo data buffer and write the DSP and are specified DRAM addresses in.
- 5. circuit according to claim 1, it is characterised in that the DSP is specifically used for：The sampled data is identified, maximum of the DSP identifications per road signal, when maximum is higher than upper threshold flag During value, automatically control gain code and turn one grade down；When maximum is less than lower threshold ident value, one grade is tuned up.
- 6. circuit according to claim 1, it is characterised in that the ADC is specifically used for：4 tunnel analog signals are gathered simultaneously, and per pass waveform produces the data volume of 3000*16 bits in each cycle, and 4 all produce These data are transferred in the DSP by the data volume of 4*3000*16 bits, collection after completing by the FPGA.
- 7. circuit according to claim 1, it is characterised in that the DSP is additionally operable to：Data phase is extracted on ground, the DSP receives related command, controls the FPGA by the data in the memory cell Read out and synchronous transfer is to the host computer real-time display.
- 8. a kind of well logging apparatus, including receiving circuit, receive transducer, radiating circuit, transmitting transducer and power circuit, it is special Sign is, in addition to acquisition control circuit as claimed in claim 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410641095.5A CN104481503B (en) | 2014-11-13 | 2014-11-13 | A kind of acquisition control circuit and well logging apparatus applied to acoustic logging while drilling instrument |
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| CN201410641095.5A CN104481503B (en) | 2014-11-13 | 2014-11-13 | A kind of acquisition control circuit and well logging apparatus applied to acoustic logging while drilling instrument |
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| CN104481503B true CN104481503B (en) | 2018-02-13 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106285624A (en) * | 2016-07-20 | 2017-01-04 | 中国海洋石油总公司 | A kind of logger data acquisition means and device |
| CN108663972B (en) | 2018-05-23 | 2020-07-17 | 中国石油大学(北京) | Main control system and device of nuclear magnetic resonance logging instrument while drilling |
| CN109117276A (en) * | 2018-08-31 | 2019-01-01 | 湖南率为控制科技有限公司 | Acoustic logging instrument data processing system and its data processing method |
| CN108920400A (en) * | 2018-09-14 | 2018-11-30 | 河南中光学集团有限公司 | A kind of multipath high-speed high frequency serial data collection device and its acquisition method |
| CN110716893B (en) * | 2019-09-12 | 2020-07-10 | 中国科学院地质与地球物理研究所 | Method for synchronizing acoustic wave asynchronous serial port signals while drilling |
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