CN104465751B - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN104465751B CN104465751B CN201310421327.1A CN201310421327A CN104465751B CN 104465751 B CN104465751 B CN 104465751B CN 201310421327 A CN201310421327 A CN 201310421327A CN 104465751 B CN104465751 B CN 104465751B
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- fin
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 230000005669 field effect Effects 0.000 description 12
- 230000012447 hatching Effects 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
Abstract
The present invention discloses a kind of semiconductor device.Semiconductor device includes an active fin area (active fin region), an at least gate bar and a dummy fins section (dummy fin region).Active fin area includes an at least active fin (active fin).Gate bar is formed in active fin area, and extends across active fin.Dummy fins section is formed in the both sides in active fin area, and dummy fins section includes multiple virtual fins (dummy fin), and virtual fin is formed in the both sides of gate bar.
Description
Technical field
The content of present invention is related to a kind of semiconductor device, and having dummy fins section (dummy fin more particularly to one kind
Region semiconductor device).
Background technology
Since the size of integrated circuit reduces, for the increase in demand with high driving current and the transistor of small size,
Thus develop fin field-effect transistor (fin field-effect, finFET).The channel of fin field-effect transistor is formed in
On the side wall and top surface of fin so that fin field-effect transistor has larger channel width, and then can increase transistor
Driving current.Therefore, increase with the application of fin field-effect transistor, just more need exploitation that there is superperformance and improvement
The fin field-effect transistor of structure.
Invention content
The purpose of the present invention is to provide a kind of semiconductor device, the virtual fin in the semiconductor device is formed in actively
The both sides in fin area so that active fin area can be protected, without, by etching damage, thus making in manufacture craft
More good edge contour (edge profile) can be had by obtaining active fin area.
In order to achieve the above object, a kind of semiconductor device proposed by the present invention, including an active fin area (active fin
Region), an at least gate bar and a dummy fins section (dummy fin region).Active fin area includes at least one master
Dynamic fin (active fin).Gate bar is formed in active fin area, and extends across active fin.Dummy fins section is formed
Both sides in active fin area, dummy fins section include multiple virtual fins (dummy fin), and virtual fin is formed in gate bar
Both sides.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, preferred embodiment cited below particularly, and coordinates institute
Attached drawing is described in detail below：
Description of the drawings
Figure 1A is painted the top view of the semiconductor device according to one embodiment of the content of present invention；
Figure 1B is painted the diagrammatic cross-section of the virtual fin and active fin of the hatching 1B-1B ' along Figure 1A；
Fig. 2A is painted the top view of the semiconductor device according to another embodiment of the content of present invention；
Fig. 2 B are painted the diagrammatic cross-section of the semiconductor device of the hatching 2B-2B ' along Fig. 2A；
Fig. 2 C are painted the diagrammatic cross-section of the semiconductor device of the hatching 2C-2C ' along Fig. 2A；
Fig. 3 A~Fig. 7 B are painted the flow chart of the manufacturing method for semiconductor device of the embodiment according to the content of present invention.
Symbol description
100、200：Semiconductor device
110、210：Active fin area
111：Active fin
120：Gate bar
130、230：Dummy fins section
131~138：Virtual fin
141、143：Dummy gate item
150：Epitaxial layer
190：Silicide layer
280：Shallow trench isolation oxide
360：Silicon substrate
361：Silicon strip
363：Nitride spacer
367：Pattern nitride layer
1B-1B’、2B-2B’、2C-2C’、3B-3B’、4B-4B’、5B-5B’、6B-6B’、7B-7B’：Hatching
G：Spacing
HM：Hard mask
L1、L2：Length
P1、P2：Pitch
S：Distance
T1、T2：Thickness
Specific implementation mode
In the embodiment of this invention content, a kind of semiconductor device is proposed.It is virtual in semiconductor device in embodiment
Fin is formed in the both sides in active fin area so that active fin area can be protected, without in manufacture craft by
Etching damage, so that active fin area can have more good edge contour.However, embodiment and respective figure are only used
To illustrate as example, the range of the invention to be protected can't be limited.Also, there is identical label in attached drawing and invention description
Element be it is identical.In addition, it is noted that dimension scale on attached drawing is not necessarily drawn according to actual product equal proportion,
Therefore it is not intended as limiting the scope of the present invention and be used.
Figure 1A -1B are please referred to, the top view of the semiconductor device 100 of the embodiment according to the content of present invention is painted.
Semiconductor device 100 includes that an active fin area (active fin region) 110, at least one gate bar 120 and one are virtual
Fin area (dummy fin region) 130.As shown in Figure 1A, active fin area 110 includes an at least active fin (active
Fin) 111, gate bar 120 is formed in active fin area 110 and extends across active fin 111.Dummy fins section 130 is formed
Both sides in active fin area 110, dummy fins section 130 include multiple virtual fins (dummy fin) 131,132,133,
134, virtual fin 131~134 is formed in the both sides of gate bar 120.That is, virtual fin 131~134 is located at semiconductor
The peripheral region (periphery region) of the total of device 100.Thus, be located at 111 both sides (periphery of active fin
Area) virtual fin 131~134 can protect active fin 111 not by the etching damage in manufacture craft so that main
Dynamic fin 111 can have more good edge contour.
For example, as shown in Figure 1A, virtual fin 131,132 is formed in the side of gate bar 120, and virtual fin
133, the 134 opposite other side for being formed in gate bar 120.Also, gate bar 120 does not extend across any virtual fin 131
~134.
As shown in Figure 1A, in the present embodiment, virtual fin 131~134 is strip (striped-shaped).However, empty
The shape of quasi- fin can do appropriate selection according to practical application, be not limited with aforementioned shapes.
In the present embodiment, semiconductor device 100 can be fin field-effect transistor (fin field-effect,
finFET)。
As shown in Figure 1A, in embodiment, virtual fin 131~134 is parallel to active fin 111.Also, virtual fin
131~134 length L1 is less than the length L2 of active fin 111.
Figure 1B is please referred to, the virtual fin 131,133 and active fin 111 of the hatching 1B-1B ' along Figure 1A are painted
Diagrammatic cross-section.In embodiment, the thickness T1 of virtual fin 131,133 is identical as the thickness T2 of active fin 111.One embodiment
In, as shown in Figure 1B, the section of fin is for example with taper (tapered-shaped).
In embodiment, as shown in Figure 1A, it is separated by with a spacing (gap) G between virtual fin 131~134 and gate bar 120
It comes, spacing G is equal to or more than 5 nanometers (nm).Preferably, spacing G is equal to or more than 10 nanometers.Thus, virtual
It will not occur electrically to interfere between fin and gate bar 120, the e.g. generation of capacitance.
Furthermore spaced a distance (spacing) S between active fin area 110 and dummy fins section 130.For example, main
It is separated with distance S between dynamic fin 111 and virtual fin 131~134, distance S is about 35~45 nanometers.
As shown in Figure 1A, semiconductor device 100 may also include two dummy gate items (dummy gate strip) 141,
143.Dummy gate item 141,143 is covered each by the opposite end in active fin area 110, and dummy gate item 141,143 is not applied
Add any voltage.For example, dummy gate item 141 covers one end of active fin 111, and the covering of dummy gate item 143 is led
The opposite other end of dynamic fin 111.
In the present embodiment, as shown in Figure 1A, semiconductor device 100 more may include an epitaxial layer (epi layer) 150, outside
Prolong layer 150 to be formed on active fin 111 and virtual fin 131~134.Also, semiconductor device 100 may also include a silication
Nitride layer (is not illustrated in Figure 1A), and silicide layer is formed on epitaxial layer 150.That is, silicide layer is also formed in simultaneously
On active fin 111 and virtual fin 131~134.It is noted that epitaxial layer 150 with dotted line be illustrated in top view with
Become apparent from description the content of present invention.
In some embodiments, semiconductor device 100 is, for example, fin field-effect transistor, epitaxial layer 150 and disilicide layer
In conjunction with the drain/source region (S/D region) of e.g. fin field-effect transistor.Epitaxial layer 150 and disilicide layer full wafer are formed in
On virtual fin and active fin so that the external form profile of entire drain/source region is more uniform, therefore current distribution is also relatively equal
It is even, and the resistance of drain/source region can be reduced.
Fig. 2A is please referred to, the top view of the semiconductor device 200 according to another embodiment of the content of present invention is painted.This reality
Apply the semiconductor device 200 of example and the semiconductor device 100 of previous embodiment the difference is that active fin area 210 and dummy fins
The detail characteristic of section 230, remaining, which mutually exists together, repeats no more.
Semiconductor device 200 includes active fin area 210, multiple gate bars 120 and dummy fins section 230.Such as Fig. 2A
Shown, active fin area 210 includes multiple active fins 111, and gate bar 120 is formed in the both sides in active fin area 210 and prolongs
It stretches across active fin 111.In the present embodiment, as shown in Figure 2 A, gate bar 120 is arranged in parallel to each other, active fin 111 that
It is arranged in parallel around here.In the present embodiment, with 4 active fins, 111,3 gate bars 120 and 16 virtual fins 131~138
For.However, the quantity of active fin 111, gate bar 120 and virtual fin can do appropriate selection according to practical application, and
It is not limited with quantity above-mentioned.For example, when active number of fins is more, it is possible to provide electric current it is bigger.
In the present embodiment, as shown in Figure 2 A, dummy fins section 230 include multiple virtual fins 131,132,133,134,
135,136,137,138, virtual fin 131~138 is formed in the both sides in active fin area 210.That is, virtual fin position
In the peripheral region of total, virtual fin is not between any two active fin 111.Furthermore virtual fin 131~
138 are formed in the both sides of gate bar 120.For example, virtual fin 131,135 and virtual fin 132,136 are respectively formed in
The opposite sides of one gate bar 120.In embodiment, two dummy fins are at least set as shown in Figure 2 A, between each gate bar 120
Piece 131~138.
Fig. 2 B are painted the diagrammatic cross-section of the semiconductor device 200 of the hatching 2B-2B ' along Fig. 2A, and Fig. 2 C are painted along figure
The diagrammatic cross-section of the semiconductor device 200 of the hatching 2C-2C ' of 2A.
In some embodiments, the pitch (pitch) of virtual fin and the pitch manufacture craft of active fin are permitted
Minimum pitch.The pitch of virtual fin and the pitch of active fin can be identical or different.In a preferred embodiment, dummy fins
The pitch of piece and the pitch of active fin are substantially the same or very close.
For example, as shown in Fig. 2 B~Fig. 2 C, the pitch of the pitch P1 and active fin 111 of virtual fin 132,136
P2 is separately about 38~60 nanometers.Preferably, the pitch of the pitch P1 and active fin 111 of virtual fin 132,136
P2 is separately about 42~50 nanometers.Furthermore in an embodiment, the pitch of virtual fin and the pitch essence of active fin
It is upper identical.For example, as shown in Fig. 2 B~Fig. 2 C, the pitch P1 of virtual fin 132,136 and the pitch P2 of active fin 111 are real
It is identical in matter.In the present embodiment, the pitch of the pitch P2 of active fin 111 and all virtual fins 131~138 can be essence
It is upper identical.
Also, the pitch of active fin and the pitch of virtual fin can be equal to or be less than active fin area and dummy fins
The distance between section S.When the distance between active fin area and dummy fins section S are more than the pitch and dummy fins of active fin
The pitch of piece, thus, which no matter the Wiring pattern (layout pattern) of active fin area and dummy fins section is same
It is drawn in one step or in different step, such Design Rule (relaxed design rule) relatively loosened is for making
Active fin area and dummy fins section in technique can provide higher elasticity.On the other hand, when active fin area and dummy fins
The distance between section S is equal to the pitch of the pitch and virtual fin of active fin, and active fin area and dummy fins section can be with
It completes in single a manufacturing process steps, and then simplifies the manufacture craft of semiconductor device 200.
Further, as shown in Figure 2 B, semiconductor device 200 may also include shallow trench isolation oxide (STI oxide)
280。
In the present embodiment, as shown in Figure 2 A, semiconductor device 200 may also include epitaxial layer 150, and epitaxial layer 150 is formed in
On active fin 111, and connect those active fins 111.As shown in Fig. 2A and Fig. 2 C, epitaxial layer 150 can be also formed in virtually
On fin 131~138.In another embodiment, epitaxial layer 150 can be formed on all active fins 111, and be not formed in
It (is not illustrated in figure) at least part of virtual fin 131~138.Furthermore as shown in Figure 2 C, semiconductor device 200 may be used also
Including silicide layer 190, silicide layer 190 is formed on epitaxial layer 150.That is, silicide layer 190 is also formed in simultaneously
On active fin 111.It is noted that epitaxial layer 150 is illustrated in top view (Fig. 2A) with dotted line to become apparent from description originally
Invention content.
In some embodiments, semiconductor device 200 is, for example, fin field-effect transistor, epitaxial layer 150 and disilicide layer 190
Combination be, for example, fin field-effect transistor drain/source region.Epitaxial layer 150 and 190 full wafer of disilicide layer are formed in dummy fins
On piece and active fin so that the external form profile of entire drain/source region is more uniform, therefore current distribution is also more uniform, and energy
Enough reduce the resistance of drain/source region.
Fig. 3 A~Fig. 7 B are please referred to, the manufacturer of the semiconductor device 200 according to the embodiment of the content of present invention is painted
The flow chart of method.
Fig. 3 A~Fig. 3 B (Fig. 3 B are painted the diagrammatic cross-section of the hatching 3B-3B ' along Fig. 3 A) are please referred to, a silicon substrate is provided
Material 360 forms hard mask HM on silicon substrate 360 and forming multiple silicon strips 361 on hard mask HM.The material of silicon strip 361
E.g. polysilicon.Then, mononitride layer is formed and is covered on silicon strip 361 and hard mask HM, then removes the nitrogen of part
Compound layer is to form the top surface of nitride spacer (nitride spacer) 363 and exposure silicon strip 361.In the present embodiment,
The nitride layer of part is e.g. removed with etching process.As shown in Fig. 3 A~Fig. 3 B, nitride spacer 363 is around silicon
The side wall of item 361.
Then, Fig. 4 A~Fig. 4 B (Fig. 4 B are painted the diagrammatic cross-section of the hatching 4B-4B ' along Fig. 4 A) are please referred to, are removed
Silicon strip 361.In the present embodiment, silicon strip 361 is e.g. removed with wet etching manufacture craft or dry-etching manufacture craft.
Then, Fig. 5 A~Fig. 5 B (Fig. 5 B are painted the diagrammatic cross-section of the hatching 5B-5B ' along Fig. 5 A), pattern are please referred to
Change remaining nitride spacer 363 to form pattern nitride layer 367.The pattern of pattern nitride layer 367 corresponds to master
The transfer pattern (transferred pattern) in dynamic fin area and dummy fins section.E.g. with photoetching process
Patterned nitride clearance wall 363.
Then, Fig. 6 A~Fig. 6 B (Fig. 6 B are painted the diagrammatic cross-section of the hatching 6B-6B ' along Fig. 6 A) are please referred to, according to
The pattern of patterned silicon compound layer 367 etches silicon substrate 360, to form active fin area 210 and dummy fins section 230.
In general, when being etched to object, the etching degree of the fringe region of object would generally be more serious, because
And cause the fringe region of etching object by etching damage.For example, the height of etching object edge region or thickness meeting
Relatively low or fringe region etching outline is poor.Relatively, according to the embodiment of the content of present invention, as shown in Figure 6A, virtually
Fin area 230 is located at the both sides in active fin area 210, therefore virtual fin becomes the fringe region of entire fin structure.So
One, active fin is protected from etching damage between virtual fin, and by virtual fin, and makes position
Mitigate in the etching degree that the active fin of active fin area edge affords, so that active fin 111 can have more
Good edge contour.
Fig. 7 A~Fig. 7 B (Fig. 7 B are painted the diagrammatic cross-section of the hatching 7B-7B ' along Fig. 7 A) are please referred to, are removed remaining
Pattern nitride layer 367 and hard mask HM, formed an oxide layer in active fin area 210 and dummy fins section 230, it is flat
After changing oxide layer, etching oxide layer to be to form shallow trench isolation oxide 280 and form dummy gate item 141,143 and grid
Pole item 120.In the present embodiment, dummy gate item 141,143 and gate bar 120 are formed in the definition of shallow trench isolation oxide 280
Groove (trench) in.Similarly, dummy gate item 141,143 is formed in the both sides of gate bar 120, helps to protect grid
The formation of item 120 allows gate bar 120 to have more good edge contour not by etching damage.So far, such as Fig. 7 A
~Fig. 7 B (Fig. 2A~Fig. 2 C) complete.
Although in conclusion the above preferred embodiment has been combined to disclose the present invention, it is not limited to this hair
It is bright.Skilled person in the technical field of the invention, without departing from the spirit and scope of the present invention, can make it is various more
Dynamic and retouching.Therefore, protection scope of the present invention should be subject to what the appended claims were defined.
Claims (16)
1. a kind of semiconductor device, including：
Active fin area (active fin region), including multiple active fins (active fin), those active fins are flat
Row setting；
An at least gate bar is formed in the active fin area, and extends across those active fins；
Dummy fins section (dummy fin region), is formed in the both sides in the active fin area, which includes more
A virtual fin (dummy fin), those virtual fins are formed in the both sides of the gate bar；And
Epitaxial layer (epi layer), is formed on those active fins, and connects those active fins.
2. semiconductor device as described in claim 1, wherein those virtual fins are parallel to those active fins.
3. semiconductor device as described in claim 1, the wherein thickness of the thickness of those virtual fins and those active fins
It is identical.
4. semiconductor device as described in claim 1, the wherein length of those virtual fins are less than the length of those active fins
Degree.
5. semiconductor device as described in claim 1, wherein with a spacing (gap) between those virtual fins and the gate bar
It is spaced and, which is equal to or more than 5 nanometers (nm).
6. semiconductor device as described in claim 1, wherein the active fin area and the dummy fins section are spaced a distance
(spacing), which is 35~45 nanometers.
7. semiconductor device as described in claim 1, further includes：
Two dummy gate items (dummy gate strip), are covered each by the opposite end in the active fin area.
8. semiconductor device as described in claim 1, further includes：
Multiple gate bars, those gate bars are arranged in parallel.
9. semiconductor device as claimed in claim 8, wherein at least two those virtual fins are respectively arranged between the gate bar.
10. semiconductor device as described in claim 1, the wherein pitch (pitch) of those active fins and those are virtual
The pitch of fin is separately 38~60 nanometers.
11. semiconductor device as described in claim 1, the wherein section of the pitch of those active fins and those virtual fins
Away from separately be 42~50 nanometers.
12. semiconductor device as described in claim 1, the wherein section of the pitch of those active fins and those virtual fins
Away from substantially the same.
13. semiconductor device as described in claim 1, the wherein epitaxial layer are also formed into those dummy fins on pieces.
14. semiconductor device as described in claim 1, further includes：
Silicide layer is formed on the epitaxial layer.
15. a kind of semiconductor device, including：
Active fin area (active fin region), including an active fin (active fin)；
An at least gate bar is formed in the active fin area, and extends across the active fin；
Dummy fins section (dummy fin region), is formed in the both sides in the active fin area, which includes more
A virtual fin (dummy fin), those virtual fins are formed in the both sides of the gate bar；And
Epitaxial layer is formed in the active fin and those dummy fins on pieces.
16. semiconductor device as claimed in claim 15, further includes：
Silicide layer is formed on the epitaxial layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310421327.1A CN104465751B (en) | 2013-09-16 | 2013-09-16 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310421327.1A CN104465751B (en) | 2013-09-16 | 2013-09-16 | Semiconductor device |
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| CN104465751A CN104465751A (en) | 2015-03-25 |
| CN104465751B true CN104465751B (en) | 2018-08-31 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106158648B (en) * | 2015-04-13 | 2019-12-27 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing Fin FET device |
| CN107634088A (en) * | 2016-07-18 | 2018-01-26 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN109560136B (en) * | 2017-09-26 | 2022-08-23 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1906755A (en) * | 2004-04-30 | 2007-01-31 | 松下电器产业株式会社 | Semiconductor manufacturing method and semiconductor device |
| CN101490822A (en) * | 2006-07-11 | 2009-07-22 | Nxp股份有限公司 | Seimiconductor devices and methods of manufacture thereof |
| CN102197467A (en) * | 2008-11-06 | 2011-09-21 | 高通股份有限公司 | A method of fabricating a fin field effect transistor (FINFET) device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09331059A (en) * | 1996-06-13 | 1997-12-22 | Nippon Telegr & Teleph Corp <Ntt> | Dual barrier structure and its manufacturing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1906755A (en) * | 2004-04-30 | 2007-01-31 | 松下电器产业株式会社 | Semiconductor manufacturing method and semiconductor device |
| CN101490822A (en) * | 2006-07-11 | 2009-07-22 | Nxp股份有限公司 | Seimiconductor devices and methods of manufacture thereof |
| CN102197467A (en) * | 2008-11-06 | 2011-09-21 | 高通股份有限公司 | A method of fabricating a fin field effect transistor (FINFET) device |
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