CN104465751A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN104465751A CN104465751A CN201310421327.1A CN201310421327A CN104465751A CN 104465751 A CN104465751 A CN 104465751A CN 201310421327 A CN201310421327 A CN 201310421327A CN 104465751 A CN104465751 A CN 104465751A
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- Prior art keywords
- fin
- fins
- semiconductor device
- active
- those
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 239000011295 pitch Substances 0.000 claims 7
- 238000005530 etching Methods 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 230000005669 field effect Effects 0.000 description 12
- 230000012447 hatching Effects 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a semiconductor device. The semiconductor device includes an active fin region, at least one gate strip and a dummy fin region, wherein the active fin region comprises at least one active fin, and the gate strip is formed on the active fin region, and extends and strides over the active fin, and the dummy fin region is formed at two sides of the active fin region and comprises a plurality of dummy fins which are formed at two sides of the gate strip.
Description
Technical field
Content of the present invention relates to a kind of semiconductor device, and particularly relates to the semiconductor device that one has dummy fins section (dummy fin region).
Background technology
Because the size of integrated circuit reduces, for the increase in demand with high drive current and undersized transistor, thus develop fin field-effect transistor (fin field-effect, finFET).On the sidewall that the passage of fin field-effect transistor is formed at fin and top surface, make fin field-effect transistor have larger channel width, and then the drive current of transistor can be increased.Therefore, along with the application of fin field-effect transistor increases, just more need exploitation to have superperformance and structure improved fin field-effect transistor.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device; virtual fin in this semiconductor device is formed at the both sides in initiatively fin district; initiatively fin district can be protected; and etching damage can not be subject in manufacture craft, thus make initiatively fin district can have better edge contour (edgeprofile).
For reaching above-mentioned purpose, a kind of semiconductor device that the present invention proposes, comprises initiatively fin district (activefin region), at least one gate bar and a dummy fins section (a dummy fin region).Initiatively fin district comprises at least one active fin (active fin).Gate bar is formed in active fin district, and extends across initiatively fin.Dummy fins section is formed at the both sides in initiatively fin district, and dummy fins section comprises multiple virtual fin (dummy fin), and virtual fin is formed at the both sides of gate bar.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating appended accompanying drawing, being described in detail below:
Accompanying drawing explanation
Figure 1A illustrates the top view of the semiconductor device according to content one embodiment of the present invention;
Figure 1B illustrates the generalized section of virtual fin along the hatching 1B-1B ' of Figure 1A and initiatively fin;
Fig. 2 A illustrates the top view of the semiconductor device according to another embodiment of content of the present invention;
Fig. 2 B illustrates the generalized section of the semiconductor device of the hatching 2B-2B ' along Fig. 2 A;
Fig. 2 C illustrates the generalized section of the semiconductor device of the hatching 2C-2C ' along Fig. 2 A;
Fig. 3 A ~ Fig. 7 B illustrates the flow chart of the manufacturing method for semiconductor device of the embodiment according to content of the present invention.
Symbol description
100,200: semiconductor device
110,210: initiatively fin district
111: initiatively fin
120: gate bar
130,230: dummy fins section
131 ~ 138: virtual fin
141,143: dummy gate bar
150: epitaxial loayer
190: silicide layer
280: shallow trench isolation oxide
360: silicon substrate
361: silicon strip
363: nitride spacer
367: pattern nitride layer
1B-1B ', 2B-2B ', 2C-2C ', 3B-3B ', 4B-4B ', 5B-5B ', 6B-6B ', 7B-7B ': hatching
G: spacing
HM: hard mask
L1, L2: length
P1, P2: pitch
S: distance
T1, T2: thickness
Embodiment
In the embodiment of this summary of the invention, a kind of semiconductor device is proposed.In embodiment, the virtual fin in semiconductor device is formed at the both sides in initiatively fin district, initiatively fin district can be protected, and can not be subject to etching damage in manufacture craft, thus make initiatively fin district can have better edge contour.But embodiment and respective figure, can't the scope of limit the present invention for protecting only in order to illustrate as example.Further, the element having identical label in accompanying drawing and invention description is identical.In addition, it is noted that dimension scale on accompanying drawing not necessarily are drawn according to actual product equal proportion, therefore not as the use of limit scope.
Please refer to Figure 1A-1B, it illustrates the top view of the semiconductor device 100 of the embodiment according to content of the present invention.Semiconductor device 100 comprises active fin district (active fin region) 110, at least one gate bar 120 and a dummy fins section (dummy fin region) 130.As shown in Figure 1A, initiatively fin district 110 comprises at least one active fin (active fin) 111, and gate bar 120 is formed at and initiatively fin district 110 extends across initiatively fin 111.Dummy fins section 130 is formed at the both sides in initiatively fin district 110, and dummy fins section 130 comprises multiple virtual fin (dummy fin) 131,132,133,134, and virtual fin 131 ~ 134 is formed at the both sides of gate bar 120.That is, virtual fin 131 ~ 134 is positioned at the surrounding zone (periphery region) of the total of semiconductor device 100.Thus, the virtual fin 131 ~ 134 being arranged in initiatively fin 111 both sides (surrounding zone) can protect initiatively fin 111 not to be subject to the etching damage of manufacture craft, thus makes initiatively fin 111 can have better edge contour.
For example, as shown in Figure 1A, virtual fin 131,132 is formed at the side of gate bar 120, and virtual fin 133,134 is formed at the relative opposite side of gate bar 120.Further, gate bar 120 does not extend across any virtual fin 131 ~ 134.
As shown in Figure 1A, in the present embodiment, virtual fin 131 ~ 134 is strip (striped-shaped).But the shape of virtual fin can do suitable selection according to practical application, is not limited with aforementioned shapes.
In the present embodiment, semiconductor device 100 can be fin field-effect transistor (fin field-effect, finFET).
As shown in Figure 1A, in embodiment, virtual fin 131 ~ 134 is parallel to initiatively fin 111.Further, the length L1 of virtual fin 131 ~ 134 is less than the length L2 of initiatively fin 111.
Please refer to Figure 1B, it illustrates the generalized section of virtual fin 131,133 along the hatching 1B-1B ' of Figure 1A and initiatively fin 111.In embodiment, the thickness T1 of virtual fin 131,133 is identical with the thickness T2 of active fin 111.In one embodiment, as shown in Figure 1B, the section of fin such as has taper (tapered-shaped).
In embodiment, as shown in Figure 1A, be separated by with a spacing (gap) G between virtual fin 131 ~ 134 and gate bar 120 and come, spacing G is for being equal to or greater than 5 nanometers (nm).Preferably, spacing G is for being equal to or greater than 10 nanometers.Thus, between virtual fin and gate bar 120, electrical interference can not occur, such as, be the generation of electric capacity.
Moreover, distance (spacing) S of being initiatively separated by between fin district 110 and dummy fins section 130.For example, initiatively separate with this distance S between fin 111 and virtual fin 131 ~ 134, this distance S is about 35 ~ 45 nanometers.
As shown in Figure 1A, semiconductor device 100 also can comprise two dummy gate bars (dummy gatestrip) 141,143.Dummy gate bar 141,143 covers the opposite end in initiatively fin district 110 respectively, and dummy gate bar 141,143 does not apply any voltage.For example, dummy gate bar 141 covers one end of initiatively fin 111, and dummy gate bar 143 covers the relative other end of initiatively fin 111.
In the present embodiment, as shown in Figure 1A, semiconductor device 100 more can comprise an epitaxial loayer (epi layer) 150, and epitaxial loayer 150 is formed on active fin 111 and virtual fin 131 ~ 134.Further, semiconductor device 100 also can comprise a silicide layer (not being illustrated in Figure 1A), and silicide layer is formed on epitaxial loayer 150.That is, silicide layer is also formed on active fin 111 and virtual fin 131 ~ 134 simultaneously.It is noted that epitaxial loayer 150 is illustrated in top view with dotted line with clearer description content of the present invention.
In some embodiments, semiconductor device 100 is such as fin field-effect transistor, and the combination of epitaxial loayer 150 and disilicide layer is such as the drain/source region of fin field-effect transistor (S/D region).Epitaxial loayer 150 and disilicide layer full wafer are formed on virtual fin and active fin, and make the external form profile of whole drain/source region comparatively even, therefore CURRENT DISTRIBUTION is also comparatively even, and can reduce the resistance of drain/source region.
Please refer to Fig. 2 A, it illustrates the top view of the semiconductor device 200 according to another embodiment of content of the present invention.Semiconductor device 200 and the difference of the semiconductor device 100 of previous embodiment of the present embodiment are the detail characteristic of initiatively fin district 210 and dummy fins section 230, and all the other exist together mutually and repeat no more.
Semiconductor device 200 comprises initiatively fin district 210, multiple gate bar 120 and dummy fins section 230.As shown in Figure 2 A, initiatively fin district 210 comprises multiple active fin 111, and gate bar 120 is formed at the both sides in initiatively fin district 210 and extends across initiatively fin 111.In the present embodiment, as shown in Figure 2 A, gate bar 120 be arranged in parallel to each other, and initiatively fin 111 be arranged in parallel to each other.In the present embodiment, for 4 active fin 111,3 gate bar 120 and 16 virtual fins 131 ~ 138.But initiatively the quantity of fin 111, gate bar 120 and virtual fin can do suitable selection according to practical application, is not limited with aforesaid quantity.For example, when active number of fins is more, available electric current is larger.
In the present embodiment, as shown in Figure 2 A, dummy fins section 230 comprises multiple virtual fin 131,132,133,134,135,136,137,138, and virtual fin 131 ~ 138 is formed at the both sides in initiatively fin district 210.That is, virtual fin is positioned at the surrounding zone of total, and virtual fin is not positioned between any two active fins 111.Moreover virtual fin 131 ~ 138 is formed at the both sides of gate bar 120.For example, virtual fin 131,135 and virtual fin 132,136 are formed at the relative both sides of a gate bar 120 respectively.In embodiment, as shown in Figure 2 A, two virtual fins 131 ~ 138 are at least set between each gate bar 120.
Fig. 2 B illustrates the generalized section of the semiconductor device 200 of the hatching 2B-2B ' along Fig. 2 A, and Fig. 2 C illustrates the generalized section of the semiconductor device 200 of the hatching 2C-2C ' along Fig. 2 A.
In some embodiments, the minimum pitch that the pitch (pitch) of virtual fin and the pitch manufacture craft of active fin allow.The pitch of virtual fin and the pitch of active fin can be identical or different.In a preferred embodiment, the pitch of virtual fin is identical in fact with the pitch of initiatively fin or closely.
For example, as shown in Fig. 2 B ~ Fig. 2 C, the pitch P1 of virtual fin 132, the 136 and pitch P2 of active fin 111 is separately about 38 ~ 60 nanometers.Preferably, the pitch P1 of virtual fin 132, the 136 and pitch P2 of active fin 111 is separately about 42 ~ 50 nanometers.Moreover in an embodiment, the pitch of virtual fin is identical in fact with the pitch of active fin.For example, as shown in Fig. 2 B ~ Fig. 2 C, the pitch P1 of virtual fin 132,136 is identical in fact with the pitch P2 of active fin 111.In the present embodiment, initiatively the pitch P2 of fin 111 can be identical in fact with the pitch of all virtual fins 131 ~ 138.
Further, initiatively the pitch of fin and the pitch of virtual fin can be equal to or less than the distance S initiatively between fin district and dummy fins section.Distance S between active fin district and dummy fins section is greater than the initiatively pitch of fin and the pitch of virtual fin, thus, no matter initiatively the Wiring pattern (layout pattern) of fin district and dummy fins section plots in same step or in different step, and the Design Rule (relaxed design rule) that this kind comparatively loosens can provide higher elasticity for the active fin district in manufacture craft and dummy fins section.On the other hand, distance S between active fin district and dummy fins section equals the initiatively pitch of fin and the pitch of virtual fin, initiatively fin district and dummy fins section can complete in single manufacturing process steps, and then simplify the manufacture craft of semiconductor device 200.
Further, as shown in Figure 2 B, semiconductor device 200 also can comprise shallow trench isolation oxide (STI oxide) 280.
In the present embodiment, as shown in Figure 2 A, semiconductor device 200 also can comprise epitaxial loayer 150, and epitaxial loayer 150 is formed on active fin 111, and connects those initiatively fins 111.As shown in Fig. 2 A and Fig. 2 C, epitaxial loayer 150 also can be formed on virtual fin 131 ~ 138.In another embodiment, epitaxial loayer 150 can be formed on all active fins 111, and is not formed at least part of virtual fin 131 ~ 138 (not being illustrated in figure).Moreover as shown in Figure 2 C, semiconductor device 200 also can comprise silicide layer 190, and silicide layer 190 is formed on epitaxial loayer 150.That is, silicide layer 190 is also formed on active fin 111 simultaneously.It is noted that epitaxial loayer 150 is illustrated in top view (Fig. 2 A) with dotted line with clearer description content of the present invention.
In some embodiments, semiconductor device 200 is such as fin field-effect transistor, and the combination of epitaxial loayer 150 and disilicide layer 190 is such as the drain/source region of fin field-effect transistor.Epitaxial loayer 150 and disilicide layer 190 full wafer are formed on virtual fin and active fin, and make the external form profile of whole drain/source region comparatively even, therefore CURRENT DISTRIBUTION is also comparatively even, and can reduce the resistance of drain/source region.
Please refer to Fig. 3 A ~ Fig. 7 B, it illustrates the flow chart of the manufacture method of the semiconductor device 200 according to the embodiment of content of the present invention.
Please refer to Fig. 3 A ~ Fig. 3 B (Fig. 3 B illustrates the generalized section of the hatching 3B-3B ' along Fig. 3 A), a silicon substrate 360 is provided, form hard mask HM on silicon substrate 360 and form multiple silicon strip 361 on hard mask HM.The material of silicon strip 361 is such as polysilicon.Then, mononitride layer is formed and is covered on silicon strip 361 and hard mask HM, then removes the nitride layer of part to form nitride spacer (nitride spacer) 363 and to expose the top surface of silicon strip 361.In the present embodiment, such as, it is the nitride layer removing part with etching process.As shown in Fig. 3 A ~ Fig. 3 B, nitride spacer 363 is around the sidewall of silicon strip 361.
Then, please refer to Fig. 4 A ~ Fig. 4 B (Fig. 4 B illustrates the generalized section of the hatching 4B-4B ' along Fig. 4 A), remove silicon strip 361.In the present embodiment, such as, be remove silicon strip 361 with Wet-type etching manufacture craft or dry-etching manufacture craft.
Then, please refer to Fig. 5 A ~ Fig. 5 B (Fig. 5 B illustrates the generalized section of the hatching 5B-5B ' along Fig. 5 A), the remaining nitride spacer 363 of patterning is to form pattern nitride layer 367.The pattern transferring (transferredpattern) of pattern corresponding initiatively fin district and the dummy fins section of pattern nitride layer 367.Such as with photoetching process patterned nitride clearance wall 363.
Then, please refer to Fig. 6 A ~ Fig. 6 B (Fig. 6 B illustrates the generalized section of the hatching 6B-6B ' along Fig. 6 A), according to the pattern etching silicon base material 360 of patterned silicon compound layer 367, to form initiatively fin district 210 and dummy fins section 230.
In general, when etching object, the etching degree of the fringe region of object usually can be comparatively serious, thus causes the fringe region of etching object to be subject to etching damage.For example, height or the thickness of etching object edge region can be lower, or the etching outline of fringe region is poor.Relatively, according to the embodiment of content of the present invention, as shown in Figure 6A, dummy fins section 230 is positioned at the both sides in initiatively fin district 210, and therefore virtual fin becomes the fringe region of whole fin structure.Thus; initiatively fin is between virtual fin; and be subject to the protection of virtual fin and be not subject to etching damage, and the etching degree that the active fin being positioned at initiatively fin area edge is afforded alleviates, thus make initiatively fin 111 can have better edge contour.
Please refer to Fig. 7 A ~ Fig. 7 B (Fig. 7 B illustrates the generalized section of the hatching 7B-7B ' along Fig. 7 A), remove remaining pattern nitride layer 367 and hard mask HM, formed an oxide layer in active fin district 210 and dummy fins section 230, after planarization oxide layer, etching oxide layer to be to form shallow trench isolation oxide 280 and to form dummy gate bar 141,143 and gate bar 120.In the present embodiment, dummy gate bar 141,143 and gate bar 120 are formed in the groove (trench) of shallow trench isolation oxide 280 definition.Similarly, dummy gate bar 141,143 is formed at the both sides of gate bar 120, contributes to protecting the formation of gate bar 120 not to be subject to etching damage, and makes gate bar 120 can have better edge contour.So far, as Fig. 7 A ~ Fig. 7 B (Fig. 2 A ~ Fig. 2 C) completes.
In sum, although disclose the present invention in conjunction with above preferred embodiment, however itself and be not used to limit the present invention.Be familiar with this operator in the technical field of the invention, without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Therefore, what protection scope of the present invention should define with the claim of enclosing is as the criterion.
Claims (18)
1. a semiconductor device, comprising:
Initiatively fin district (active fin region), at least one active fin (active fin) is comprised;
At least one gate bar, is formed in this active fin district, and extends across this active fin; And
Dummy fins section (dummy fin region), is formed at the both sides in this active fin district, and this dummy fins section comprises multiple virtual fin (dummy fin), and those virtual fins are formed at the both sides of this gate bar.
2. semiconductor device as claimed in claim 1, wherein those virtual fins are parallel to this active fin.
3. semiconductor device as claimed in claim 1, wherein the thickness of those virtual fins is identical with the thickness of this active fin.
4. semiconductor device as claimed in claim 1, wherein the length of those virtual fins is less than the length of this active fin.
5. semiconductor device as claimed in claim 1, be wherein separated by with a spacing (gap) between those virtual fin and this gate bar and come, this spacing is for being equal to or greater than 5 nanometers (nm).
6. semiconductor device as claimed in claim 1, wherein this active fin district and this dummy fins section are separated by one apart from (spacing), and this distance is 35 ~ 45 nanometers.
7. semiconductor device as claimed in claim 1, also comprises:
Two dummy gate bars (dummy gate strip), cover the opposite end in this active fin district respectively.
8. semiconductor device as claimed in claim 1, also comprises:
This gate bar multiple, those gate bar be arranged in parallel.
9. semiconductor device as claimed in claim 8, wherein respectively arranges at least two those virtual fins between this gate bar.
10. semiconductor device as claimed in claim 1, wherein this active fin district also comprises those active fins multiple, and those active fins be arranged in parallel.
11. semiconductor devices as claimed in claim 10, wherein those active pitches (pitch) of fin and the pitch of those virtual fins are separately 38 ~ 60 nanometers.
12. semiconductor devices as claimed in claim 10, wherein those active pitches of fin and the pitch of those virtual fins are separately 42 ~ 50 nanometers.
13. semiconductor devices as claimed in claim 10, wherein those initiatively the pitch of fins and the pitch of those virtual fins identical in fact.
14. semiconductor devices as claimed in claim 10, also comprise:
Epitaxial loayer (epi layer), is formed on those active fins, and connects those initiatively fins.
15. semiconductor devices as claimed in claim 14, wherein this epitaxial loayer is also formed on those virtual fins.
16. semiconductor devices as claimed in claim 14, also comprise:
Silicide layer, is formed on this epitaxial loayer.
17. semiconductor devices as claimed in claim 1, also comprise:
Epitaxial loayer, is formed on this active fin and those virtual fins.
18. semiconductor devices as claimed in claim 17, also comprise:
Silicide layer, is formed on this epitaxial loayer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310421327.1A CN104465751B (en) | 2013-09-16 | 2013-09-16 | Semiconductor device |
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| CN201310421327.1A CN104465751B (en) | 2013-09-16 | 2013-09-16 | Semiconductor device |
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| CN104465751A true CN104465751A (en) | 2015-03-25 |
| CN104465751B CN104465751B (en) | 2018-08-31 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158648A (en) * | 2015-04-13 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The method preparing Fin FET device |
| CN107634088A (en) * | 2016-07-18 | 2018-01-26 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN109560136A (en) * | 2017-09-26 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN1906755A (en) * | 2004-04-30 | 2007-01-31 | 松下电器产业株式会社 | Semiconductor manufacturing method and semiconductor device |
| CN101490822A (en) * | 2006-07-11 | 2009-07-22 | Nxp股份有限公司 | Seimiconductor devices and methods of manufacture thereof |
| CN102197467A (en) * | 2008-11-06 | 2011-09-21 | 高通股份有限公司 | A method of fabricating a fin field effect transistor (FINFET) device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106158648A (en) * | 2015-04-13 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The method preparing Fin FET device |
| CN106158648B (en) * | 2015-04-13 | 2019-12-27 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing Fin FET device |
| CN107634088A (en) * | 2016-07-18 | 2018-01-26 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
| CN109560136A (en) * | 2017-09-26 | 2019-04-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| Publication number | Publication date |
|---|---|
| CN104465751B (en) | 2018-08-31 |
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