CN104465658A - Ultra-high voltage semiconductor device and manufacturing method thereof - Google Patents

Ultra-high voltage semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN104465658A
CN104465658A CN201310435383.0A CN201310435383A CN104465658A CN 104465658 A CN104465658 A CN 104465658A CN 201310435383 A CN201310435383 A CN 201310435383A CN 104465658 A CN104465658 A CN 104465658A
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China
Prior art keywords
trap
oxide semiconductor
pressure
metal oxide
high pressure
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CN201310435383.0A
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Chinese (zh)
Inventor
陈建志
张宇瑞
林正基
连士进
吴锡垣
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Macronix International Co Ltd
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Macronix International Co Ltd
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Priority to CN201310435383.0A priority Critical patent/CN104465658A/en
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Abstract

The invention discloses an ultra-high voltage semiconductor device and a manufacturing method of the ultra-high voltage semiconductor device. The ultra-high voltage semiconductor device is provided with an isolating structure for high-voltage side operation. The semiconductor device, especially an ultra-high voltage metal-oxide semiconductor device, is defined by a doping gradient structure in a drain region. For example, an ultra-high voltage n-type metal-oxide semiconductor device is defined by an n- doping gradient structure in the drain region. The n- doping gradient structure is provided with at least one of a high-voltage n trap, a drain side high-voltage n-type deep trap and a drain side n-type trap in the drain region. A drain side n+ trap is additionally configured in at least one of the high-voltage n trap, the drain side high-voltage n-type deep trap and the drain side n-type trap. The manufacturing method of the ultra-high voltage n-type metal-oxide semiconductor device with the doping gradient structure of the drain region is provided together.

Description

A kind of superhigh pressure semiconductor device and manufacture method thereof
Technical field
The invention relates to a kind of semiconductor device, after repeated, its breakdown voltage has essence Shangdi significantly to be improved.And relate to a kind of ultrahigh voltage metal oxide semiconductor device with a kind of two-step diffusion structure of amendment especially.The present invention is also about the manufacture method of this semiconductor device.
Background technology
The enhancement of the manufacture of semiconductor device is the miniaturization continuing to emphasize metal-oxide semiconductor (MOS) (MOS) transistor.The degree that the size that high-voltage metal oxide semiconductor (HVMOS) transistor design tends to limit transistor reduces.Therefore, the semiconductor device using high voltage most is the number being limited to the integrated circuit that can be formed on a wafer.
Ultrahigh voltage metal oxide semiconductor (UHV MOS) device is attempted to integrate ultra-high pressure apparatus structure and lower voltage devices structure.For example, ultra-high pressure apparatus may comprise the metal-oxide semiconductor (MOS) of a sideways diffusion and the drain metal oxide semiconductor of a dual diffusion.
The feature of sideways diffusion metal-oxide semiconductor (MOS) (LDMOS) transistor arrangement is: higher junction breakdown voltage, but generally speaking needs large-size.The feature of sideways diffusion metal oxide semiconductor transistor is: the drift region of a sideways diffusion, and it has a low dopant concentration but has a sizable area, and its part contributes to the device of large-size.The drift region of sideways diffusion metal-oxide semiconductor (MOS) is the high pressure for relaxing between drain electrode and source electrode, and allows the breakdown voltage of an increase.Sideways diffusion metal oxide semiconductor transistor has adopted less grid structure to reduce their size and to improve their reliabilitys in high speed operation, but this also causes the minimizing of a short-channel effect and limit voltage.
A kind of structure of LDD metal-oxide semiconductor (MOS) (LDD MOS) attempts to suppress short-channel effect, and it causes the channel electric fields of a minimizing by being reduced to the density of the doping of drain electrode and source area.Comparatively low-density doping in these regions reduces applied voltage, causes the minimizing needing the electric field strength traversing the sensed generation of source electrode and drain region.A shortcoming of LDD MOS device, for the photoresist number of steps generally needed than known mos device more increases.
One is the difficulty of reliability of promoting breakdown voltage in the common problem of known ultrahigh voltage metal oxide semiconductor device.For example, ultrahigh voltage metal oxide semiconductor possible operation is in the voltage range of 0 to 600V.The breakdown voltage of whole circuit not only depends on the breakdown voltage of ultrahigh voltage metal oxide semiconductor device, and also depends on the impact for the breakdown voltage of the interconnection structure of conduct high tension in circuit.
Drain metal oxide semiconductor (DDD MOS) device of dual diffusion is applicable to being normally used as high voltage transistor (that is, high voltage most).But the drain metal oxide semiconductor device of known dual diffusion is invalid when experiencing harsh reliability test.For example, high temperature reverse bias (HTRB) test is a kind of normally used harsh reliability test.Because the high electric field brought out between gate electrode (its may quite close to earth terminal) and drain electrode (applying high pressure in this), the doping of the high dose in drain region can cause Gate Induced Drain leakage current.Need to reduce the limit voltage of Gate Induced Drain leakage current at device.
In addition, As time goes on the breakdown voltage continuing to use known super high voltage metal oxide semiconductor transistor tube to tend to show device degenerates.In this skill, there is a demand to have larger operating flexibility exactly, but do not need the high voltage most structure of the number of the processing step increased significantly required for manufacturing installation.
Summary of the invention
The semiconductor device of the embodiment of the present invention, it has the breakdown voltage more continued when lasting use.
Of the present invention one implements pattern provides a kind of ultrahigh voltage metal oxide semiconductor device, and it comprises a metal oxide semiconductor transistor, and it has a doping gradient structure in a drain region; One high pressure interconnecting area, closest to metal oxide semiconductor transistor, high pressure interconnecting area has at least one dielectric layer and at least one metal level; One self-mask regions, aims at high pressure interconnecting area closest to metal oxide semiconductor transistor; And an operating space, high-pressure side, separate high pressure interconnecting area and self-mask regions with metal oxide semiconductor transistor.
In one embodiment of the invention, ultrahigh voltage metal oxide semiconductor device doping gradient structure may comprise a high pressure n trap, a high pressure N-shaped deep trap and a N-shaped trap one of at least.In some embodiment of the present invention, doping gradient structure may comprise a n+ trap in addition.
Some embodiment of the present invention also comprises a superhigh pressure n-type metal oxide semiconductor device, more especially comprise a substrate and a drain region, substrate has an epitaxial loayer, epitaxial layer portion is configured in substrate, drain region has a n-doping gradient structure and one first N-shaped embedding layer, is positioned at a boundary of drain region.
In some embodiment of the present invention, the epitaxial loayer of ultrahigh voltage metal oxide semiconductor device may be a p-type epitaxial layer or a N-shaped epitaxial loayer one of at least.In some embodiment of the present invention, n-doping gradient structure comprise a high pressure n trap, a high pressure N-shaped deep trap and a N-shaped trap one of at least.In some embodiment of the present invention, n-doping gradient structure comprises a n+ trap in addition.
In one embodiment of the invention, ultrahigh voltage metal oxide semiconductor device may comprise a body region, one source pole district, a channel region and a gate regions in addition.Body region and source area are just in the face of drain region, body region and source area defined by one second N-shaped embedding layer, one first high pressure p-type deep trap, a main body p+ trap and one source pole n+ trap, wherein a part for the second N-shaped embedding layer to be configured in substrate and another part in epitaxial loayer, first high pressure p-type deep trap partial configuration in the second N-shaped embedding layer and a remaining portion on the second N-shaped embedding layer, main body p+ trap is configured to define a body contact in the first high pressure p-type deep trap, and source electrode n+ trap is configured in the first high pressure p-type deep trap to define one source pole contact site.Drain region and body region and source area separate by channel region, and channel region has one first high pressure n trap, and it traverses channel region from body region and source area extension and arrive drain region.Gate regions is closest to body region and source area and part in alignment with on channel region, and gate regions has a conductive layer.In some embodiment of the present invention, the second N-shaped embedding layer volt is below the main body p+ trap and source electrode n+ trap of body region and source area.
In some embodiment of the present invention, the channel region of ultrahigh voltage metal oxide semiconductor device may comprise a p top zone in addition, and the upper surface along a mask of substrate configures.In some other embodiment of the present invention, p top zone may comprise multiple discrete p tops section.
In one embodiment of the invention, ultrahigh voltage metal oxide semiconductor device may comprise a self-mask regions in addition, aim at the boundary of drain region, the boundary of drain region is positioned at tossing about of the side of the drain region aimed at channel region, and self-mask regions has one second high pressure p-type deep trap; One high pressure interconnecting area, is aligned on self-mask regions, has at least one dielectric layer and at least one metal level; And an operating space, high-pressure side, separate high pressure interconnecting area and self-mask regions with drain region, had: one the 3rd N-shaped embedding layer at least partially, has extended and traversed operating space, high-pressure side; One second high pressure n trap, extend in fact and traverse operating space, high-pressure side, partial configuration is in the 3rd N-shaped embedding layer and another remaining portion is configured on the 3rd N-shaped embedding layer; One n trap, is configured to closest to self-mask regions; One p trap, tosses about in one of operating space, high-pressure side and is configured to just in the face of n trap; One first operating space, high-pressure side n+ trap, is configured in n trap; One operating space, high-pressure side p+ trap, is configured in p trap; And one second operating space, high-pressure side n+ trap, be configured in p trap.In some embodiment of the present invention, the second high pressure p-type deep trap of superhigh pressure n-type metal oxide semiconductor device may comprise plural discrete high pressure p-type deep trap section.
In one embodiment of the invention, at least one dielectric layer may comprise one and be configured at interlayer dielectric layer on substrate and a metal intermetallic dielectric layer, and at least one metal level may comprise one is configured at the second metal level that the first metal on interlayer dielectric layer and one and the first metal layer separated metal intermetallic dielectric layer.In some embodiment of the present invention, the first metal layer is patterned to make to only have a part for the second metal level to be positioned on self-mask regions.In some other embodiment of the present invention, the second metal is patterned the part only having the first metal layer is positioned on self-mask regions.Further according to the present embodiment of the present invention, the part being aligned in the first metal layer on self-mask regions is a pattered region of the first metal layer.
In one embodiment of the invention, ultrahigh voltage metal oxide semiconductor device may comprise a substrate contact region in addition, aim at body region and source area, source area is positioned at tossing about of the side of body region, and source area is aimed at channel region, substrate contact region has a third high pressure p-type deep trap, and one is configured at substrate contact portion p+ trap in third high pressure p-type deep trap; And one along the separator of the patterning of substrate arrangement.
In one embodiment of the invention, ultrahigh voltage metal oxide semiconductor device can comprise one more in addition along the separator of the patterning of substrate arrangement.In some embodiment of the present invention, the separator of patterning is a field oxide layer.In some other embodiment of the present invention, the separator of patterning is one or more isolation structure of shallow trench.In some embodiment again of the present invention, the isolation structure of patterning may comprise a combination of a field oxide layer and one or more isolation structure of shallow trench.
Of the present invention one implements the manufacture method that pattern provides superhigh pressure n-type metal oxide semiconductor (UHV NMOS) device, and the method comprises provides a substrate; Inject a N-shaped embedding layer in substrate; Drive in an admixture of N-shaped embedding layer; Deposit an epitaxial loayer; Inject a high pressure p-type deep trap; Inject a high pressure n trap; Inject a n trap in operating space, high-pressure side; Inject a p trap in operating space, high-pressure side; Drive in an admixture of n trap; Inject a p top layer; Form a separator; Form a conductive layer; And inject a n-doping gradient structure in a drain region.
In one embodiment of the invention, inject the step of n-doping gradient structure in drain region and may comprise following additional step: inject a high pressure n trap, a drain side high pressure N-shaped deep trap and a drain side N-shaped trap one of at least; And inject a drain side n+ trap in high pressure n trap, drain side high pressure N-shaped deep trap and drain side n trap one of at least.
In some embodiment of the present invention, the manufacture method of superhigh pressure n-type metal oxide semiconductor device comprises in addition injects one source pole side n+ trap, one first operating space, high-pressure side n+ trap and one second operating space, high-pressure side n+ trap; And inject a substrate contact portion p+ trap, a main body side p+ trap and operating space, a high-pressure side p+ trap.
Of the present invention one additionally implements pattern provides according to the ultrahigh voltage metal oxide semiconductor device manufactured by method of the present invention.
These embodiments of the present invention and of the present invention other are implemented pattern and will the Shi Gengxian that following explanation inspected by accompanying drawing be coordinated clear with embodiment.But the present invention is defined especially by the right of enclosing.
Accompanying drawing explanation
Blanket the present invention is described after, please refer to the accompanying drawing that may not draw in proportion, wherein:
Figure 1A is the vertical view of display according to a ultrahigh voltage metal oxide semiconductor device of one embodiment of the invention.
Figure 1B is the detailed view of the ultrahigh voltage metal oxide semiconductor device of display Figure 1A.
Fig. 1 C is the more detailed view of the ultrahigh voltage metal oxide semiconductor device of display Figure 1B.
Fig. 2 is the vertical view of the known ultrahigh voltage metal oxide semiconductor device of display one.
Fig. 3 A is the profile of the known superhigh pressure n-type metal oxide semiconductor of display one.
Fig. 3 B is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of one embodiment of the invention.
Fig. 4 A is the vertical view of a memory cell of a superhigh pressure n-type metal oxide semiconductor device of foundation one embodiment of the invention.
Fig. 4 B is the profile of display superhigh pressure n-type metal oxide semiconductor device along the BB ' line of Fig. 4 A.
Fig. 5 is the profile that display is subject to a superhigh pressure n-type metal oxide semiconductor device of foundation one embodiment of the invention of a high temperature reverse bias reliability test.
Fig. 6 A is the graphic of a TCAD simulation result of a superhigh pressure n-type metal oxide semiconductor device of foundation one embodiment of the invention.
Fig. 6 B is the dopant profile of the drain region of a superhigh pressure n-type metal oxide semiconductor device of foundation one embodiment of the invention.
Fig. 6 C is the dopant profile of the admixture of the various types of drain region in the superhigh pressure n-type metal oxide semiconductor device according to various embodiment of the present invention.
Fig. 7 A is the superhigh pressure n-type metal oxide semiconductor profile experience some manufacturing step after of display according to one embodiment of the invention.
Fig. 7 B is the superhigh pressure n-type metal oxide semiconductor profile experience some manufacturing step after of display according to another embodiment of the present invention.
Fig. 7 C is the superhigh pressure n-type metal oxide semiconductor profile experience some manufacturing step after of display according to another embodiment again of the present invention.
Fig. 7 D is the superhigh pressure n-type metal oxide semiconductor profile experience some manufacturing step after of display according to another embodiment more of the present invention.
Fig. 8 is the process chart of display according to the various manufacturing steps of a superhigh pressure n-type metal oxide semiconductor device of one embodiment of the invention.
Fig. 9 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 10 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 11 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 12 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 13 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 14 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 15 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 16 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 17 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 18 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 19 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 20 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 21 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 22 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 23 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 24 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 25 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 26 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 27 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 28 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 29 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
Figure 30 A is the vertical view of display according to the single UHV memory cell of a kind of semiconductor device of one embodiment of the invention.
Figure 30 B is the vertical view of display according to the multiple UHV memory cell of a kind of semiconductor device of one embodiment of the invention.And
Figure 31 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.
[symbol description]
1: superhigh pressure n-type metal oxide semiconductor
2: substrate
4:p type epitaxial loayer
6:n type embedding layer
8: high pressure N-shaped trap
10: high pressure p-type deep trap
12:n trap
14:p trap
16:p top layer
18: field oxide layer
20: conductive layer
22: source side n+ trap
24: drain side n+ trap
25: outer admixture
26: the first operating space, high-pressure side n+ traps
28: the second operating space, high-pressure side n+ traps
30: substrate contact region p+ trap
32: main body side p+ trap
34: operating space, high-pressure side p+ trap
36: gate regions
40: main body and source area
42: drain region
44: operating space, high-pressure side
46: interlayer dielectric layer
48: the first metal layer
50: metal intermetallic dielectric layer
52: the second metal levels
101: superhigh pressure n-type metal oxide semiconductor
105: substrate
110:p type epitaxial loayer
112:n type embedding layer
112a: the first N-shaped embedding layer
112b: the second N-shaped embedding layer
112c: the three N-shaped embedding layer
114: high pressure N-shaped trap
114a: the first high pressure n trap
114b: the second high pressure n trap
116: high pressure p-type deep trap
116a: the first high pressure p-type deep trap
116b: the second high pressure p-type deep trap
116c: third high pressure p-type deep trap
118:n trap
120:p trap
122:p top layer
124: field oxide layer
126: conductive layer
128: high pressure n trap
130: source side n+ trap
132:n+ trap
133: outer admixture
134: the first operating space, high-pressure side n+ traps
136: the second operating space, high-pressure side n+ traps
138: son contact p+ trap
140: main body side p+ trap/main body side p trap
142: operating space, high-pressure side p+ trap
144: high pressure n trap/gate regions
146: main body and source area
148: drain region
150: operating space, high-pressure side
151: substrate contact region
152: interlayer dielectric layer
154: the first metal layer
156: metal intermetallic dielectric layer
158: the second metal levels
160: region
170: region
180: high pressure interconnecting area
190: superhigh pressure n-type metal oxide semiconductor structure
201: semiconductor device
210: substrate
220:n type embedding layer
225:n type embedding layer
240: high pressure p-type deep trap
250: high pressure N-shaped trap
260: operating space, high-pressure side
270: operating space, high-pressure side
280:n trap admixture
300: isolated area
310: conductive layer
320: high pressure n trap
330: the second operating space, high-pressure side n+ traps
340: operating space, high-pressure side p+ trap
350: high pressure N-shaped deep trap
360:n type trap
380:p top layer
390: discrete high pressure p-type deep trap section
400: discrete p top section
410: high pressure interconnection p-type trap
420: sub-contact zone p trap
430: main body and source electrode p trap
440: implanted layer
450: the second metal intermetallic dielectric layer
460: the three metal levels
470: the first metal layer
480: the second metal levels
500:n type epitaxial loayer
510: the oxide skin(coating) imbedded
520: silicon on insulated substrate
540: semiconductor device
541: superhigh pressure memory cell
560: operating space, high-pressure side
570: high pressure interconnecting area
580: self-mask regions
Embodiment
Hereinafter describing some embodiment of the present invention in detail with reference to accompanying drawing, is illustrate section Example of the present invention in accompanying drawing, but and the embodiment of not all.Various embodiment of the present invention may be specific in many different forms, and should not be construed as being limited to the embodiment proposed in this, otherwise, provide these embodiments to be make this specification meet and be applicable to legal provisions.
As in specification and right use, unless context clearly represents, otherwise singulative " ", " one " and " this " comprise plural reference.For example, " a kind of MOS device " mentioned comprises multiple this MOS device.
Although adopt specific term in this, they only be used in meaning that is general and that describe and not be the objects in order to limit.All buzz words (comprise as in this technology that uses and science buzz word) have and the meaning equivalent in meaning had the knack of art person and usually understand, unless buzz word is otherwise defined, otherwise the invention belongs to this.We will further understand those buzz words defined in such as common dictionary, should be construed as having haveing the knack of the meaning that art person understands usually belonging to the present invention.We will further understand, those buzz words such as, defined in common dictionary should be construed as having the consistent meaning of the meaning with them in the context of related art techniques and current specification.Unless specification so defines clearly in this, otherwise this conventional buzz word can not be explained with a kind of Utopian or too formal meaning.
The present invention proposes a kind of semiconductor device, more especially a kind of ultrahigh voltage metal oxide semiconductor device (UHV MOS), even if when device As time goes on uses, it still has the response elasticity of improvement.The present invention is the apparatus design with the reliability of improvement proposing to compare with known devices without any significantly increasing device area.
In some embodiment, ultrahigh voltage metal oxide semiconductor of the present invention defined by following: a metal oxide semiconductor transistor, one closest to the high pressure interconnecting area of metal oxide semiconductor transistor, a self-mask regions aimed at high pressure interconnecting area and one and metal oxide semiconductor transistor separate the operating space, high-pressure side (HSOR) of high pressure interconnecting area and self-mask regions.
According to one embodiment of the invention, a drain region of ultrahigh voltage metal oxide semiconductor device of the present invention comprises drain electrode (DDD) the type frame structure of a dual diffusion.In some embodiment, the drain type framework of dual diffusion of the present invention is different in essence in the drain type structure of a known dual diffusion.So, be further defined in this, a drain region of ultrahigh voltage metal oxide semiconductor device of the present invention comprises a doping gradient structure.
According to one embodiment of the invention, a drain region of a superhigh pressure n-type metal oxide semiconductor (UHV NMOS) device of the present invention may comprise a n-doping gradient structure.According to another embodiment of the present invention, a drain region of superhigh pressure p-type metal-oxide semiconductor (MOS) (UHV PMOS) device of the present invention may comprise a p-doping gradient structure.
Figure 1A is a ultrahigh voltage metal oxide semiconductor device of demonstration example is implemented in display vertical view according to of the present invention one.One gate regions 144, main body of the special display device of the ultrahigh voltage metal oxide semiconductor 101 of Figure 1A and source area 146 and a drain region 148, main body and source area 146 collectively comprise a body region and one source pole district.
The detailed view of a memory cell of ultrahigh voltage metal oxide semiconductor 101 of Figure 1B for being identified by the region 160 of Figure 1A.Figure 1B shows high pressure N-shaped trap 114 and a high pressure p-type deep trap 116 in addition, is configured at the conductive layer 126 that main body and source area 146 and are arranged in gate regions 144.A kind of n-doping gradient structure comprising the drain side n+ trap 132 that is surrounded by an outer admixture 133 is configured in drain region 148, and outer admixture 133 has the dopant concentration that one may be different from the drain side n+ trap 132 be more configured in a high pressure n-trap (HVN-well) 128.One metal level, such as a first metal layer 154, is also shown in Figure 1B.
The more detailed view of the memory cell of the ultrahigh voltage metal oxide semiconductor 101 that the region 170 that Fig. 1 C is Figure 1B identifies.Fig. 1 C is shown in the drain region 148 with a n-doping gradient structure of this enforcement demonstration example of the present invention, and it has the n+ trap 132 of an outer admixture 133, and a high pressure n trap 128.In comparison, Fig. 2 display only has a drain region 42 of the known devices of the drain side n+ trap 24 that is surrounded by an outer admixture 25.
Fig. 3 A is the profile of the known superhigh pressure n-type metal oxide semiconductor 1 of display one.The Partial Feature of superhigh pressure n-type metal oxide semiconductor 1 is gate regions 36, main body and drain region, source area 40, one 42 and an operating space, high-pressure side 44.Superhigh pressure n-type metal oxide semiconductor 1 comprises substrate 2 and p-type extension (p-epi) layer 4, enters and is wherein configured with dark (HVPD) trap 10 of multiple N-shaped embedding layer (NBL) 6, multiple high pressure N-shaped trap 8 and multiple high pressure p-type.One n trap 12 and a p trap 14 are configured in the p-type epitaxial layer 4 of operating space, high-pressure side 44.One p top layer 16 is configured at one to be defined in main body and the channel region between source area 40 and drain region 42.One field oxide (FOX) layer 18 is used for isolating some region of superhigh pressure n-type metal oxide semiconductor 1.
Superhigh pressure n-type metal oxide semiconductor 1 also comprises a conductive layer 20, such as one is configured at polysilicon layer on substrate 2.A series of n+ trap and p+ trap are configured in substrate, and substrate comprises one source pole side n+ trap 22, drain side n+ trap 24,1 first operating space, high-pressure side n+ trap 26,1 second operating space, high-pressure side n+ trap 28, substrate contact region p+ trap 30, main body side p+ trap 32 and operating space, a high-pressure side p+ trap 34.
Known superhigh pressure n-type metal oxide semiconductor 1 also comprises an interlayer dielectric (ILD) layer 46, the first metal layer 48, inter-metal dielectric (IMD) layer 50 and one second metal level 52 usually.
In comparison, Fig. 3 B is the profile of a kind of superhigh pressure n-type metal oxide semiconductor 101 according to one embodiment of the invention of display.The Partial Feature that superhigh pressure n-type metal oxide semiconductor 101 is possible is that a gate regions 144, comprises a body region and the main body both one source pole district and drain region, source area 146, one 148 and an operating space, high-pressure side (HSOR) 150.Superhigh pressure n-type metal oxide semiconductor 101 comprises a substrate 105 (it may be such as a p-type substrate or a n-type substrate), and a p-type epitaxial layer 110.In some embodiment of the present invention, N-shaped extension (n-epi) layer may be used, instead of p-type epitaxial layer 110.The non-limiting examples of substrate 105 may comprise system of crystallization and/or amorphous silicon, and the epitaxial silicon that silicon-on-insulator substrate framework, is combined except epitaxial loayer 110 or with epitaxial loayer 110, SiGe, now known or future are used in this those skilled in the art etc.
Multiple N-shaped embedding layer 112 possible configuration is throughout p-type epitaxial layer 110 and selectively extend in substrate 105.In the illustrative embodiments of Fig. 3 B, one first N-shaped embedding layer 112a is the boundary being configured at drain region 148, and in the adjacent isolated area in this drain region 148, and one of isolated area tosses about and to adjoin with operating space, high-pressure side 150; One second N-shaped embedding layer 112b is configured at main body and source area 146; And one the 3rd N-shaped embedding layer 112c at least partially configures to traverse operating space, high-pressure side 150, and one the 3rd N-shaped embedding layer 112c is the large boundary on drain region of configuration.In one embodiment of the invention, a part of possible configuration of the second N-shaped embedding layer 112b is in substrate 105.According to another embodiment of the present invention, the second N-shaped embedding layer 112b, another part or even another remaining part second N-shaped embedding layer 112b possible configuration are in such as p-type epitaxial layer 110.
Moreover according to some embodiment of the present invention, multiple high pressure n trap 114 possible configuration is in p-type epitaxial layer 110 and may extend in substrate 105.In the illustrative embodiments of Fig. 3 B, one first high pressure n trap 114a traverses channel region from main body and source area 146 extension and arrives drain region 148.In this illustrative embodiments, one second high pressure n trap 114b extends in fact and traverses operating space, high-pressure side 150.
Dark (HVPD) trap 116 possible configuration of multiple high pressure p-type in p-type epitaxial layer 110, and extends in substrate 105 in some cases.In the illustrative embodiments of Fig. 3 B, one first high pressure p-type deep trap 116a is configured at main body and source area 146, one second high pressure p-type deep trap 116b is configured in an isolated area between drain region 148 and operating space, high-pressure side 150, and a third high pressure p-type deep trap 116c is configured at a substrate contact region 151, substrate contact region 151 aims at main body and source area 146, and main body and source area 146 are positioned at tossing about of the side main body and source area 146 aimed at channel region.
One n trap 118 and a p trap 120 are configured in operating space, high-pressure side 150, and a p top layer 122 is configured at one to extend to the channel region of drain region 148 from main body and source area 146.One field oxide layer 124 and a conductive layer 126 have also been configured in the superhigh pressure n-type metal oxide semiconductor 101 of Fig. 3 B.
In the illustrative embodiments of the present invention being shown in Fig. 3 B, a n-doping gradient structure of drain region comprises one and is configured at high pressure n trap 128 in drain region 148.In addition, the n-doping gradient structure of drain region comprises one and has been configured at drain side n+ trap 132 in high pressure n trap 128.Further according to this kind of illustrative embodiments of the present invention, the pattern of admixture of these traps of dopant concentration and the n-doping gradient structure that or even may be used in drain region 148 may be different.
In one embodiment of the invention, the dopant concentration of high pressure n trap 128 be less than drain side n+ trap 132 dopant concentration to define n-doping gradient structure.In some embodiment of the present invention, the dopant concentration in high pressure n trap 128 is 1/10th of the dopant concentration in drain side n+ trap 132.According to one embodiment of the invention, the dopant concentration of a drain side n+ trap 132 may from about 1 × 10 13atom/cm 3to about 1 × 10 18atom/cm 3, and the dopant concentration of a high pressure n trap 128 may from about 1 × 10 12atom/cm 3to about 1 × 1017 atom/cm 3.In some embodiment of the present invention, for example, the dopant concentration in drain side n+ trap 132 may be similar to about 1 × 10 13atom/cm 3, and the dopant concentration in high pressure n trap 128 may be similar to about 10 12atom/cm 3.
The illustrative embodiments of the superhigh pressure n-type metal oxide semiconductor 101 of Fig. 3 B also comprises son contact p+ trap 138, main body side p+ trap 140, one source pole side n+ trap 130,1 first operating space, high-pressure side n+ trap 134,1 second operating space, high-pressure side n+ trap 136 and operating space, a high-pressure side p+ trap 142.In some embodiment of the present invention, the second N-shaped embedding layer 112b lies prostrate below source side n+ trap 130 with main body side p trap 140.According to the present embodiment of Fig. 3 B, dielectric and metal level comprise an interlayer dielectric layer 152, are configured with a first metal layer 154 on it.One metal intermetallic dielectric layer 156 is configured between the first metal layer 154 and one second metal level 158.
Fig. 4 A is the vertical view of a memory cell of a superhigh pressure n-type metal oxide semiconductor device of foundation one embodiment of the invention.Fig. 4 B is the profile of display superhigh pressure n-type metal oxide semiconductor device along the BB ' hatching of Fig. 4 A.The superhigh pressure n-type metal oxide semiconductor of Fig. 4 B is similar in fact the device of Fig. 3 B; But in order to support further description, some region of superhigh pressure n-type metal oxide semiconductor 101 shows with high brightness in Fig. 4 B.Generally speaking, operating space, high-pressure side 150 (being intended to absolutely not by theoretical institute boundary) is designed to perform the level between gate drive signal needed change, from one ground connection-low reference voltage to the high voltage being intended to treat to be transmitted by device.
Superhigh pressure n-type metal oxide semiconductor structure 190 is designed to have a breakdown voltage.In some embodiment of the present invention, the breakdown voltage of superhigh pressure n-type metal oxide semiconductor structure 190 is similar to about 700V or higher.
High pressure interconnecting area 180 be configured at superhigh pressure n-type metal oxide semiconductor structure 190 between drain region 148 and operating space, high-pressure side 150.When being not intended to by theoretical institute's boundary, superhigh pressure n-type metal oxide semiconductor structure 190 is designed to have a self-mask regions, it is configured under high pressure interconnecting area 180 and also aims at high pressure interconnecting area 180 in fact, to isolate the transistor operation of superhigh pressure n-type metal oxide semiconductor structure 190 and operating space, high-pressure side 150.
The test of a kind of high temperature reverse bias (HTRB) may be used as the measurement of device reliability.Fig. 5 is the profile that a superhigh pressure n-type metal oxide semiconductor device of display foundation one embodiment of the invention is subject to a high temperature reverse bias test.High temperature reverse bias test measurement device stand a reverse bias be subject to device assembly simultaneously can the ability of patient most high ambient temperature.Device also may expose continuously and continues for some time to high temperature reverse bias condition, is also called as stress time (stress time).In some test, semiconductor device of the present invention is at the temperature of about 150 DEG C and to nearly about 560 volts or higher high pressure are subject to the stress time of a high temperature reverse bias test more than 168 hours.According to some embodiment, be subject to the breakdown voltage of the ultrahigh voltage metal oxide semiconductor of the present invention of these high temperature reverse bias conditions, after being exposed to high temperature reverse bias test condition, in fact not by reliability and the elasticity effect of the exemplary illustration of structure of the present invention.
Fig. 6 A is the graphic of the result of a superhigh pressure n-type metal oxide semiconductor device one TCAD emulation of foundation one embodiment of the invention.The TCAD Emulating display of Fig. 6 A traverses the stress level of apparatus structure, and wherein the weakest point of device is closest to the drain region 148 of device.Therefore, be intended to absolutely not by theoretical institute boundary, the result (display do not have in fact the deterioration of device performance) of high temperature reverse bias test advises out the drain electrode-type structure of the dual diffusion represented with the drain side n+ trap 132 be configured in high pressure n trap 128, to strengthen and to improve the stability of the drain side of superhigh pressure n-type metal oxide semiconductor 101 of the present invention.
Fig. 6 B is the dopant profile of the drain region of a superhigh pressure n-type metal oxide semiconductor device of foundation one embodiment of the invention.More especially, Fig. 6 B is the dopant profile of the doping gradient structure of the drain region 148 of representative graph 6A.Varied concentration system is shown in down: as distribution map (uses the logarithmic scale/cm of the atomicity of a radix 10 3) shown in various form and aspect about from substrate one upper surface measure varying depth and Fig. 6 A drain region 148 in various width.For example, as shown in Figure 6B, the maximum dopant concentration of the doping gradient structure of drain region (that is in drain side n+ trap) is approximately 4 × 10 16atom/cm 3, and the minimum dopant concentration of the doping gradient structure of drain region (that is in HVN trap) is approximately 5 × 10 15atom/cm 3.
Fig. 6 C is the dopant profile of the admixture of the various types of the doping gradient structure of the drain region of a superhigh pressure n-type metal oxide semiconductor device according to various embodiment of the present invention.Y-axis line represents that dopant concentration uses the logarithmic scale/cm of the atomicity of a radix 10 3, and x-axis is the degree of depth of representative from a surface measurement of substrate.In some embodiment of the present invention, the concentration of arsenic may from about 5 × 10 in drain side n+ trap 13atom/cm 3be changed to about 1 × 10 18atom/cm 3, and may from being less than about 1 × 10 in high pressure n trap 11atom/cm 3be changed to about 5 × 10 13atom/cm 3.In some other embodiment of the present invention, the concentration of boron may from being greater than about 2 × 10 in drain side n+ trap 14atom/cm 3be changed to about 2.5 × 10 16atom/cm 3, and may from about 1 × 10 in high pressure n trap 14atom/cm 3be changed to about 2 × 10 14atom/cm 3.In some embodiment again of the present invention, the concentration of phosphorus may from about 2 × 10 in drain side n+ trap 16atom/cm 3be changed to about 4 × 10 17atom/cm 3, and may from about 1 × 10 in high pressure n trap 12atom/cm 3be changed to about 2 × 10 16atom/cm 3.Merging when the admixture of plural pattern is the doping gradient structure for defining according to the drain region of some embodiment of the present invention, the drawing of Fig. 6 C may be merged.
Of the present invention another implements manufacture or the manufacture method that pattern provides a kind of semiconductor device.Generally speaking, the manufacture method according to a kind of semiconductor device of some embodiment of the present invention may comprise: the substrate of prepared silicon wafer or provide a silicon wafer with a substrate.In specific words, the manufacture method of a kind of semiconductor device of the present invention is about a kind of ultrahigh voltage metal oxide semiconductor device with a doping gradient structure of manufacture.
Fig. 8 is the process chart of display according to the various manufacturing steps of the superhigh pressure n-type metal oxide semiconductor device of one embodiment of the invention.According to Fig. 8, a kind of manufacture method of semiconductor device 201 comprises provides a substrate 210, injects a N-shaped embedding layer 220 and enters substrate, and drive in the admixture of N-shaped embedding layer 225.General description itself may comprise other sub-steps not needing to be identified in some step of the method.For example, also will comprise about these steps of injection one admixture (be use for example photoetching and produce in a kind of injection of this this) and a mask layer is provided and just removes this one deck once executed implantation step.Have the knack of art person and will appreciate that these additional steps under the help of this disclosure.Fig. 7 A be display superhigh pressure n-type metal oxide semiconductor experience according to one embodiment of the invention the setting being illustrated in this, inject and profile after driving in step.
A kind of manufacture method of semiconductor device 201 may comprise in addition: deposit an epitaxial loayer 230, such as be p-type epitaxial layer; Inject a high pressure p-type deep trap 240, inject a high pressure n trap 250; Inject a n trap in operating space, high-pressure side 260; Inject a p trap in operating space, high-pressure side 270; And drive in n trap admixture 280.Fig. 7 B is the profile of display superhigh pressure n-type metal oxide semiconductor after these steps of the manufacture method of a kind of semiconductor device 201 of experience foundation one embodiment of the invention.
A kind of method that semiconductor device 201 manufactures may comprise in addition: inject a p top layer 290; Such as form an isolated area 300 by a field oxide layer of growing up; Form a conductive layer 310, such as a polysilicon layer is according to one embodiment of the invention; Inject a high pressure n trap 320; Inject one source pole side n+ trap, a drain side n+ trap, one first operating space, high-pressure side n+ trap and one second operating space, high-pressure side n+ trap 330; And inject a son contact p+ trap, a main body side p+ trap and operating space, a high-pressure side p+ trap 340.According to one embodiment of the invention, the area that the N-shaped admixture that may produce high pressure injects defined by field oxide layer at least partly.In other embodiments of the present invention, photoetching may be used for further defining the injection area for HVN-ion implantation.
According to some embodiment of the present invention, isolated area may comprise one or more shallow trench isolation (STI) structure.In some embodiment of the present invention, isolated area may comprise a field oxide layer and one or more isolation structure of shallow trench.
In one embodiment of the invention, the angle of inclination defining the angle of the high pressure N-shaped ion implantation relative to a vertical line (being substantially perpendicular to the surface of ion substrate to be implanted) is approximately zero.That is in some embodiment of the present invention, high pressure N-shaped ion does not almost have the mode at angle of inclination to be injected into.In other embodiments of the present invention, angle of inclination is at least about 0.5 degree, at least about 1.6 degree, at least about 7 degree, about 7 degree to about 30 degree or extremely nearly about 60 degree.Fig. 7 C is the profile of display superhigh pressure n-type metal oxide semiconductor after these steps of the manufacture method of a kind of semiconductor device 201 of experience foundation one embodiment of the invention.
Step deposition one interlayer dielectric that a kind of manufacture method of semiconductor device 201 may comprise in addition, deposit a first metal layer, deposit a metal intermetallic dielectric layer and deposition one second metal level and form a pad pattern in superhigh pressure n-type metal oxide semiconductor.Fig. 7 D is the profile of display superhigh pressure n-type metal oxide semiconductor after these steps of the manufacture method of a kind of semiconductor device 201 of experience foundation one embodiment of the invention.
Ultrahigh voltage metal oxide semiconductor device of the present invention may be applied for example under mixing-pattern or analog circuit design.The non-limiting examples that ultrahigh voltage metal oxide semiconductor device of the present invention can have the place of applicability comprises LED illumination, power saving fluorescent lamps, electronic stabilization apparatus and the driver for motor and other equipment.When being not intended to be restricted, as use the test of high temperature reverse bias the reliability of ultrahigh voltage metal oxide semiconductor of the present invention of demonstrating make this device be applicable to the high-voltage applications of these and other majority.
Inventor has been susceptible to the structural design of other patterns of the majority of the stability of the improvement caused at drain region.Fig. 9 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.In each except the high pressure n trap 128 that a high pressure N-shaped deep trap 350 replaces drain region 148, the similar of the superhigh pressure n-type metal oxide semiconductor of Fig. 9 is in the structure of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D.
Figure 10 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Except in drain region a multi-layer n-type doped structure be used except each in, the similar of the superhigh pressure n-type metal oxide semiconductor of Figure 10 is in the structure of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D.The illustrative enforcement demonstration example of Figure 10 shows a high pressure N-shaped deep trap 350 and a high pressure n trap 128 is configured in drain region 148.One drain side n+ trap 132 is configured in high pressure n trap 128.
Figure 11 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.In each except being used except another multi-layer n-type doped structure in drain region, the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D of the superhigh pressure n-type metal oxide semiconductor of Figure 11.The illustrative enforcement demonstration example of Figure 11 shows a N-shaped trap 360 and a high pressure n trap 128 is configured in drain region 148.One drain side n+ trap 132 is configured in high pressure n trap 128.
Figure 12 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.In each except being used except another multi-layer n-type doped structure again in drain region, the similar of the superhigh pressure n-type metal oxide semiconductor of Figure 12 is in the structure of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D.The illustrative enforcement demonstration example of Figure 12 shows n trap 360, high pressure N-shaped deep trap 350 and a high pressure n trap 128 is configured in drain region 148.One drain side n+ trap 132 is configured in high pressure n trap 128.
Figure 13 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.In to have except an extra p top layer 380 except the superhigh pressure n-type metal oxide semiconductor of Figure 13 each, the similar of the superhigh pressure n-type metal oxide semiconductor of Figure 13 is in the structure of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D.Further implement demonstration example according to this kind, the admixture for additional p top layer 380 may be injected at the high pressure n trap 144 of channel region, further drives in the expectation degree of depth in additional p top layer 380 to substrate 105 subsequently.According to the illustrative embodiments of Figure 13, additional p top layer may be placed in the somewhere within the interface of substrate 105 with p-type epitaxial layer 110.According in other embodiments of the present invention, additional p top layer 380 may to be placed within the HVn trap 144 of channel region Anywhere.In other embodiments again of the present invention, additional p top layer 380 may be placed in the substrate 105 of below substrate 105 and the interface of p-type epitaxial layer 110.
One embodiment of the invention provide a kind of structure with the p top layer of more than three or three.Each p top layer may be injected into and be driven into the desired locations in substrate, as illustrated further in this.The position of these p top layers of more than three or three may be within substrate Anywhere, as illustrated further again in this.
In other embodiments again, superhigh pressure n-type metal oxide semiconductor of the present invention has a single p top layer, but p top layer may use the program as illustrated further in this and be injected into and be driven into substrate.Further according to the present embodiment of the present invention, p top layer may to be designed to be placed within the HVn trap 144 of channel region Anywhere; The upper, middle and lower of Jie are just in time handed at p-type epitaxial layer 110 and substrate 105; Or only have within substrate 105.
Figure 14 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor device of another embodiment of the present invention.In not have except a p top layer 122 except the superhigh pressure n-type metal oxide semiconductor of Figure 14 each, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 14 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.
Figure 15 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor device of another embodiment of the present invention.In to be injected to except plural discrete high pressure p-type deep trap section 390 except the high pressure p-type deep trap 116 of Fig. 7 D in high pressure interconnecting area 180 each, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 15 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.For example, the superhigh pressure n-type metal oxide semiconductor of Figure 15 has three discrete high pressure p-type deep trap sections 390.According to one embodiment of the invention, the size of each and the shape of plural discrete high pressure p-type deep trap section may change or have identical size and/or shape.According to the embodiment with plural discrete high pressure p-type deep trap section, the distance between each discrete high pressure p-type deep trap section may be identical or different in fact.
Figure 16 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor device of another embodiment of the present invention.In to have except plural discrete p top section 400 except the p top layer of Figure 16 each, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 16 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.For example, the superhigh pressure n-type metal oxide semiconductor of Figure 16 has eight separation discrete p top sections 400.According to one embodiment of the invention, the size of each and the shape of plural discrete p top section may change or have same size and/or shape.Plural discrete p top section 400 may be positioned the degree of depth identical in fact in substrate, or the degree of depth of discrete p top section 400 may change within substrate.According to the embodiment with plural discrete p top section, the distance between each discrete p top section may be identical or different in fact.
Figure 17 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Except using a high pressure interconnection p-type trap 410 but not in each except high pressure p-type deep trap 116 in the high pressure interconnecting area 180 of Fig. 7 D, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 17 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.
Figure 18 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Under the superhigh pressure n-type metal oxide semiconductor structure of Fig. 7 D, the superhigh pressure n-type metal oxide semiconductor structure of Figure 18 does not have the p-type epitaxial layer or N-shaped embedding layer that are shown in Fig. 7 D.In addition, the superhigh pressure n-type metal oxide semiconductor structure of Figure 18 adopts high pressure interconnection p-type trap 410, sub-contact zone p trap 420 and a main body and source electrode p trap 430, instead of the high pressure p-type dark 116 of Fig. 7 D.The superhigh pressure n-type metal oxide semiconductor device being shown in Figure 18 provides a kind of low cost solution, and it uses a kind of shallow p trap technique that may be suitable for some high-voltage applications.
Figure 19 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.The structure of the superhigh pressure n-type metal oxide semiconductor of Figure 19 is the change of the structure (demonstrate field oxide layer 124 and can have change framework) of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D.For example, the field oxide layer 124 of Figure 19 is the local mask being designed to provide substrate in channel region, uses and another kind of admixture may be injected in substrate to form an implanted layer 440.
Figure 20 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.The structure of the superhigh pressure n-type metal oxide semiconductor device of Figure 20 demonstrates may to use according to one embodiment of the invention only has a metal level.
Figure 21 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.It is be configured between the second metal level 158 and one the 3rd metal level 460 that the structure of the superhigh pressure n-type metal oxide semiconductor device of Figure 21 demonstrates one second metal intermetallic dielectric layer 450.In other embodiments again of the present invention, a superhigh pressure n-type metal oxide semiconductor device may be designed to have the metal level of more than three.
Figure 22 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.That in each except the first metal layer 154 being different from Fig. 7 D, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 22 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D at a first metal layer 470 of the superhigh pressure n-type metal oxide semiconductor except Figure 22.As shown in figure 22, the first metal layer 470 is designed to allow to only have the second metal level 158 to be attached on high pressure interconnecting area 180.
Figure 23 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.That in each except the second metal level 158 being different from Fig. 7 D, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 23 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D at one second metal level 480 of the superhigh pressure n-type metal oxide semiconductor except Figure 23.As shown in figure 23, the second metal level 480 is designed to allow to only have the first metal layer 154 to be attached on high pressure interconnecting area 180.
Figure 24 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Be in be designed to be attached to except on high pressure interconnecting area 180 each in a pattered region of a first metal layer 490 of the superhigh pressure n-type metal oxide semiconductor except Figure 24, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 24 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.
Figure 25 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.In each except the p-type epitaxial layer 110 of the superhigh pressure n-type metal oxide semiconductor except a N-shaped epitaxial loayer 500 permutation graph 7D, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 25 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.When being not intended to by principle institute boundary, the use of N-shaped epitaxial loayer 500 eliminates the needs of the N-shaped embedding layer 112 of the source area of the high pressure n trap 114 in channel region.In addition, the use of N-shaped epitaxial loayer 500 need operation bias voltage in fixing-that is, identical in fact with the voltage of sub-contact site in source electrode.
Figure 26 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Except the p-type epitaxial layer 110 of the superhigh pressure n-type metal oxide semiconductor of a N-shaped epitaxial loayer 500 permutation graph 7D, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 26 is similar to the structure of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D most.But the superhigh pressure n-type metal oxide semiconductor of Figure 26 has been adapted to make the N-shaped embedding layer 112 of the source area in channel region and a part for high pressure n trap 114 holdout device structure.
Figure 27 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Compared to the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D, the superhigh pressure n-type metal oxide semiconductor of Figure 27 comprises a N-shaped epitaxial loayer 500 and does not have a p-type epitaxial layer 110.In addition, the superhigh pressure n-type metal oxide semiconductor of Figure 27 adopts a multi-layer n-type doped structure in drain region 148.According to the illustrative embodiments of Figure 27, a high pressure N-shaped deep trap 350 and a high pressure n trap 128 are configured in drain region 148.One drain side n+ trap 132 is configured in high pressure n trap 128.In some other embodiment of the present invention, both a n trap and a high pressure N-shaped deep trap 350 may by use (not shown)s.In other embodiments again of the present invention, a n trap may be used, instead of high pressure N-shaped deep trap 350 (not shown).
Figure 28 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.It not the substrate 105 only used as shown in the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D, the superhigh pressure n-type metal oxide semiconductor of Figure 28 adopts a silicon-on-insulator (SOI) structure 520, and it has a substrate 105 and and is configured at buried oxide skin(coating) 510 wherein.
Figure 29 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.Are being superhigh pressure n-type metal oxide semiconductor of being used in Figure 29 except isolation structure of shallow trench 530 in replace except the field oxide layer 124 of the superhigh pressure n-type metal oxide semiconductor of Fig. 7 D almost each, the structure of the superhigh pressure n-type metal oxide semiconductor of Figure 29 is the structure of the superhigh pressure n-type metal oxide semiconductor of similar Fig. 7 D.The structure of Figure 29 is particularly useful in the size reducing superhigh pressure n-type metal oxide semiconductor
Figure 30 A is the vertical view of display according to a kind of semiconductor device of one embodiment of the invention.A kind of semiconductor device 540 of the present invention may be designed to have a superhigh pressure memory cell 541, as shown in fig. 30 a.Figure 30 B is the vertical view of display according to a kind of semiconductor device of another embodiment of the present invention.Semiconductor device 550 of the present invention may be designed to have two superhigh pressure memory cell 551, as shown in figure 30b.Really, a kind of semiconductor device of the present invention may be designed to have plural superhigh pressure memory cell.
Figure 31 is the profile of display according to a superhigh pressure n-type metal oxide semiconductor of another embodiment of the present invention.When explaining, the region of the superhigh pressure n-type metal oxide semiconductor of Figure 31 comprises operating space, high-pressure side 560, high pressure interconnecting area 570 and a self-mask regions 580.According to one embodiment of the invention, high pressure interconnecting area 570 is designed to be provided in the interconnection between superhigh pressure n-type metal oxide semiconductor structure and operating space, high-pressure side 560.According to some embodiment of the present invention, isolated high-voltage side, self-mask regions 580 (operating space, high-pressure side 560) and low-pressure side (superhigh pressure n-type metal oxide semiconductor structure).
When being not intended to by theoretical institute's boundary, the degree of depth according to the high pressure n trap 114 of the operating space, high-pressure side 560 of some embodiment of the present invention is that operation with high pressure can be continued by this device.When being further intended to not by theoretical institute's boundary, the injection of p top layer 122 allows reduction surface field (RESURF) effect to treat to be implemented in this device.When being further intended to not by theoretical institute's boundary, the N-shaped embedding layer 112 of operating space, high-pressure side 560 is designed to avoid puncturing to substrate or earth terminal from operating space, high-pressure side 560.Again when being further intended to not by theoretical institute's boundary, the N-shaped embedding layer 112 according to the source area 146 of some embodiment of the present invention may be designed to isolation source electrode and substrate or earth terminal.
In some embodiment of the present invention, operating space, high-pressure side 560 is designed to support at least approximately 560V, at least approximately 600V or at least approximately 650V.In one embodiment of the invention, at least approximately 700V may can be supported in operating space, high-pressure side 560.
Enforcement pattern of the present invention provides the several methods manufacturing semiconductor device of the present invention.Have the knack of any technique that art person is known after consulting this specification, may for the manufacture of semiconductor device of the present invention.
To appear in one's mind in the brain haveing the knack of the art person's (there is the benefit of the instruction provided in above-mentioned explanation and correlative type) affiliated by these inventions in this majority amendment of the present invention proposed and other embodiments.Therefore, we it will be appreciated that the present invention is not limited to disclosed specific embodiment, and within the category that amendment and other embodiments are intentions is included in following right.In addition, although above-mentioned explanation and relevant some in assembly and/or function graphic illustrate in the context of combination and describe illustrative embodiments, but we should recognize the different combination of assembly and/or function, may be provided by alternate embodiment under the category not deviating from following right.In this, for example, the combination of those assemblies and/or function of being different from above-mentioned detailed description is also considered to be and may be suggested in some of following right.Although adopt specific term in this, they only be used in meaning that is general and that describe and not be the objects in order to limit.

Claims (23)

1. a ultrahigh voltage metal oxide semiconductor device, comprising:
One metal oxide semiconductor transistor, is arranged in a drain region, and this metal oxide semiconductor transistor has a doping gradient structure;
One high pressure interconnecting area, close to this metal oxide semiconductor transistor, this high pressure interconnecting area has at least one dielectric layer and at least one metal level;
One self-mask regions, to aim at this high pressure interconnecting area close to this metal oxide semiconductor transistor; And
One operating space, high-pressure side, has separated this high pressure interconnecting area and this self-mask regions with this metal oxide semiconductor transistor.
2. ultrahigh voltage metal oxide semiconductor device according to claim 1, wherein this doping gradient structure comprise a high pressure n-trap, a high pressure N-shaped deep trap and a N-shaped trap one of at least.
3. ultrahigh voltage metal oxide semiconductor device according to claim 1, wherein this doping gradient structure more comprises a n+ trap.
4. a superhigh pressure n-type metal oxide semiconductor device, comprising:
One substrate, has an epitaxial loayer, and this epitaxial layer portion is configured in this substrate;
One drain region, has:
One n-doping gradient structure, and
One first N-shaped embedding layer, is positioned at a boundary of this drain region.
5. superhigh pressure n-type metal oxide semiconductor device according to claim 4, wherein this epitaxial loayer is a p-type epitaxial layer.
6. superhigh pressure n-type metal oxide semiconductor device according to claim 4, wherein this n-doping gradient structure comprise a high pressure n-trap, a high pressure N-shaped deep trap and a N-shaped trap one of at least.
7. superhigh pressure n-type metal oxide semiconductor device according to claim 6, wherein this n-doping gradient structure more comprises a n+ trap.
8. superhigh pressure n-type metal oxide semiconductor device according to claim 4, more comprises:
One body region and one source pole district, relative with this drain region, this body region and this source area have:
One second N-shaped embedding layer, a part is configured in this substrate and another part is configured in this epitaxial loayer,
One first high pressure p-type deep trap, partial configuration is in this second N-shaped embedding layer, and a remaining portion is configured on this second N-shaped embedding layer,
One main body p+ trap, is configured to define a body contact in this first high pressure p-type deep trap, and
One source pole n+ trap, is configured to define one source pole contact site in this first high pressure p-type deep trap, and wherein this second N-shaped embedding layer is positioned under this main body p+ trap and this source electrode n+ trap;
One channel region, separated from this body region and this source area this drain region, this channel region has one first high pressure n trap, extends traverse this channel region and arrive this drain region from this body region and this source area; And
One gate regions, close to this body region and this source area, and part is in alignment with on this channel region, and this gate regions has a conductive layer.
9. superhigh pressure n-type metal oxide semiconductor device according to claim 8, wherein this channel region more comprises a p top zone, and this p top zone is along a mask upper surface configuration of this substrate.
10. superhigh pressure n-type metal oxide semiconductor device according to claim 9, wherein this p top zone comprises multiple discrete p tops section.
11. superhigh pressure n-type metal oxide semiconductor devices according to claim 8, more comprise:
One self-mask regions, aims at this boundary of this drain region, and this boundary of this drain region is positioned at tossing about of the side of this drain region aimed at this channel region, and this self-mask regions has one second high pressure p-type deep trap;
One high pressure interconnecting area, is aligned on this self-mask regions, has:
At least one dielectric layer, and
At least one metal level; And
One operating space, high-pressure side, has separated this high pressure interconnecting area and this self-mask regions with this drain region, has had:
One the 3rd N-shaped embedding layer at least partially, extends and traverses this operating space, high-pressure side,
One second high pressure n trap, extend and traverse this operating space, high-pressure side, partial configuration is in the 3rd N-type embedding layer and another remaining portion is configured on the 3rd N-type embedding layer,
One n trap, is configured to closest to this self-mask regions,
One p trap, tosses about in one of this operating space, high-pressure side and is configured to just in the face of this N trap,
One first operating space, high-pressure side n+ trap, is configured in this N trap,
One operating space, high-pressure side p+ trap, is configured in this P trap, and
One second operating space, high-pressure side n+ trap, is configured in this P trap.
12. superhigh pressure n-type metal oxide semiconductor devices according to claim 11, wherein this second high-voltage P-type deep trap comprises plural discrete high-voltage P-type deep trap section.
13. superhigh pressure n-type metal oxide semiconductor devices according to claim 11, wherein:
This at least one dielectric layer comprises one and is configured at interlayer dielectric layer on this substrate and a metal intermetallic dielectric layer, and
This at least one metal level comprises one and is configured at the second metal level that the first metal on this interlayer dielectric layer and one and this first metal layer separated this metal intermetallic dielectric layer.
14. superhigh pressure n-type metal oxide semiconductor devices according to claim 12, wherein this first metal layer be patterned to make to only have a part for this second metal level to adjoin this self-mask regions and position on this self-mask regions.
15. superhigh pressure n-type metal oxide semiconductor devices according to claim 12, wherein this second metal level be patterned to make the part only having this first metal layer adjoin this self-mask regions and position on this self-mask regions.
16. superhigh pressure n-type metal oxide semiconductor devices according to claim 15, wherein this part is a pattered region of this first metal layer.
17. superhigh pressure n-type metal oxide semiconductor devices according to claim 11, more comprise:
One substrate contact region, aim at this body region and this source area, this source area is positioned at tossing about of the side of this body region, and this source area is aimed at this channel region, and this substrate contact region has:
One third high pressure P moldeed depth trap, and
One substrate contact portion p+ trap, is configured in this third high pressure P moldeed depth trap; And
The separator of one patterning, along this substrate arrangement.
18. superhigh pressure n-type metal oxide semiconductor devices according to claim 11, more comprise the separator of a patterning, along this substrate arrangement.
19. superhigh pressure n-type metal oxide semiconductor devices according to claim 18, wherein the separator of this patterning comprise a field oxide layer and one or more isolation structure of shallow trench one of at least.
20. 1 kinds of superhigh pressure n-type metal oxide semiconductor devices, comprising:
One substrate, has an epitaxial loayer, and this epitaxial layer portion is configured in this substrate;
One drain region, has:
One n-doping gradient district, and
One first N-shaped embedding layer, is positioned at a boundary of this drain region;
One body region and one source pole district, just in the face of this drain region, this body region and this source area have:
One second N-shaped embedding layer, partial configuration is in this substrate, and another part is configured in this epitaxial loayer,
One first high pressure p-type deep trap, partial configuration is in this second N-type embedding layer and a remaining portion is configured on this second N-shaped embedding layer,
One main body p+ trap, is configured to define a body contact in this first high pressure p-type deep trap, and
One source pole n+ trap, is configured to define one source pole contact site in this first high pressure p-type deep trap,
Wherein this second N-shaped embedding layer volt is below this main body p+ trap and this source electrode n+ trap;
One channel region, be separated this drain region and this body region and this source area, this channel region has:
One first high pressure n trap, extends from this body region and this source area and traverses this channel region and arrive this drain region, and
One p top zone, the upper surface along a mask of this substrate configures;
One gate regions, closest to this body region and this source area and part be aligned on this channel region, this gate regions has a conductive layer;
One self-mask regions, aims at this boundary of this drain region, and this boundary of this drain region is positioned at tossing about of the side of this drain region aimed at this channel region, and this self-mask regions has one second high-voltage P-type deep trap;
One high pressure interconnecting area, is aligned on this self-mask regions, has:
At least one dielectric layer, and
At least one metal level;
One operating space, high-pressure side, has separated this high pressure interconnecting area and this self-mask regions with this drain region, has had:
One the 3rd N-shaped embedding layer at least partially, extends and traverses this operating space, high-pressure side,
One second high pressure n trap, extend in fact and traverse this operating space, high-pressure side, a part is configured in the 3rd N-shaped embedding layer and another remaining portion is configured on the 3rd N-shaped embedding layer,
One n trap, is configured to closest to this self-mask regions,
One p trap, tosses about in one of this operating space, high-pressure side and is configured to just in the face of this n trap,
One first operating space, high-pressure side n+ trap, is configured in this n trap,
One operating space, high-pressure side p+ trap, is configured in this p trap, and
One second operating space, high-pressure side n+ trap, is configured in this p trap;
One substrate contact region, aim at this body region and this source area, this source area is positioned at tossing about of the side of this body region, and this source area is aimed at this channel region, and this substrate contact region has:
One third high pressure p-type deep trap, and
One substrate contact portion p+ trap, is configured in this third high pressure p-type deep trap; And
The separator of one patterning, along this substrate arrangement.
The manufacture method of 21. 1 kinds of superhigh pressure n-type metal oxide semiconductor devices, comprises the following steps:
One substrate is provided;
Inject a N-shaped embedding layer in this substrate;
Drive in an admixture of this N-shaped embedding layer;
Deposit an epitaxial loayer;
Inject a high pressure p-type deep trap;
Inject a high pressure n trap;
Inject a n trap in an operating space, high-pressure side;
Inject a p trap in this operating space, high-pressure side;
Drive in an admixture of this n trap;
Inject a p top layer;
Form a separator;
Form a conductive layer; And
Inject a n-doping gradient structure in a drain region.
22. manufacture methods according to claim 21, wherein inject the step of this n-doping gradient structure in this drain region and comprise:
Inject a high pressure n trap, a drain side high pressure N-shaped deep trap and a drain side N-shaped trap one of at least; And
Inject a drain side n+ trap in this high pressure n trap, this drain side high pressure N-shaped deep trap and this drain side N-shaped trap one of at least.
23. manufacture methods according to claim 21, more comprise the following steps:
Inject one source pole side n+ trap, one first operating space, high-pressure side n+ trap and one second operating space, high-pressure side n+ trap; And
Inject a substrate contact portion p+ trap, a main body side p+ trap and operating space, a high-pressure side p+ trap.
CN201310435383.0A 2013-09-24 2013-09-24 Ultra-high voltage semiconductor device and manufacturing method thereof Pending CN104465658A (en)

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