CN104465434B - Defect analysis method - Google Patents
Defect analysis method Download PDFInfo
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- CN104465434B CN104465434B CN201310444792.7A CN201310444792A CN104465434B CN 104465434 B CN104465434 B CN 104465434B CN 201310444792 A CN201310444792 A CN 201310444792A CN 104465434 B CN104465434 B CN 104465434B
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- defect
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The present invention proposes a kind of defect analysis method, defect is analyzed using defects analysis system, draw the quantity that can kill wafer yield to be measured, simultaneously, the defect of current layer film is carried out into coordinate with the defect of previous layer film to be superimposed, the quantity of the defect for killing wafer yield to be measured can be more accurately drawn, it is more accurate with the yield killing rate that this is calculated, the sensitiveness to defect monitoring can be increased, be easy to more accurately judge whether wafer is scrapped.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of defect analysis method.
Background technology
It is also more and more stricter to semiconductor technology requirement as semiconductor technology characteristic size is less and less.In wafer
(wafer) in manufacturing process, equipment or technique occur surprisingly causing crystal column surface that defect occurs（defect）, due to defect
The yield of wafer can be caused to be reduced, and serious meeting causes wafer directly to be scrapped.Defect analysis method of the prior art is generally in crystalline substance
Circle is formed during film layer, and the surface of film layer is scanned using photosignal, while collecting different test point feedbacks
Photosignal, the difference of adjacent area signal is compared afterwards, if difference value exceed preset standard (Spec), be denoted as lacking
Fall into.During actual production, all defect statistics can be got up, for calculating yield lethality（Yield Kill Rate）, and judge
Whether wafer is scrapped.
However, crystal column surface can be divided into multiple regions, workspace and virtual area can be divided into according to function（Dummy
Area）；The workspace is mainly the region for realizing circuit function, such as device region, metal contact wires etc.；The virtual area
Primarily to process requirements are formed in wafer, but are not involved in the region of circuit function, the virtual area is general in order to balance
The closeness of different crystal column surfaces, is conducive to the realization of CMP process.Because defect can be randomly occurring in wafer
The Anywhere region on surface, therefore, defect is understood some and is fallen into workspace, and another part is fallen into virtual area.But
The defect of different zones is also entirely different for the influence of the yield of product, for example, be formed in the defect in virtual area to good
The influence of rate is very small.However, as described above, typically being united according to the whole defect of wafer in actually detected
Count killing rate and judge whether to scrap, therefore, the yield lethality for calculating in the prior art is not very accurate, is sentenced with this
Whether disconnected wafer is scrapped also there is certain error.
And, the analysis method of prior art defect cannot also judge when during the defect of layer film falls within virtual area to after
Whether the circuit or line of layer have an impact.
The content of the invention
It is an object of the invention to provide a kind of defect analysis method, by increasing capacitance it is possible to increase the sensitiveness monitored to defect, accurately
Yield lethality of the defect to wafer is drawn, is easy to more accurately judge whether wafer is scrapped.
To achieve these goals, the present invention proposes a kind of defect analysis method, including step：
（1）Defects detection is carried out to wafer n-th layer film to be measured, the defects count and coordinate of n-th layer film is obtained；
（2）Judge the defect of n-th layer film whether beyond preassigned；If exceeding preassigned, into step（3）,
If without departing from preassigned, into step（5）；
（3）The defect of n-th layer film is analyzed using defects analysis system, is shown that n-th layer film defects are killed and is treated
Survey the quantity of wafer yield；
（4）Judge the quantity of the defect for killing wafer yield to be measured whether beyond preassigned；If exceeding preassigned,
Wafer to be measured is scrapped, if without departing from preassigned, into step（5）；
（5）The defect of n-th layer film is carried out into coordinate with the defect of N-1 layer films to be superimposed, n-th layer film and is drawn
The quantity of the defect of wafer yield to be measured is killed in N-1 layer films;
（6）Judge whether the quantity of the defect for killing wafer to be measured in n-th layer film and N-1 layer films calibrates beyond pre-
It is accurate；If exceeding preassigned, wafer to be measured is scrapped, if without departing from preassigned, carrying out follow-up production；
Wherein, the N is the natural number more than 0.
Further, the defects analysis system includes：
The crystal column surface to be measured is divided into workspace and virtual area；
Calculate the quantity that the defect that the workspace kills wafer yield to be measured is fallen into n-th layer film.
Further, the part being connected with N-1 layer films and M layer film circuits in n-th layer film is defined as
Workspace, wherein M are the natural number more than N.
Further, the part of circuit function will can be realized in n-th layer film with N-1 layer films electric isolution, with
And the part that can realize circuit function is electrically insulated in n-th layer film with M layer films, it is defined as workspace.
Further, will be electrically insulated for improving the crystal column surface to be measured with N-1 layer films in n-th layer film
The part of closeness, and M layer films electrically insulate the part of the closeness for improving the crystal column surface to be measured, define
It is the virtual area.
Further, after the defect of n-th layer film and the defect of N-1 layer films being carried out coordinate and is superimposed, then will
The defect of n-th layer film carries out coordinate and is superimposed with the workspace of M layer films, show that the defect of n-th layer film falls into M layers thin
The quantity of the defect of wafer yield to be measured can be killed in the workspace of film.
Further, judging that the defect of n-th layer film is fallen into the workspace of M layer films can kill wafer yield to be measured
Defect quantity whether exceed preassigned, if exceed preassigned, scrap wafer to be measured, if without departing from preassigned,
Then carry out follow-up production.
Compared with prior art, the beneficial effects are mainly as follows：Defect is carried out using defects analysis system
Analysis, draws the quantity that can kill wafer yield to be measured, meanwhile, by the defect of the defect of current layer film and previous layer film
Coordinate superposition is carried out, the quantity of the defect for killing wafer yield to be measured, the yield calculated with this can be more accurately drawn
Killing rate is more accurate, by increasing capacitance it is possible to increase to the sensitiveness of defect monitoring, be easy to more accurately judge whether wafer is scrapped.
Brief description of the drawings
Fig. 1 is the flow chart of defect analysis method in one embodiment of the invention.
Specific embodiment
Defect analysis method of the invention is described in more detail below in conjunction with schematic diagram, which show this hair
Bright preferred embodiment, it should be appreciated that those skilled in the art can change invention described herein, and still realize this hair
Bright advantageous effects.Therefore, description below is appreciated that widely known for those skilled in the art, and is not intended as
Limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer,
The present invention is more specifically described by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, is only used to conveniently, lucidly aid in illustrating the purpose of the embodiment of the present invention.
Fig. 1 is refer to, in the present embodiment, it is proposed that a kind of defect analysis method, including step：
（1）Defects detection is carried out to wafer n-th layer film to be measured, the defects count and coordinate of n-th layer film is obtained；
In step（1）In, the surface of film layer is scanned using photosignal while collecting different test point feedbacks
Photosignal method detection defect, and obtain the quantity and coordinate of defect.
（2）Judge the defect of n-th layer film whether beyond preassigned；If exceeding preassigned, into step（3）,
If without departing from preassigned, into step（5）；
In step（2）In, preassigned can be selected according to specific technique, not limited herein.
（3）The defect of n-th layer film is analyzed using defects analysis system, is shown that n-th layer film defects are killed and is treated
Survey the quantity of wafer yield；
In step（3）In, the defects analysis system includes：
The crystal column surface to be measured is divided into workspace and virtual area；
Wherein it is possible to the part being connected with N-1 layer films and M layer film circuits in n-th layer film is defined as
Workspace, can also will can realize the part of circuit function, and N with N-1 layer films electric isolution in n-th layer film
The part of circuit function can be realized in layer film with M layer films electric isolution, workspace is defined as；By n-th layer film
In the part of closeness for improving the crystal column surface to be measured, and M layer films electricity are electrically insulated with N-1 layer films
Isolate the part of the closeness for improving the crystal column surface to be measured, be defined as the virtual area, the virtual area is not
Circuit function can be realized.
Calculate the quantity that the defect that the workspace kills wafer yield to be measured is fallen into n-th layer film.
The workspace is mainly that by circuit function, when defect is fallen into the workspace, to wafer to be measured
Yield influence it is also just maximum, therefore be many to more accurately calculate defect to the killing rate of the yield of wafer to be measured
It is few, just first should accurately draw the quantity that defect is fallen into the workspace.
（4）Judge the quantity of the defect for killing wafer yield to be measured whether beyond preassigned；If exceeding preassigned,
Wafer to be measured is scrapped, if without departing from preassigned, into step（5）；
（5）The defect of n-th layer film is carried out into coordinate with the defect of N-1 layer films to be superimposed, n-th layer film and is drawn
The quantity of the defect of wafer yield to be measured is killed in N-1 layer films;
In step（5）In, if the defect of N-1 layer films fall into N-1 layers of virtual area, calculating N-1 layers
Will not be counted when killing wafer yield to be measured, if but during drawbacks described above but fall into the workspace of n-th layer film,
At this moment just should be by being counted after being superimposed of n-th layer film and N-1 layer films.
Preferably, after the defect of n-th layer film and the defect of N-1 layer films being carried out coordinate and is superimposed, then by N
The defect of layer film carries out coordinate and is superimposed with the workspace of M layer films, show that the defect of n-th layer film falls into M layer films
Workspace in can kill wafer yield to be measured defect quantity, likewise, in order to prevent from falling into virtual area in n-th layer film
Defect workspace is fall into M layers, accordingly, it would be desirable to the defect of virtual area and M layer films will be fallen into n-th layer film
Workspace carry out coordinate superposition, if the defect that virtual area is fallen into n-th layer film fall into the workspace of M layer films,
Should be calculated in the defect for killing wafer yield to be measured.
Next, it is determined that the defect of n-th layer film is fallen into the workspace of M layer films can kill lacking for wafer yield to be measured
Whether sunken quantity exceeds preassigned, if exceeding preassigned, wafer to be measured is scrapped, if without departing from preassigned, entering
The follow-up production of row.
（6）Judge whether the quantity of the defect for killing wafer to be measured in n-th layer film and N-1 layer films calibrates beyond pre-
It is accurate；If exceeding preassigned, wafer to be measured is scrapped, if without departing from preassigned, carrying out follow-up production.
Wherein, described N, M are the natural number more than 0, and e.g. 1,2,3 etc., and M is more than N.
Specifically, for example, when defects detection is carried out to the layer film of wafer to be measured 3rd, first judging that the defect for detecting is
It is no beyond preassigned, such as preassigned is 5%, if the ratio of defects for detecting is 4%, need not carry out extra analysis, directly
Connect and wafer to be measured is entered into subsequent production；
If the ratio of defects for detecting is 6%, the defect of the 3rd layer film is analyzed using defects analysis system, if
What defect fell into the 3rd layer film workspace is 4%, and remaining 2% falls into virtual area, then illustrate that the ratio of defects of the 3rd layer film does not reach
To Rejection standard, then, the defect of the 3rd layer film is carried out into coordinate with the defect of the 2nd layer film and is superimposed, if the 2nd layer film
Defect be 3%, but have 2% workspace for falling into the 3rd layer film, therefore the 2nd layer film and the 3rd layer film can kill crystalline substance to be measured
The ratio of defects of circle yield should be 4% plus 2% for 6% more than 5%, is now overlapped in the workspace with the 4th layer film, if superposition
Afterwards, only 4% defect is fallen into the workspace of the 4th layer film, then should regard the ratio of defects of the 3rd layer film less than Rejection standard, if
After superposition, 6% defect is entirely fallen in the workspace of the 4th layer film, then should scrap wafer to be measured, if the 2nd layer film is scarce
Fall into not falling with the workspace of the 3rd layer film, then wafer to be measured should be entered in subsequent production；
If the ratio of defects of the 3rd layer film is 6%, and entirely fall in workspace, then by the defect of the 3rd layer film with the 4th layer
Film（Do not formed）Workspace carry out coordinate superposition, because the workspace of the 4th layer film has been planned by semiconductor layout,
Although the 4th layer film is not formed, the coordinate of the 4th layer film workspace can be also obtained, if after superposition, only 4%
Defect is fallen into the workspace of the 4th layer film, then should regard the ratio of defects of the 3rd layer film less than Rejection standard, if after superposition, 6%
Defect is entirely fallen in the workspace of the 4th layer film, then should scrap wafer to be measured.
To sum up, in defect analysis method provided in an embodiment of the present invention, defect is divided using defects analysis system
Analysis, draws the quantity that can kill wafer yield to be measured, meanwhile, the defect of current layer film is entered with the defect of previous layer film
Row coordinate is superimposed, and can more accurately draw the quantity of the defect for killing wafer yield to be measured, is killed with the yield that this is calculated
Hinder rate more accurate, by increasing capacitance it is possible to increase to the sensitiveness of defect monitoring, be easy to more accurately judge whether wafer is scrapped.
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Belonging to any
Those skilled in the art, not departing from the range of technical scheme, to the invention discloses technical scheme and
Technology contents make the variation such as any type of equivalent or modification, belong to the content without departing from technical scheme, still
Belong within protection scope of the present invention.
Claims (7)
1. a kind of defect analysis method, including step：
(1) defects detection is carried out to wafer n-th layer film to be measured, the quantity and the coordinate of defect of defect in n-th layer film is obtained；
(2) judge the defects count of n-th layer film whether beyond preassigned；If exceeding preassigned, into step (3),
If without departing from preassigned, into step (5)；
(3) defect of n-th layer film is analyzed using defects analysis system, show that n-th layer film defects fall into workspace
Kill the quantity of wafer yield to be measured；
(4) judge the quantity for falling into workspace defect for killing wafer yield to be measured whether beyond preassigned；If beyond predetermined
Standard, then scrap wafer to be measured, if without departing from preassigned, into step (5)；
(5) defect of n-th layer film is carried out into coordinate with the defect of N-1 layer films to be superimposed, draws n-th layer film and N-1
The quantity that workspace kills the defect of wafer yield to be measured is fallen into layer film；
(6) judge whether the quantity of the defect for falling into workspace killing wafer to be measured in n-th layer film and N-1 layer films exceeds
Preassigned；If exceeding preassigned, wafer to be measured is scrapped, if without departing from preassigned, carrying out follow-up production；
Wherein, the N is the natural number more than 0.
2. defect analysis method as claimed in claim 1, it is characterised in that the defects analysis system includes：
The crystal column surface to be measured is divided into the workspace and virtual area.
3. defect analysis method as claimed in claim 2, it is characterised in that by n-th layer film with N-1 layer films and
The part of M layer films circuit connection is defined as workspace, and wherein M is the natural number more than N.
4. defect analysis method as claimed in claim 3, it is characterised in that will in n-th layer film with N-1 layer films electricity
Isolation can realize the part of circuit function, and can realize circuit function with M layer films electric isolution in n-th layer film
Part, be defined as workspace.
5. defect analysis method as claimed in claim 3, it is characterised in that will in n-th layer film with N-1 layer films electricity
Isolate the part of the closeness for improving the crystal column surface to be measured, and M layer films are electrically insulated for improving described treating
The part of the closeness of crystal column surface is surveyed, the virtual area is defined as.
6. defect analysis method as claimed in claim 3, it is characterised in that the defect of n-th layer film is thin with N-1 layers
The defect of film is carried out after coordinate superposition, then the defect of n-th layer film is carried out into coordinate with the workspace of M layer films is superimposed,
Show that the defect of n-th layer film falls into the workspace of M layer films the quantity of the defect that can kill wafer yield to be measured.
7. defect analysis method as claimed in claim 6, it is characterised in that judge that the defect of n-th layer film falls into M layers thin
Whether the quantity of defect of wafer yield to be measured can be killed in the workspace of film beyond preassigned, if exceeding preassigned,
Wafer to be measured is scrapped, if without departing from preassigned, carrying out follow-up production.
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| CN201310444792.7A CN104465434B (en) | 2013-09-23 | 2013-09-23 | Defect analysis method |
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| CN104465434A CN104465434A (en) | 2015-03-25 |
| CN104465434B true CN104465434B (en) | 2017-07-11 |
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| US9940704B2 (en) * | 2015-06-19 | 2018-04-10 | KLA—Tencor Corporation | Pre-layer defect site review using design |
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| CN103187329A (en) * | 2011-12-28 | 2013-07-03 | 无锡华润上华科技有限公司 | Analytical method of wafer yield |
| CN103187343A (en) * | 2011-12-28 | 2013-07-03 | 敖翔科技股份有限公司 | Intelligent defect diagnosis method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102129164B (en) * | 2010-01-15 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Method and system for judging mask defects |
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|---|---|---|---|---|
| CN1521822A (en) * | 2003-01-29 | 2004-08-18 | 力晶半导体股份有限公司 | Defect detecting parametric analysis method |
| CN1677637A (en) * | 2004-03-29 | 2005-10-05 | 力晶半导体股份有限公司 | Method for detecting again fault |
| CN1845305A (en) * | 2005-04-08 | 2006-10-11 | 力晶半导体股份有限公司 | Wafer fault detecting method and system and storage media |
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| CN103187329A (en) * | 2011-12-28 | 2013-07-03 | 无锡华润上华科技有限公司 | Analytical method of wafer yield |
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