CN104461758B - A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings - Google Patents
A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings Download PDFInfo
- Publication number
- CN104461758B CN104461758B CN201410628863.3A CN201410628863A CN104461758B CN 104461758 B CN104461758 B CN 104461758B CN 201410628863 A CN201410628863 A CN 201410628863A CN 104461758 B CN104461758 B CN 104461758B
- Authority
- CN
- China
- Prior art keywords
- cache
- streamline
- hit
- vacation
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings, processing method includes：" vacation hit " state, access result of the illegal command that mark is emptied by streamline to cache are defined first；Cache does not ensure that instruction code or data word are correct under " vacation hit " state, directly exports the corresponding cache information of reference address；Streamline empty signal is directly acted on into command cache in " vacation hit " state fetching operation, selection " vacation hit " state when nullified instruction accesses cache；When abnormality processing starts, control data cache is selected using the "or" logic of streamline empty signal and memory access level invalidated identification signal；During abnormal generation, cache enters " vacation hit " state, streamline is continued propulsion.The present invention discloses the structure of the application abnormality eliminating method.The present invention can accelerate abnormality processing speed, improve the real-time of system.
Description
Technical field
The present invention relates to the risc processor of Harvard structure the knot of streamline can be quickly emptied when carrying out abnormality processing
Structure and method, specially a kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings.
Background technology
Current high-performance microprocessor is generally used as the buffering of data and instruction using the multistage cache of stratification, with
Reduce the speed difference between processor and memory.Wherein, first order cache has the access delay of very little, substantially with
The speed of processor is consistent, in order to obtain the concurrent access of instruction and data, and it would generally be divided into independent command cache
With data cache, i.e., so-called Harvard structure；Second level cache typically uniformly stores together instruction and data, and it can be with
Can also be outside piece in piece；In following high-end designs, the third level cache of Large Copacity is integrated in also have very much in piece can
A kind of universal technological means can be turned into.But in any case, one-level cache missing is the important of influence processor performance all the time
Factor, during this influence not only shows computing device normal function, and is also manifested by its processing abnormal conditions
Mode on.For the risc microcontroller of current most main flows, they typically all use precise abnormal processing
Mode, i.e., when occurring abnormal, it is ensured that all instructions before exceptional instructions all successful executions, and after exceptional instructions
The instruction of all entrance streamlines can not all be performed, it is necessary to be cleared；This preprocessor just takes new at abnormal entry address
Instruct and start to perform abnormality processing subprogram.In streamline cleanup process, due to potential cache missings, it is possible to lead
Whole streamline is caused to be blocked so that abnormality processing is also stagnated, the reality of final influence computer system processor anomalous event
Shi Xing.
In order to reduce the performance loss caused by cache missings, two are had been proposed from the aspect of architecture at present
Plant technological means：(1) non-obstruction cache technologies, that is, when occurring cache missings, streamline is not blocked, and can continue executing with it
Follow-up unrelated instruction, the expense of cache missings is hidden with this.It stores missing by one special " miss queue "
Instruction, until the data block of missing is read back from main memory, therefore the periodicity that cache missings can be hidden refers to depending on missing
Make the bar number of follow-up independent instructions.Obviously, this structure contributes to performance boost in computing device normal function,
But of no avail in abnormality processing, because the subsequent instructions of missing instruction will be cleared out by streamline, themselves is simultaneously
The effective execution time is not take up, the expense of missing also can not be just hidden；On the other hand, non-obstruction is substantially a kind of out of order holds
Capable thought, for strict guarantee instruction sequences it is precise abnormal for, only can increase the complexity of control.(2) prefetch
Cache technologies, it by excite in advance in the future issuable cache lack behavior, make missing processing with before missing instruction
Other executing instructions so that hide cache missing expense.In order to realize pre-fetch function, it needs " memory reference
Predict table " and " prefetching queue " two hardware logics.The fetching address produced every time using branch predictor is gone to access memory
Reference prediction table, if occurrence, then illustrates that its corresponding instruction will be performed, is then put into the instruction and prefetches queue
In, lacked with triggering potential cache in advance.Regrettably, the technology is also only applicable to the feelings of computing device normal function
Condition, effect is not gathered when carrying out abnormality processing, because anomalous event is rare chance event, without statistical property,
The fetching address that so branch predictor is produced is when accessing memory reference prediction table, it is likely that without occurrence, and can not
Which bar instruction is predicted will perform, and potential cache missings behavior finally also can not be just triggered in advance.
How effectively to reduce cache missings expense, be rapidly performed by abnormality processing, be the certainty of real-time computer system
It is required that.However, both the above technology is directed to the processing of anomalous event, streamline stops caused by being still unavoidable from cache missings
, through retrieving pertinent literature, at present also without the method that can solve the problem very well.
The content of the invention
For problems of the prior art, the present invention provides a kind of by being set in conventional block type cache
" vacation hit " state eliminates the pipeline stall caused by the cache of illegal command accesses missing, does not increase additional complexity
Hardware logic be that quickly can empty streamline in accidental anomalous event, so as to accelerate the speed of abnormality processing, carry
The quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings of high computer system real-time.
The quick abnormality eliminating method for emptying streamline of present invention tolerance cache missings comes real by the following technical programs
It is existing：
First, cache hit decision logic is changed：Definition " vacation hit " state, identify by streamline empty it is invalid
Instruct the access result to cache；
Then, the behavior of cache under " vacation hit " state is defined：Cache to streamline without providing correct instruction code
Or data word, directly the corresponding cache information of reference address is exported；
Secondly, the Pipeline control of command cache " vacation hit " state is realized：The stream for generating processor in fetching operation
Waterline empty signal directly acts on command cache, current period illegal command is selected " vacation life when accessing cache
In " state；
Again, the Pipeline control of data cache " vacation hit " state is realized：When abnormality processing starts, processing is used
The "or" logic of the streamline empty signal of device generation and memory access level invalidated identification signal is used as data cache " vacation lives
In " selection of state control；
Finally, in the case where occurring exception, cache enters " vacation hit " state, directly returns data to streamline,
Neither ensure the correctness of data nor send access request, and then cause streamline to continue to promote.
The instruction of described abnormality processing includes the instruction for accessing data cache and subsequent cycle accesses data
Cache instruction.
The streamline empty signal of processor generation is acted on after the pipelining-stage of current all instructions, by previous pipelining-stage
Invalidated identification signal transmitted to latter pipelining-stage.
Saving scene operation is carried out before described abnormality processing first, then by streamline empty signal to exceptional instructions
All instructions afterwards are identified；All instructions after described exceptional instructions are included from fetching level to memory access level
Instruction.
Described illegal command includes correspondence decoding level, register access level and the instruction for performing level.
The quick exception handling structure for emptying streamline of present invention tolerance cache missings comes real by the following technical programs
It is existing：Including can be identified for that hit decision logic unit of the illegal command emptied by streamline to cache access result, flowing water
The instruction control that the streamline empty signal that can generate processor in the operation of line fetching directly acts on command cache is single
Member, and the streamline empty signal and memory access level that can generate processor during pipeline-exception processing beginning are invalid
The "or" logic of id signal selects the DCU data control unit of control, described hit decision logic unit as data cache
The illegal command of mark can directly be exported cache information by cache.
The described hit decision logic list that can be identified for that the illegal command that is emptied by streamline to cache access result
Member includes MUX and its selection logic unit.
Compared with prior art, the present invention is completely eliminated due to caused by the potential cache access missing of illegal command
Pipeline stall phenomenon, accelerates the speed of abnormality processing, and beneficial technique effect is as follows：
(1) " vacation hit " mechanism creates the zero-waiting of illegal command in a pipeline.For current Electrosurgical treatment equipment
For, cache missings at least need tens up to a hundred clock cycle, but " vacation is hit " nullified access instructed to cache is not
Missing behavior is produced, so as to avoid the wait of streamline.
(2) system power dissipation is reduced." vacation hit " does not send out access request, it is to avoid it is unnecessary that illegal command is carried out to memory
Access operation, so as to reduce the power dissipation overhead of whole system.
(3) processing capability in real time of computer system is improved.When external interrupt or internal exception event occur, refer to
Make streamline to be emptied and response abnormality processing immediately by quick, effectively enhance the real-time of computer system.
(4) present invention is more suitable for the microprocessor Design of depth flowing water.The flowing water series of processor is more, abnormal to occur
When need the instruction that empties more, wherein access instruction causes the expense of pipeline stall will be bigger due to cache missings,
For growing number of invalid access instruction in deep streamline, the effect of " vacation hit " tactful zero-overhead characteristic will be apparent from.
(5) control structure of the invention is simple, except the MUX and its selection logic of increase " vacation hit " state
Outside without other hardware resources.
Brief description of the drawings
Fig. 1 realizes the control structure block diagram of rapid abnormal processing for the present invention；
Fig. 2 is the conventional RISC processor timing diagram that streamline is emptied when carrying out abnormality processing；
Fig. 3 is the present invention timing diagram that streamline is emptied when carrying out abnormality processing.
Embodiment
With reference to specific embodiment, the present invention is described in further detail, it is described be explanation of the invention and
It is not to limit.
The present invention is main in exception handling procedure to include following aspect：
First, cache hit decision logic is changed.Generally, cache access result can only be in mutual exclusion
Two states, i.e., " hit " state or " missing " state, the cleanup process of streamline when we are directed to abnormality processing, then specially
A kind of " vacation hit " state of definition, to identify the access result of illegal command that those are emptied by streamline to cache.
Second, define the behavior of cache under " vacation hit " state.Because the illegal command in streamline can not finally update
Instruction obtained by any status information of processor, therefore their access cache will not be by pipeline decoding, resulting number
According to also will not being processed or write back in register file；That is, for these illegal commands, cache need not give flowing water
Line provides correct instruction code or data word.Then, " vacation hit " state can be realized as " hit " state completely, this
When cache directly the corresponding cache information of reference address is exported, due to not sending out access request, so the stream that would not pause
Waterline；Unlike unique, under " vacation hit " state, cache and without ensureing instruction or data of the output to streamline
Correctness.
3rd, realize the Pipeline control of command cache " vacation hit " state.Accident occurs every time and exception is carried out
During processing, processor can all generate a streamline empty signal, for controlling to come into flowing water after cancellation exceptional instructions
The execution of all instructions of line；The entry address of abnormality processing is generated simultaneously, and carries out fetching to fetching level in the next cycle.By
Just operated in current period in fetching level in access instruction cache fetching for existing one, and the instruction is taken by streamline
Disappear the illegal command of execution, however, next cycle carries out the fetching operation of exception process entry address, the instruction is effective
, therefore, the streamline empty signal of generation only maintains a cycle, and the signal will bear directly against command cache, makes current
Cycle illegal command can select " vacation hit " state when accessing cache.
4th, realize the Pipeline control of data cache " vacation hit " state.During generation anomalous event, current period
Bar instruction is likely to access data cache, can cancel the ineffective access of the illegal command by streamline empty signal,
And select " vacation hit " state；But certain instruction is there is likely to be in streamline and does not currently access data cache, subsequent cycle
It just starts to access data cache situation, then only maintain the streamline empty signal of current a cycle to will be unable to this
Instruction carries out invalidated identification.Therefore, when abnormality processing starts, the streamline empty signal of generation, which is once acted on, currently to be owned
After the pipelining-stage of instruction, we must also allow the invalidated identification signal of previous pipelining-stage to be transmitted to latter pipelining-stage, that
When instruction is advanced to memory access level and starts to access data cache, the invalidated identification of memory access level is delivered to
Signal can then control access of the instruction to data cache to be in " vacation is hit " state just.So, emptied using streamline
Signal and the invalidated identification signal or logic of memory access level are controlled as the selection of data cache " vacation is hit " state.
Referring to Fig. 1, for first-level instruction cache and data cache, their tag array and data array is by simultaneously
Capable access, the tag values read from tag array, which are used to hit, to be judged, if hit, the data values read from data array
Streamline can be returned to directly as hit word to be handled；Else if lacking, then deposited to two grades of cache or outside
Reservoir sends access request, and now whole streamline is stalled.When memory access is completed, memory access result memdata is returned
To streamline, it is set normally to promote while decontroling streamline.As an example, seven grades of flowing structures are illustrated in figure, wherein
Abnormality processing level specially internal accident or external break events are handled.When there is anomalous event, first
It is saving scene operation, then generation empties the control signal All_flush of streamline, for all after exceptional instructions
Instruction (including from fetching level to the instruction of memory access level) is identified, and shows that they have turned into from this point on invalid, and
And the invalidated identification per first-level instruction also transmits a downward pipelining-stage；At the same time, generation exception process entry address is taken
Refer to level, to instruct it to carry out the fetching of new command in the next cycle.Due to current period fetching level and the nothing of memory access level
Effect instruction accesses cache, and other illegal commands (correspondence decoding level, register access level and the instruction for performing level) exist
Subsequent cycle may also need the access into line storage, in order to avoid potential cache is lacked and causes the pause of streamline,
The present invention adds the state mhit of one " vacation hit " for cache hit decision logic.In computing device normal function
When, cache either in hit condition hit or is in miss status miss, and only in the case where occurring exception,
Cache can just enter " vacation hit " state mhit, and now the data values of data array are directly returned to streamline by cache, and
The correctness of the value need not be ensured, it will not also send access request, therefore streamline can make smooth advances.For instruction
For cache, the signal ici_inull of control mhit states arises directly from streamline empty signal All_flush；For number
For cache, the signal dci_inull of control mhit states then comes from All_flush signals and memory access level
Invalidated identification signal be M_flush's or logic.
Referring to Fig. 2, the digitized representation in the upper right corner instructs sequence number in figure, and inst represents that icache returns to the finger of streamline
Order, data represents that dcache returns to the data of streamline, and F, D, A, E, M, X, W represent seven pipelining-stages respectively.In instruction 1
X grades (i.e. abnormality processing levels) detect abnormal and start to process, produce the signal All_flush for emptying streamline, identify flowing water
The ineffectivity of all instructions in line.Now instruction 6 and instruction 2 are accessing icache and dcache respectively, and all there occurs scarce
Lose, it is necessary to carry out access request, then whole streamline is all deadlocked.Until the instruction and data of missing is all returned, stream
Waterline is just promoted, it is assumed that instruction 2, instruction 3 and instruction 100 are all load instructions, now exception process entry address (instruction 100)
Start to carry out fetching at F grades；Dcache is accessed at M grades yet with instruction 3 and missing behavior is there occurs again, then whole stream
Waterline is deadlocked again.Arrow in instruction represents that the instruction being delivered to when streamline is emptied in corresponding pipelining-stage is marked as
It is invalid, but the cache of exactly this illegal command missing behaviors result in unnecessary pipeline stall, have impact on exception
The speed of reason.
Referring to Fig. 3, when instructing 1 X levels progress abnormality processing, streamline empty signal All_flush promotes now
Instruction 6 and instruct 2 cache to access all to enter " vacation hit " state, and subsequent instructions 3 when accessing data cache then to
The pipelining-stage id signal M_flush transmitted afterwards is controlled and is entered " vacation hit " state.Cache is direct under " vacation hit " state
The cache size in its data array is returned to streamline, and without ensureing the correctness of these values, because streamline is identified
These illegal commands, will not enter row decoding to the cache instructions returned or data and write back." vacation hit " does not produce memory access please
Ask, without the streamline that pauses, hence it is evident that accelerate exception handling procedure.
The present invention has been successfully applied to a kind of risc microcontroller with seven grades of flowing water of compatible SPARC V8 frameworks
In, and have been realized in many money SOC products.Cache " vacation hit " control strategy of the present invention, only needs increase " vacation hit " shape
The MUX of state and control logic is selected accordingly, design structure is simple, it is easy to implement.Exception is carried out in processor
During reason, the structure can avoid flowing caused by accessing missing due to the cache of illegal command in streamline cleanup process completely
Waterline pauses, and realizes the zero-waiting of streamline without carrying out access request, hence it is evident that accelerate the speed of abnormality processing, be conducive to
Improve the real-time of whole system.
Claims (7)
1. a kind of quick abnormality eliminating method for emptying streamline of tolerance cache missings, it is characterised in that：
First, cache hit decision logic is changed：Definition " vacation hit " state, identifies the illegal command emptied by streamline
To cache access result；
Then, the behavior of cache under " vacation hit " state is defined：Cache to streamline without providing correct instruction code or number
According to word, directly the corresponding cache information of reference address is exported；
Secondly, the Pipeline control of command cache " vacation hit " state is realized：The streamline for generating processor in fetching operation
Empty signal directly acts on command cache, current period illegal command is selected " vacation hit " shape when accessing cache
State；
Again, the Pipeline control of data cache " vacation hit " state is realized：When abnormality processing starts, given birth to using processor
Into the "or" logic of streamline empty signal and memory access level invalidated identification signal be used as data cache " vacation is hit " shape
The selection control of state；
Finally, in the case where occurring exception, cache enters " vacation hit " state, directly returns data to streamline, neither
Ensure that the correctness of data does not also send access request, and then cause streamline to continue to promote.
2. the quick abnormality eliminating method for emptying streamline of tolerance cache missings according to claim 1, its feature exists
In：The instruction of described abnormality processing includes the instruction for accessing data cache and subsequent cycle accesses data cache's
Instruction.
3. the quick abnormality eliminating method for emptying streamline of tolerance cache missings according to claim 1 or 2, its feature
It is：The streamline empty signal of processor generation is acted on after the pipelining-stage of current all instructions, by previous pipelining-stage
Invalidated identification signal is transmitted to latter pipelining-stage.
4. the quick abnormality eliminating method for emptying streamline of tolerance cache missings according to claim 1, its feature exists
In：Saving scene operation is carried out before described abnormality processing first, then by streamline empty signal to exceptional instructions after
All instructions be identified；All instructions after described exceptional instructions include the finger from fetching level to memory access level
Order.
5. the quick abnormality eliminating method for emptying streamline of tolerance cache missings according to claim 1, its feature exists
In：Described illegal command includes correspondence decoding level, register access level and the instruction for performing level.
6. a kind of quick exception handling structure for emptying streamline of tolerance cache missings, it is characterised in that：Including can be identified for that by
The illegal command that streamline is emptied, can in the operation of streamline fetching to the hit decision logic unit of cache access result
The streamline empty signal that processor is generated directly acts on the instruction control unit of command cache, and pipeline-exception
The "or" of the streamline empty signal that processing can generate processor when starting and memory access level invalidated identification signal is patrolled
Collect the DCU data control unit that control is selected as data cache, the described illegal command energy for hitting decision logic unit marks
Enough cache information is directly exported by cache.
7. the quick exception handling structure for emptying streamline of tolerance cache missings according to claim 6, its feature exists
In：The described hit decision logic unit bag that can be identified for that the illegal command that is emptied by streamline to cache access result
Include MUX and its selection logic unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410628863.3A CN104461758B (en) | 2014-11-10 | 2014-11-10 | A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410628863.3A CN104461758B (en) | 2014-11-10 | 2014-11-10 | A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104461758A CN104461758A (en) | 2015-03-25 |
| CN104461758B true CN104461758B (en) | 2017-08-25 |
Family
ID=52907855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410628863.3A Active CN104461758B (en) | 2014-11-10 | 2014-11-10 | A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104461758B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105224412B (en) * | 2015-09-24 | 2017-12-05 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of accurate trap control structure of memory based on SPARCV8 processors and method |
| CN107688470B (en) * | 2016-12-23 | 2020-04-07 | 北京国睿中数科技股份有限公司 | Verification method and device for uncache data access |
| US10713053B2 (en) * | 2018-04-06 | 2020-07-14 | Intel Corporation | Adaptive spatial access prefetcher apparatus and method |
| CN108845832B (en) * | 2018-05-29 | 2023-05-30 | 西安微电子技术研究所 | Pipeline subdivision device for improving main frequency of processor |
| CN109992411B (en) * | 2019-02-18 | 2021-05-18 | 华夏芯（北京）通用处理器技术有限公司 | Method for realizing VLV access array capable of being released quickly |
| CN110457238B (en) * | 2019-07-04 | 2023-01-03 | 中国民航大学 | Method for slowing down GPU (graphics processing Unit) access request and pause when instructions access cache |
| CN111414321B (en) * | 2020-02-24 | 2022-07-15 | 中国农业大学 | Cache protection method and device based on dynamic mapping mechanism |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214146A (en) * | 2011-07-28 | 2011-10-12 | 中国人民解放军国防科学技术大学 | Step size adaptive Cache pre-fetching method and system |
| CN102841857A (en) * | 2012-07-25 | 2012-12-26 | 龙芯中科技术有限公司 | Processor, device and method for carrying out cache prediction |
| CN103294567A (en) * | 2013-05-31 | 2013-09-11 | 中国航天科技集团公司第九研究院第七七一研究所 | Precise abnormality processing method for single-emitting five-stage pipeline processor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070113055A1 (en) * | 2005-11-15 | 2007-05-17 | Dale Jason N | Apparatus and method for improving single thread performance through speculative processing |
| US7461239B2 (en) * | 2006-02-02 | 2008-12-02 | International Business Machines Corporation | Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines |
| US20140095847A1 (en) * | 2012-09-28 | 2014-04-03 | Doron Orenstein | Instruction and highly efficient micro-architecture to enable instant context switch for user-level threading |
-
2014
- 2014-11-10 CN CN201410628863.3A patent/CN104461758B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102214146A (en) * | 2011-07-28 | 2011-10-12 | 中国人民解放军国防科学技术大学 | Step size adaptive Cache pre-fetching method and system |
| CN102841857A (en) * | 2012-07-25 | 2012-12-26 | 龙芯中科技术有限公司 | Processor, device and method for carrying out cache prediction |
| CN103294567A (en) * | 2013-05-31 | 2013-09-11 | 中国航天科技集团公司第九研究院第七七一研究所 | Precise abnormality processing method for single-emitting five-stage pipeline processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104461758A (en) | 2015-03-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104461758B (en) | A kind of quick abnormality eliminating method and its processing structure for emptying streamline of tolerance cache missings | |
| US10831494B2 (en) | Event triggered programmable prefetcher | |
| EP1889152B1 (en) | A method and apparatus for predicting branch instructions | |
| KR101513953B1 (en) | Methods and apparatus to predict non-execution of conditional non-branching instructions | |
| US20050066131A1 (en) | Apparatus and method for loading data values | |
| CN102112966A (en) | Apparatus and methods for speculative interrupt vector prefetching | |
| CN107851020A (en) | Equipment and processing framework for command memory efficiency | |
| CN105511838A (en) | Processor and executing method of same | |
| US9891972B2 (en) | Lazy runahead operation for a microprocessor | |
| KR100496944B1 (en) | Controlling instruction translation using dynamic feedback | |
| US9870226B2 (en) | Control of switching between executed mechanisms | |
| TW201439904A (en) | Managing potentially invalid results during runahead | |
| CN103870240A (en) | Instruction categorization for runahead operation | |
| US20140129805A1 (en) | Execution pipeline power reduction | |
| US6006325A (en) | Method and apparatus for instruction and data serialization in a computer processor | |
| CN101501635B (en) | Methods and apparatus for reducing lookups in a branch target address cache | |
| CN103140847B (en) | Regulate atomic memory operation with the attack preventing denial of service | |
| CN106843816A (en) | A kind of branch prediction control method and device | |
| CN103294567B (en) | A kind of precise abnormal disposal route of single transmit Pyatyi flow water treater | |
| JPH0816394A (en) | Apparatus and method for prefetch for prefetching of instruction code from system memory | |
| JP3762816B2 (en) | System and method for tracking early exceptions in a microprocessor | |
| CN1306411C (en) | Device, method and system for processing events in processor | |
| US5987599A (en) | Target instructions prefetch cache | |
| CN106383926A (en) | Instruction prefetching method based on Cortex-M series processor and circuit | |
| US8266414B2 (en) | Method for executing an instruction loop and a device having instruction loop execution capabilities |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |