CN104461758A - Exception handling method and structure tolerant of missing cache and capable of emptying assembly line quickly - Google Patents
Exception handling method and structure tolerant of missing cache and capable of emptying assembly line quickly Download PDFInfo
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Abstract
The invention provides an exception handling method and structure tolerant of missing cache and capable of emptying an assembly line quickly. The exception handling method includes the steps that firstly, a false hit state is defined, and the access result of the cache by invalid commands emptied by the assembly line is marked; correct command codes or data words are not guaranteed by the cache under the false hit state, and the corresponding cache information of access addresses is output directly; an assembly line emptying signal is directly acted on the command cache in the command taking operation in the false hit state to enable the false hit state to be selected when the invalid commands have access to the cache; when exception handling begins, data cache is selected and controlled through the assembly line emptying signal and the or logic of a storage access level invalid marking signal; when an exception occurs, the cache enters the false hit state to enable the assembly line to advance continuously. The invention further discloses the structure applying the exception handling method. By means of the exception handling method and structure tolerant of missing the cache and capable of emptying the assembly line quickly, the exception handling speed can be increased, and the real-time performance of the system is improved.
Description
Technical field
The risc processor that the present invention relates to Harvard structure can empty structure and the method for streamline fast when carrying out abnormality processing, be specially abnormality eliminating method and process structure thereof that a kind of cache of tolerance disappearance empties streamline fast.
Background technology
Current high-performance microprocessor generally uses the multistage cache of stratification to be used as the buffering of data and instruction, to reduce the speed difference between processor and storer.Wherein, first order cache has very little access delay, is substantially consistent with the speed of processor, and in order to obtain the concurrent access of instruction and data, it can be divided into independently command cache and data cache usually, i.e. so-called Harvard structure; Second level cache generally stores together unified for instruction and data, and it can also can outside sheet in sheet; In the high-end designs in future, jumbo third level cache is integrated in sheet and also probably becomes a kind of general technological means.But in any case, the disappearance of one-level cache is the key factor affecting processor performance all the time, this impact not only shows that processor performs in the process of normal function, but also shows in the mode of its process abnormal conditions.For the risc microcontroller of current most main flow, they generally all adopt precise abnormal processing mode, namely when occurring abnormal, all instructions all successful execution before ensureing exceptional instructions, and all instructions entering streamline all can not perform after exceptional instructions, must be cleared; This preprocessor just from abnormal entry address place get new instruction and execute exception process subroutine.In streamline cleanup process, because potential cache lacks, whole streamline just may be caused to get clogged, abnormality processing is also stagnated, finally affect the real-time of computer system processor anomalous event.
The performance loss caused is lacked in order to reduce cache, two kinds of technological means have been proposed at present: (1) unblock cache technology the aspect of architecture, when namely there is cache disappearance, streamline does not get clogged, can continue to perform its follow-up irrelevant instruction, carry out the expense of hiding cache disappearance with this.It stores disappearance instruction by special " miss queue ", until the data block of disappearance is read back from main memory, therefore cache lack the periodicity that can be hidden and depends on the number lacking the follow-up independent instructions of instruction.Obviously, this structure contributes to performance boost when processor performs normal function, but of no avail in abnormality processing, because the subsequent instructions of disappearance instruction all will be cleared out by streamline, they itself do not take the effective execution time, just cannot hide the expense of disappearance yet; On the other hand, unblock is a kind of thought of Out-of-order execution in essence, precise abnormal for strict guarantee instruction sequences, only can increase the complexity of control.(2) look ahead cache technology, it lacks behavior by exciting issuable cache in the future in advance, makes other executing instructions before disappearance process and disappearance instruction, thus hides the expense of cache disappearance.In order to realize pre-fetch function, it needs " memory reference caluclate table " and " prefetch queue " two hardware logics.Access memory reference caluclate table is removed in the fetching address that each use branch predictor produces, if there is occurrence, then illustrates that its corresponding instruction will perform, so prefetch queue is put in this instruction, to trigger potential cache disappearance in advance.Regrettably, this technology is also only applicable to the situation that processor performs normal function, effect is not gathered when carrying out abnormality processing, this is because anomalous event is rare random occurrence, do not have statistical property, the fetching address of so branch predictor generation, when accessing memory reference caluclate table, does not probably have occurrence, and can not predict to perform any bar instruction, finally also just cannot trigger potential cache in advance and lack behavior.
How effectively reducing cache to lack expense, carry out abnormality processing fast, is the inevitable requirement of real-time computer system.But above two kinds of technology, for the process of anomalous event, still cannot avoid cache to lack the pipeline stall caused, through retrieval pertinent literature, there is no the method that can solve this problem very well at present yet.
Summary of the invention
For problems of the prior art, the invention provides a kind of cache access eliminated because of illegal command by arranging " false hit " state in the block type cache of routine and lack the pipeline stall caused, namely the hardware logic not increasing additional complexity can empty streamline fast in accidental anomalous event, thus accelerate the speed of abnormality processing, the tolerance cache disappearance improving computer system real-time empties abnormality eliminating method and the process structure thereof of streamline fast.
The present invention tolerates that cache lacks the abnormality eliminating method emptying streamline fast and is achieved through the following technical solutions:
First, the hit decision logic of amendment cache: definition " false hit " state, identifies the illegal command that emptied by streamline to the access result of cache;
Then, the behavior of cache under definition " false hit " state: cache information corresponding for reference address, without the need to providing correct order code or data word to streamline, directly exports by cache;
Secondly, realizing the Pipeline control of command cache " false hit " state: in fetch operation, the streamline that processor generates is emptied signal and directly act on command cache, enabling current period illegal command select " false hit " state when accessing cache;
Again, realize the Pipeline control of data cache " false hit " state: when abnormality processing starts, the "or" logic that the streamline that purpose processor is generated empties signal and memory access level invalidated identification signal controls as the selection of data cache " vacation is hit " state;
Finally, data are directly returned to streamline, neither ensure that the correctness of data does not also send access request, and then make streamline continue to advance by state that when occurring abnormal, cache enters " false hit ".
The instruction of described abnormality processing comprises just in the instruction of visit data cache and the instruction of subsequent cycle visit data cache.
The streamline that processor generates empties signal function after the pipelining-stage of current all instructions, by the pipelining-stage transmission backward of the invalidated identification signal of previous pipelining-stage.
First carry out saving scene operation before described abnormality processing, then empty control signal by streamline and all instructions after exceptional instructions are identified; All instructions after described exceptional instructions comprise the instruction from fetching level to memory access level.
Described illegal command comprises the instruction of corresponding decode stage, register access level and execution level.
The present invention tolerates that the exception handling structure that cache disappearance empties streamline is fast achieved through the following technical solutions: comprise the illegal command that can identify and be emptied by streamline to the hit decision logic unit of the access result of cache, the streamline that processor generates can be emptied the instruction control unit that signal directly acts on command cache in streamline fetch operation, and the pipeline-exception process "or" logic that the streamline that processor generates can be emptied signal and memory access level invalidated identification signal when starting selects as data cache the DCU data control unit that controls, cache information directly can be exported by cache by the illegal command of described hit decision logic unit marks.
Described can identifying is comprised MUX and selection logical block thereof by the hit decision logic unit of illegal command to the access result of cache that streamline empties.
Compared with prior art, the cache access that the present invention completely eliminates because illegal command is potential lacks the pipeline stall phenomenon caused, and accelerate the speed of abnormality processing, useful technique effect is as follows:
(1) " false hit " mechanism creates illegal command zero-waiting in a pipeline.For current Electrosurgical treatment equipment, cache disappearance at least needs tens up to a hundred clock period, but " false hit " nullified instruction does not produce disappearance behavior to the access of cache, thus avoids the wait of streamline.
(2) system power dissipation is reduced." false hit " does not send out access request, avoids illegal command to carry out unnecessary accessing operation to storer, thus reduces the power dissipation overhead of whole system.
(3) improve the processing capability in real time of computer system.When external interrupt or internal exception event occur, instruction pipelining can be emptied and response abnormality process immediately fast, effectively enhances the real-time of computer system.
(4) the present invention is more suitable for the microprocessor Design of degree of depth flowing water.The flowing water progression of processor is more, the instruction that during abnormal generation, needs empty is more, wherein access instruction causes the expense of pipeline stall will be larger due to cache disappearance, for the invalid access instruction be on the increase in dark streamline, the effect of " false hit " tactful zero-overhead characteristic will be more obvious.
(5) control structure of the present invention is simple, except the MUX that increases " false hit " state and the hardware resource selecting without the need to other except logic thereof.
Accompanying drawing explanation
Fig. 1 is the control structure block diagram that the present invention realizes rapid abnormal process;
Fig. 2 is the conventional RISC processor sequential chart that streamline empties when carrying out abnormality processing;
Fig. 3 is the present invention's sequential chart that streamline empties when carrying out abnormality processing.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in further detail, and the explanation of the invention is not limited.
The present invention mainly comprise in exception handling procedure following in:
First, the hit decision logic of cache is revised.Generally, the access result of cache only can be in the two states of mutual exclusion, i.e. " hit " state or " disappearance " state, we are for the cleanup process of streamline during abnormality processing, special definition one " false hit " state again, in order to identify those illegal commands emptied by streamline to the access result of cache.
The second, the behavior of cache under definition " false hit " state.Because the illegal command in streamline finally can not any status information of update processors, the instruction that therefore their access cache obtain can not by pipeline decoding, and the data obtained also can not be processed or write back in register file; That is, for these illegal commands, cache is without the need to providing correct order code or data word to streamline.So " false hit " state can equally with " hit " state realize completely, and now cache information corresponding for reference address directly exports by cache, owing to not sending out access request, so the streamline that would not pause; Uniquely unlike, under " false hit " state, cache also need not ensure to export to the instruction of streamline or the correctness of data.
3rd, realize the Pipeline control of command cache " false hit " state.The event that at every turn meets accident when carrying out abnormality processing, processor all can generate a streamline and empty signal, has entered the execution of all instructions of streamline after being used for controlling to cancel exceptional instructions; Generate the entry address of abnormality processing simultaneously, and carry out fetching in the next cycle to fetching level.Because current period has one just at the fetch operation of access instruction cache in fetching level, and the illegal command that this instruction is cancelled by streamline, but, next cycle carries out the fetch operation of exception process entry address, this instruction is but effective, and therefore, the streamline of generation empties signal and only maintains one-period, this signal will directly act on command cache, make current period illegal command can select " false hit " state when accessing cache.
4th, realize the Pipeline control of data cache " false hit " state.When there is anomalous event, a current period instruction, probably just at visit data cache, empties by streamline the ineffective access that signal can cancel this illegal command, and selects " false hit " state; But also may there is certain the current non-visit data cache of instruction in streamline, subsequent cycle it just start the situation of visit data cache, the streamline so only maintaining current one-period empties signal and cannot carry out invalidated identification to this instruction.For this reason, when abnormality processing starts, the streamline generated empties signal once after acting on the pipelining-stage of current all instructions, we also must allow the invalidated identification signal pipelining-stage transmission backward of previous pipelining-stage, so when instruction is advanced to memory access level and start visit data cache, the invalidated identification signal being delivered to memory access level then just can control the access of this instruction to data cache and be in " false hit " state.So, use that streamline empties the invalidated identification signal of signal and memory access level or logic to control as the selection of data cache " vacation is hit " state.
See Fig. 1, for first-level instruction cache and data cache, their tag array and data array are by the access walked abreast, from tag array read tag value for hitting judgement, if hit, then the data value read from data array directly can return to streamline as hit word and process; Lack else if, then send access request to secondary cache or external memory storage, now whole streamline is deadlocked.When memory access completes, memory access result memdata is returned to streamline, decontrol streamline simultaneously and make it normally advance.Exemplarily, illustrate seven grades of flowing structures in figure, abnormality processing level wherein processes inner unscheduled event or external break events specially.When there is anomalous event, first be saving scene operation, then the control signal All_flush emptying streamline is generated, all instructions (comprising the instruction from fetching level to memory access level) after being used for exceptional instructions identify, show that they have become from this moment invalid, and the invalidated identification of every first-level instruction is also by a downward pipelining-stage transmission; Meanwhile, generate exception process entry address to fetching level, carry out the fetching of new instruction to instruct it in the next cycle.Because the illegal command of current period fetching level and memory access level accesses cache, and other illegal command (instruction of corresponding decode stage, register access level and execution level) also may need at subsequent cycle the access carrying out storer, lack in order to avoid potential cache and cause the pause of streamline, the present invention is the state mhit that the hit decision logic of cache adds " false hit ".When processor performs normal function, cache is in hit condition hit or is in miss status miss, and only when occurring abnormal, cache just can enter " false hit " state mhit, now the data value of data array is directly returned to streamline by cache, and without the need to ensureing the correctness of this value, it also can not send access request, therefore streamline can make smooth advances.For command cache, the signal ici_inull of control mhit state directly comes from streamline and empties signal All_flush; For data cache, the signal dci_inull of control mhit state then come from All_flush signal and memory access level invalidated identification signal M_flush's or logic.
See the digitized representation instruction sequence number in the upper right corner in Fig. 2, figure, inst represents that icache returns to the instruction of streamline, and data represents that dcache returns to the data of streamline, and F, D, A, E, M, X, W represent seven pipelining-stages respectively.Exception detected in the X level (i.e. abnormality processing level) of instruction 1 and start process, producing the signal All_flush emptying streamline, the ineffectivity of all instructions in identification pipeline.Now instruction 6 and instruction 2 respectively at access icache and dcache, and all there occurs disappearance, need to carry out access request, so whole streamline is all deadlocked.By the time when the instruction and data lacked all returns, streamline just advances, and presumptive instruction 2, instruction 3 and instruction 100 are all load instructions, and now exception process entry address (instruction 100) beginning carries out fetching in F level; But because instruction 3 is at M level access dcache and there occurs again disappearance behavior, so whole streamline is deadlocked again.Arrow in instruction when representing that streamline empties the instruction be delivered in corresponding pipelining-stage be marked as invalid, but just this illegal command cache lack behavior result in unnecessary pipeline stall, have impact on the speed of abnormality processing.
See Fig. 3, when the X level of instruction 1 carries out abnormality processing, streamline empties signal All_flush and impels the cache of instruction 6 now and instruction 2 access all to enter " false hit " state, and subsequent instructions 3 is then controlled by the pipelining-stage id signal M_flush transmitted backward when visit data cache and enters " false hit " state.Cache returns the cache size in its data array under " false hit " state directly to streamline, and the correctness of these values need not be ensured, because streamline has identified these illegal commands, the instruction that can not return cache or data have been carried out decoding and have write back." false hit " does not produce access request, without the need to the streamline that pauses, obviously accelerates exception handling procedure.
The present invention has been successfully applied to having in the risc microcontroller of seven grades of flowing water of a kind of compatible SPARC V8 framework, and has achieved many moneys SOC product.Cache of the present invention " false hit " control strategy, only need the MUX of increase " false hit " state and select steering logic accordingly, project organization is simple, easy to implement.When processor carries out abnormality processing, this structure can avoid the pipeline stall caused due to the cache access disappearance of illegal command in streamline cleanup process completely, the zero-waiting of streamline is realized without the need to carrying out access request, obviously accelerate the speed of abnormality processing, be conducive to the real-time improving whole system.
Claims (7)
1. tolerate that cache disappearance empties an abnormality eliminating method for streamline fast, it is characterized in that:
First, the hit decision logic of amendment cache: definition " false hit " state, identifies the illegal command that emptied by streamline to the access result of cache;
Then, the behavior of cache under definition " false hit " state: cache information corresponding for reference address, without the need to providing correct order code or data word to streamline, directly exports by cache;
Secondly, realizing the Pipeline control of command cache " false hit " state: in fetch operation, the streamline that processor generates is emptied signal and directly act on command cache, enabling current period illegal command select " false hit " state when accessing cache;
Again, realize the Pipeline control of data cache " false hit " state: when abnormality processing starts, the "or" logic that the streamline that purpose processor is generated empties signal and memory access level invalidated identification signal controls as the selection of data cache " vacation is hit " state;
Finally, data are directly returned to streamline, neither ensure that the correctness of data does not also send access request, and then make streamline continue to advance by state that when occurring abnormal, cache enters " false hit ".
2. tolerance cache disappearance according to claim 1 empties the abnormality eliminating method of streamline fast, it is characterized in that: the instruction of described abnormality processing comprises just in the instruction of visit data cache and the instruction of subsequent cycle visit data cache.
3. tolerance cache disappearance according to claim 1 and 2 empties the abnormality eliminating method of streamline fast, it is characterized in that: the streamline that processor generates empties signal function after the pipelining-stage of current all instructions, by the pipelining-stage transmission backward of the invalidated identification signal of previous pipelining-stage.
4. tolerance cache disappearance according to claim 1 empties the abnormality eliminating method of streamline fast, it is characterized in that: before described abnormality processing, first carry out saving scene operation, then empty control signal by streamline and all instructions after exceptional instructions are identified; All instructions after described exceptional instructions comprise the instruction from fetching level to memory access level.
5. tolerance cache disappearance according to claim 1 empties the abnormality eliminating method of streamline fast, it is characterized in that: described illegal command comprises the instruction of corresponding decode stage, register access level and execution level.
6. tolerate that cache disappearance empties the exception handling structure of streamline fast for one kind, it is characterized in that: comprise the illegal command that can identify and be emptied by streamline to the hit decision logic unit of the access result of cache, the streamline that processor generates can be emptied the instruction control unit that signal directly acts on command cache in streamline fetch operation, and the pipeline-exception process "or" logic that the streamline that processor generates can be emptied signal and memory access level invalidated identification signal when starting selects as data cache the DCU data control unit that controls, cache information directly can be exported by cache by the illegal command of described hit decision logic unit marks.
7. tolerance cache disappearance according to claim 6 empties the exception handling structure of streamline fast, it is characterized in that: described can identifying is comprised MUX and selection logical block thereof by the hit decision logic unit of illegal command to the access result of cache that streamline empties.
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